[llvm] [AMDGPU] Handle True16 high-half 16-bit packing idiom with uniform operand (PR #211102)

[Zach Goldthorpe via llvm-commits]

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zGoldthorpe wrote:

I tried looking into this more deeply.
With the pattern
```
(i16 (EXTRACT_SUBREG (COPY_TO_REGCLASS $src2, VGPR_32), hi16))
```
it looks like the pattern just gets dropped completely (for having an empty set for the result type for `COPY_TO_REGCLASS`, apparently), which explains my earlier comment about the optimisations being undone.

If I help by annotating with
```
(i16 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS $src2, VGPR_32)), hi16))
```
the pattern is no longer dropped, but the input node to `EXTRACT_SUBREG` is not recognised as being divergent, so although it correctly copies the hi16 bits from a VGPR, these bits get copied into an SGPR, which is an invalid operand to `V_OR_B16_t16_e64`.

https://github.com/llvm/llvm-project/pull/211102