[llvm] [AMDGPU] Move VGPR, EU, and Wave Queries into TargetParser (PR #211312)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 22 09:46:46 PDT 2026
https://github.com/theSK2005 created https://github.com/llvm/llvm-project/pull/211312
Relocated VGPR, EU, and Wave queries into the public TargetParser. Part of resolving a comgr issue (https://github.com/ROCm/llvm-project/issues/3298) to reduce comgr-isa-metadata.def duplication. Followup for PR#209848.
Assisted by: Claude Code
>From e59bce90528a71c0b9e2a07d2e597a0ffc0b5e9f Mon Sep 17 00:00:00 2001
From: Soumil Kushwaha <Soumil.Kushwaha at amd.com>
Date: Tue, 21 Jul 2026 11:48:34 -0500
Subject: [PATCH 1/2] [AMDGPU] Move VGPR, EU, and Wave Queries into
TargetParser
Relocated VGPR, EU, and Wave queries into the public TargetParser. Part of resolving a comgr issue (ROCm#3298) to reduce comgr-isa-metadata.def duplication. Followup for PR#209848.
Assisted by: Claude Code
---
.../llvm/TargetParser/AMDGPUTargetParser.def | 30 ++--
.../llvm/TargetParser/AMDGPUTargetParser.h | 36 +++-
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 9 +-
llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp | 9 +-
llvm/lib/Target/AMDGPU/GCNSubtarget.cpp | 4 +-
llvm/lib/Target/AMDGPU/GCNSubtarget.h | 16 +-
llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 5 +-
llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp | 2 +-
.../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 132 ++++----------
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 30 +---
llvm/lib/TargetParser/AMDGPUTargetParser.cpp | 169 ++++++++++++++++++
.../TargetParser/TargetParserTest.cpp | 108 +++++++++++
12 files changed, 389 insertions(+), 161 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/AMDGPUTargetParser.def b/llvm/include/llvm/TargetParser/AMDGPUTargetParser.def
index c09bd25e55deb..99a098cf915e8 100644
--- a/llvm/include/llvm/TargetParser/AMDGPUTargetParser.def
+++ b/llvm/include/llvm/TargetParser/AMDGPUTargetParser.def
@@ -95,10 +95,10 @@ AMDGCN_GPU ("gfx904", GK_GFX904, Triple::AMDGPUSubArch904, ( 9, 0, 4),
AMDGCN_GPU ("gfx906", GK_GFX906, Triple::AMDGPUSubArch906, ( 9, 0, 6), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_SRAMECC)
AMDGCN_GPU ("gfx908", GK_GFX908, Triple::AMDGPUSubArch908, ( 9, 0, 8), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_SRAMECC)
AMDGCN_GPU ("gfx909", GK_GFX909, Triple::AMDGPUSubArch909, ( 9, 0, 9), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES)
-AMDGCN_GPU ("gfx90a", GK_GFX90A, Triple::AMDGPUSubArch90A, ( 9, 0, 10), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_SRAMECC)
+AMDGCN_GPU ("gfx90a", GK_GFX90A, Triple::AMDGPUSubArch90A, ( 9, 0, 10), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_SRAMECC|FEATURE_GFX90A_INSTS)
AMDGCN_GPU ("gfx90c", GK_GFX90C, Triple::AMDGPUSubArch90C, ( 9, 0, 12), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES)
-AMDGCN_GPU ("gfx942", GK_GFX942, Triple::AMDGPUSubArch942, ( 9, 4, 2), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_SRAMECC)
-AMDGCN_GPU ("gfx950", GK_GFX950, Triple::AMDGPUSubArch950, ( 9, 5, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_SRAMECC)
+AMDGCN_GPU ("gfx942", GK_GFX942, Triple::AMDGPUSubArch942, ( 9, 4, 2), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_SRAMECC|FEATURE_GFX90A_INSTS)
+AMDGCN_GPU ("gfx950", GK_GFX950, Triple::AMDGPUSubArch950, ( 9, 5, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_SRAMECC|FEATURE_GFX90A_INSTS)
AMDGCN_GPU ("gfx1010", GK_GFX1010, Triple::AMDGPUSubArch1010, (10, 1, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_WGP)
AMDGCN_GPU ("gfx1011", GK_GFX1011, Triple::AMDGPUSubArch1011, (10, 1, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_WGP)
AMDGCN_GPU ("gfx1012", GK_GFX1012, Triple::AMDGPUSubArch1012, (10, 1, 2), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_WGP)
@@ -110,23 +110,23 @@ AMDGCN_GPU ("gfx1033", GK_GFX1033, Triple::AMDGPUSubArch1033, (10, 3, 3)
AMDGCN_GPU ("gfx1034", GK_GFX1034, Triple::AMDGPUSubArch1034, (10, 3, 4), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
AMDGCN_GPU ("gfx1035", GK_GFX1035, Triple::AMDGPUSubArch1035, (10, 3, 5), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
AMDGCN_GPU ("gfx1036", GK_GFX1036, Triple::AMDGPUSubArch1036, (10, 3, 6), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx1100", GK_GFX1100, Triple::AMDGPUSubArch1100, (11, 0, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx1101", GK_GFX1101, Triple::AMDGPUSubArch1101, (11, 0, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx1100", GK_GFX1100, Triple::AMDGPUSubArch1100, (11, 0, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP|FEATURE_1536_VGPRS)
+AMDGCN_GPU ("gfx1101", GK_GFX1101, Triple::AMDGPUSubArch1101, (11, 0, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP|FEATURE_1536_VGPRS)
AMDGCN_GPU ("gfx1102", GK_GFX1102, Triple::AMDGPUSubArch1102, (11, 0, 2), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
AMDGCN_GPU ("gfx1103", GK_GFX1103, Triple::AMDGPUSubArch1103, (11, 0, 3), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
AMDGCN_GPU ("gfx1150", GK_GFX1150, Triple::AMDGPUSubArch1150, (11, 5, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx1151", GK_GFX1151, Triple::AMDGPUSubArch1151, (11, 5, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx1151", GK_GFX1151, Triple::AMDGPUSubArch1151, (11, 5, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP|FEATURE_1536_VGPRS)
AMDGCN_GPU ("gfx1152", GK_GFX1152, Triple::AMDGPUSubArch1152, (11, 5, 2), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
AMDGCN_GPU ("gfx1153", GK_GFX1153, Triple::AMDGPUSubArch1153, (11, 5, 3), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
AMDGCN_GPU ("gfx1154", GK_GFX1154, Triple::AMDGPUSubArch1154, (11, 5, 4), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
AMDGCN_GPU ("gfx1170", GK_GFX1170, Triple::AMDGPUSubArch1170, (11, 7, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
AMDGCN_GPU ("gfx1171", GK_GFX1171, Triple::AMDGPUSubArch1171, (11, 7, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
AMDGCN_GPU ("gfx1172", GK_GFX1172, Triple::AMDGPUSubArch1172, (11, 7, 2), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx1200", GK_GFX1200, Triple::AMDGPUSubArch1200, (12, 0, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx1201", GK_GFX1201, Triple::AMDGPUSubArch1201, (12, 0, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx1250", GK_GFX1250, Triple::AMDGPUSubArch1250, (12, 5, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_SRAMECC)
-AMDGCN_GPU ("gfx1251", GK_GFX1251, Triple::AMDGPUSubArch1251, (12, 5, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_SRAMECC)
-AMDGCN_GPU ("gfx1310", GK_GFX1310, Triple::AMDGPUSubArch1310, (13, 1, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx1200", GK_GFX1200, Triple::AMDGPUSubArch1200, (12, 0, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP|FEATURE_1536_VGPRS)
+AMDGCN_GPU ("gfx1201", GK_GFX1201, Triple::AMDGPUSubArch1201, (12, 0, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP|FEATURE_1536_VGPRS)
+AMDGCN_GPU ("gfx1250", GK_GFX1250, Triple::AMDGPUSubArch1250, (12, 5, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_SRAMECC|FEATURE_1024_ADDRESSABLE_VGPRS)
+AMDGCN_GPU ("gfx1251", GK_GFX1251, Triple::AMDGPUSubArch1251, (12, 5, 1), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_SRAMECC|FEATURE_1024_ADDRESSABLE_VGPRS)
+AMDGCN_GPU ("gfx1310", GK_GFX1310, Triple::AMDGPUSubArch1310, (13, 1, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP|FEATURE_1536_VGPRS)
// Generic targets return the lowest common denominator
// within their family. That is, the ISA that is the most
@@ -142,14 +142,14 @@ AMDGCN_GPU ("gfx1310", GK_GFX1310, Triple::AMDGPUSubArch1310, (13, 1, 0)
// TODO: Split up this API depending on its caller so
// generic target handling is more obvious and less risky.
AMDGCN_GPU ("gfx9-generic", GK_GFX9_GENERIC, Triple::AMDGPUSubArch9, ( 9, 0, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES)
-AMDGCN_GPU ("gfx9-4-generic", GK_GFX9_4_GENERIC, Triple::AMDGPUSubArch9_4, ( 9, 4, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_SRAMECC)
+AMDGCN_GPU ("gfx9-4-generic", GK_GFX9_4_GENERIC, Triple::AMDGPUSubArch9_4, ( 9, 4, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_SRAMECC|FEATURE_GFX90A_INSTS)
AMDGCN_GPU ("gfx10-1-generic", GK_GFX10_1_GENERIC, Triple::AMDGPUSubArch10_1, (10, 1, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_XNACK_ON_OFF_MODES|FEATURE_WGP)
AMDGCN_GPU ("gfx10-3-generic", GK_GFX10_3_GENERIC, Triple::AMDGPUSubArch10_3, (10, 3, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
AMDGCN_GPU ("gfx11-generic", GK_GFX11_GENERIC, Triple::AMDGPUSubArch11, (11, 0, 3), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
AMDGCN_GPU ("gfx11-7-generic", GK_GFX11_7_GENERIC, Triple::AMDGPUSubArch11_7, (11, 7, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx12-generic", GK_GFX12_GENERIC, Triple::AMDGPUSubArch12, (12, 0, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
-AMDGCN_GPU ("gfx12-5-generic", GK_GFX12_5_GENERIC, Triple::AMDGPUSubArch12_5, (12, 5, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK)
-AMDGCN_GPU ("gfx13-generic", GK_GFX13_GENERIC, Triple::AMDGPUSubArch13, (13, 1, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP)
+AMDGCN_GPU ("gfx12-generic", GK_GFX12_GENERIC, Triple::AMDGPUSubArch12, (12, 0, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP|FEATURE_1536_VGPRS)
+AMDGCN_GPU ("gfx12-5-generic", GK_GFX12_5_GENERIC, Triple::AMDGPUSubArch12_5, (12, 5, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_1024_ADDRESSABLE_VGPRS)
+AMDGCN_GPU ("gfx13-generic", GK_GFX13_GENERIC, Triple::AMDGPUSubArch13, (13, 1, 0), FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP|FEATURE_1536_VGPRS)
#undef AMDGCN_GPU
#undef AMDGCN_GPU_ALIAS
diff --git a/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h b/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
index e8f9268f5c1fb..38bede75aeadf 100644
--- a/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
+++ b/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
@@ -86,7 +86,14 @@ enum ArchFeatureKind : uint32_t {
FEATURE_XNACK_ON_OFF_MODES = 1 << 10,
// VI SGPR initialization bug requiring a fixed SGPR allocation size.
- FEATURE_SGPR_INIT_BUG = 1 << 11
+ FEATURE_SGPR_INIT_BUG = 1 << 11,
+
+ // GFX90A-style unified VGPR/AGPR register file instructions.
+ FEATURE_GFX90A_INSTS = 1 << 12,
+
+ // VGPR register-file capacities.
+ FEATURE_1536_VGPRS = 1 << 13,
+ FEATURE_1024_ADDRESSABLE_VGPRS = 1 << 14
};
enum FeatureError : uint32_t {
@@ -161,6 +168,33 @@ LLVM_ABI unsigned getAddressableNumSGPRs(Triple::SubArchType SubArch);
LLVM_ABI unsigned getSGPRAllocGranule(GPUKind AK);
LLVM_ABI unsigned getSGPRAllocGranule(Triple::SubArchType SubArch);
+enum { MAX_DYNAMIC_VGPR_BLOCKS = 8 };
+
+LLVM_ABI unsigned getEUsPerCU(GPUKind AK, bool CuMode);
+LLVM_ABI unsigned getEUsPerCU(Triple::SubArchType SubArch, bool CuMode);
+
+LLVM_ABI unsigned getMaxWavesPerEU(GPUKind AK);
+LLVM_ABI unsigned getMaxWavesPerEU(Triple::SubArchType SubArch);
+
+LLVM_ABI unsigned getTotalNumVGPRs(GPUKind AK, bool Wave32);
+LLVM_ABI unsigned getTotalNumVGPRs(Triple::SubArchType SubArch, bool Wave32);
+
+LLVM_ABI unsigned getVGPRAllocGranule(GPUKind AK, unsigned DynamicVGPRBlockSize,
+ bool Wave32);
+LLVM_ABI unsigned getVGPRAllocGranule(Triple::SubArchType SubArch,
+ unsigned DynamicVGPRBlockSize,
+ bool Wave32);
+
+LLVM_ABI unsigned getAddressableNumArchVGPRs(GPUKind AK, bool Wave32);
+LLVM_ABI unsigned getAddressableNumArchVGPRs(Triple::SubArchType SubArch,
+ bool Wave32);
+
+LLVM_ABI unsigned
+getAddressableNumVGPRs(GPUKind AK, unsigned DynamicVGPRBlockSize, bool Wave32);
+LLVM_ABI unsigned getAddressableNumVGPRs(Triple::SubArchType SubArch,
+ unsigned DynamicVGPRBlockSize,
+ bool Wave32);
+
/// Fills Features map with default values for given target GPU.
/// \p Features contains overriding target features and this function returns
/// default target features with entries overridden by \p Features.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index 01eebf593769e..74c30b572f654 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -419,9 +419,12 @@ const AMDGPUMCExpr *createOccupancy(unsigned InitOcc, const MCExpr *NumSGPRs,
const MCExpr *NumVGPRs,
unsigned DynamicVGPRBlockSize,
const GCNSubtarget &STM, MCContext &Ctx) {
- unsigned MaxWaves = IsaInfo::getMaxWavesPerEU(STM);
- unsigned Granule = IsaInfo::getVGPRAllocGranule(STM, DynamicVGPRBlockSize);
- unsigned TargetTotalNumVGPRs = IsaInfo::getTotalNumVGPRs(STM);
+ unsigned MaxWaves = AMDGPU::getMaxWavesPerEU(STM.getTargetID().getGPUKind());
+ bool Wave32 = STM.getFeatureBits().test(AMDGPU::FeatureWavefrontSize32);
+ unsigned Granule = AMDGPU::getVGPRAllocGranule(STM.getTargetID().getGPUKind(),
+ DynamicVGPRBlockSize, Wave32);
+ unsigned TargetTotalNumVGPRs =
+ AMDGPU::getTotalNumVGPRs(STM.getTargetID().getGPUKind(), Wave32);
// Bake the per-function SGPR budget into the operands so the late-evaluated
// MCExpr stays arithmetic. The trap reservation in particular is implicit on
diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
index c86b16573ca2b..54aea87fb423b 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -173,10 +173,11 @@ void GCNSchedStrategy::initialize(ScheduleDAGMI *DAG) {
LLVM_DEBUG(dbgs() << "Region is known to spill, use alternative "
"VGPRCriticalLimit calculation method.\n");
unsigned DynamicVGPRBlockSize = MFI.getDynamicVGPRBlockSize();
- unsigned Granule =
- AMDGPU::IsaInfo::getVGPRAllocGranule(ST, DynamicVGPRBlockSize);
- unsigned Addressable =
- AMDGPU::IsaInfo::getAddressableNumVGPRs(ST, DynamicVGPRBlockSize);
+ bool Wave32 = ST.getFeatureBits().test(AMDGPU::FeatureWavefrontSize32);
+ unsigned Granule = AMDGPU::getVGPRAllocGranule(
+ ST.getTargetID().getGPUKind(), DynamicVGPRBlockSize, Wave32);
+ unsigned Addressable = AMDGPU::getAddressableNumVGPRs(
+ ST.getTargetID().getGPUKind(), DynamicVGPRBlockSize, Wave32);
unsigned VGPRBudget = alignDown(Addressable / TargetOccupancy, Granule);
VGPRBudget = std::max(VGPRBudget, Granule);
VGPRCriticalLimit = std::min(VGPRBudget, VGPRExcessLimit);
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
index 1c0e718bd8d97..7389aa9bb0f78 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
@@ -245,8 +245,8 @@ GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
LLVM_DEBUG(dbgs() << "sramecc setting for subtarget: "
<< TargetID.getSramEccSetting() << '\n');
- MaxWavesPerEU = AMDGPU::IsaInfo::getMaxWavesPerEU(*this);
- EUsPerCU = AMDGPU::IsaInfo::getEUsPerCU(*this);
+ MaxWavesPerEU = AMDGPU::getMaxWavesPerEU(getTargetID().getGPUKind());
+ EUsPerCU = AMDGPU::getEUsPerCU(getTargetID().getGPUKind(), isCuModeEnabled());
TSInfo = std::make_unique<AMDGPUSelectionDAGInfo>();
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index f21927a636bc0..22b44fcdb5148 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -828,7 +828,9 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
/// \returns VGPR allocation granularity supported by the subtarget.
unsigned getVGPRAllocGranule(unsigned DynamicVGPRBlockSize) const {
- return AMDGPU::IsaInfo::getVGPRAllocGranule(*this, DynamicVGPRBlockSize);
+ return AMDGPU::getVGPRAllocGranule(
+ getTargetID().getGPUKind(), DynamicVGPRBlockSize,
+ getFeatureBits().test(AMDGPU::FeatureWavefrontSize32));
}
/// \returns VGPR encoding granularity supported by the subtarget.
@@ -838,18 +840,24 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
/// \returns Total number of VGPRs supported by the subtarget.
unsigned getTotalNumVGPRs() const {
- return AMDGPU::IsaInfo::getTotalNumVGPRs(*this);
+ return AMDGPU::getTotalNumVGPRs(
+ getTargetID().getGPUKind(),
+ getFeatureBits().test(AMDGPU::FeatureWavefrontSize32));
}
/// \returns Addressable number of architectural VGPRs supported by the
/// subtarget.
unsigned getAddressableNumArchVGPRs() const {
- return AMDGPU::IsaInfo::getAddressableNumArchVGPRs(*this);
+ return AMDGPU::getAddressableNumArchVGPRs(
+ getTargetID().getGPUKind(),
+ getFeatureBits().test(AMDGPU::FeatureWavefrontSize32));
}
/// \returns Addressable number of VGPRs supported by the subtarget.
unsigned getAddressableNumVGPRs(unsigned DynamicVGPRBlockSize) const {
- return AMDGPU::IsaInfo::getAddressableNumVGPRs(*this, DynamicVGPRBlockSize);
+ return AMDGPU::getAddressableNumVGPRs(
+ getTargetID().getGPUKind(), DynamicVGPRBlockSize,
+ getFeatureBits().test(AMDGPU::FeatureWavefrontSize32));
}
/// \returns the minimum number of VGPRs that will prevent achieving more than
diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
index bcd8d0bef062d..320067d938d6d 100644
--- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
@@ -889,8 +889,9 @@ void SIFrameLowering::emitEntryFunctionPrologue(MachineFunction &MF,
assert(FPReg != AMDGPU::FP_REG);
unsigned VGPRSize = llvm::alignTo(
(ST.getAddressableNumVGPRs(MFI->getDynamicVGPRBlockSize()) -
- AMDGPU::IsaInfo::getVGPRAllocGranule(ST,
- MFI->getDynamicVGPRBlockSize())) *
+ AMDGPU::getVGPRAllocGranule(
+ ST.getTargetID().getGPUKind(), MFI->getDynamicVGPRBlockSize(),
+ ST.getFeatureBits().test(AMDGPU::FeatureWavefrontSize32))) *
4,
FrameInfo.getMaxAlign());
MFI->setScratchReservedForDynamicVGPRs(VGPRSize);
diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index ed40bc511b601..221d9906813fd 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -3683,7 +3683,7 @@ bool SIInsertWaitcnts::run() {
ST.getOccupancyWithNumVGPRs(
TRI.getNumUsedPhysRegs(MRI, AMDGPU::VGPR_32RegClass),
/*IsDynamicVGPR=*/false) <
- AMDGPU::IsaInfo::getMaxWavesPerEU(ST))) {
+ AMDGPU::getMaxWavesPerEU(ST.getTargetID().getGPUKind()))) {
for (auto [MI, Flag] : EndPgmInsts) {
if (Flag) {
if (ST.requiresNopBeforeDeallocVGPRs()) {
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 6c847107db593..d0f677b850670 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -1200,32 +1200,14 @@ unsigned getAddressableLocalMemorySize(const MCSubtargetInfo &STI) {
return 32768;
}
-unsigned getEUsPerCU(const MCSubtargetInfo &STI) {
- // "Per CU" really means "per whatever functional block the waves of a
- // workgroup must share".
-
- // GFX12.5 only supports CU mode, which contains four SIMDs.
- if (isGFX1250(STI)) {
- assert(STI.getFeatureBits().test(FeatureCuMode));
- return 4;
- }
-
- // For gfx10 in CU mode the functional block is the CU, which contains
- // two SIMDs.
- if (isGFX10Plus(STI) && STI.getFeatureBits().test(FeatureCuMode))
- return 2;
-
- // Pre-gfx10 a CU contains four SIMDs. For gfx10 in WGP mode the WGP
- // contains two CUs, so a total of four SIMDs.
- return 4;
-}
-
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo &STI,
unsigned FlatWorkGroupSize) {
assert(FlatWorkGroupSize != 0);
if (!STI.getTargetTriple().isAMDGCN())
return 8;
- unsigned MaxWaves = getMaxWavesPerEU(STI) * getEUsPerCU(STI);
+ GPUKind Kind = parseArchAMDGCN(STI.getCPU());
+ bool CuMode = STI.getFeatureBits().test(FeatureCuMode);
+ unsigned MaxWaves = getMaxWavesPerEU(Kind) * getEUsPerCU(Kind, CuMode);
unsigned N = getWavesPerWorkGroup(STI, FlatWorkGroupSize);
if (N == 1) {
// Single-wave workgroups don't consume barrier resources.
@@ -1241,19 +1223,12 @@ unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo &STI,
unsigned getMinWavesPerEU(const MCSubtargetInfo &STI) { return 1; }
-unsigned getMaxWavesPerEU(const MCSubtargetInfo &STI) {
- // FIXME: Need to take scratch memory into account.
- if (isGFX90A(STI))
- return 8;
- if (!isGFX10Plus(STI))
- return 10;
- return hasGFX10_3Insts(STI) ? 16 : 20;
-}
-
unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo &STI,
unsigned FlatWorkGroupSize) {
+ GPUKind Kind = parseArchAMDGCN(STI.getCPU());
+ bool CuMode = STI.getFeatureBits().test(FeatureCuMode);
return divideCeil(getWavesPerWorkGroup(STI, FlatWorkGroupSize),
- getEUsPerCU(STI));
+ getEUsPerCU(Kind, CuMode));
}
unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo &STI) { return 1; }
@@ -1291,10 +1266,10 @@ unsigned getMinNumSGPRs(const MCSubtargetInfo &STI, unsigned WavesPerEU) {
if (Version.Major >= 10)
return 0;
- if (WavesPerEU >= getMaxWavesPerEU(STI))
+ GPUKind Kind = parseArchAMDGCN(STI.getCPU());
+ if (WavesPerEU >= getMaxWavesPerEU(Kind))
return 0;
- GPUKind Kind = parseArchAMDGCN(STI.getCPU());
unsigned MinNumSGPRs =
getSGPRBudgetPerWave(getTotalNumSGPRs(Kind), WavesPerEU + 1,
getSGPRTrapHandlerReserve(STI),
@@ -1368,28 +1343,6 @@ unsigned getNumSGPRBlocks(const MCSubtargetInfo &STI, unsigned NumSGPRs) {
1;
}
-unsigned getVGPRAllocGranule(const MCSubtargetInfo &STI,
- unsigned DynamicVGPRBlockSize,
- std::optional<bool> EnableWavefrontSize32) {
- if (STI.getFeatureBits().test(FeatureGFX90AInsts))
- return 8;
-
- if (DynamicVGPRBlockSize != 0)
- return DynamicVGPRBlockSize;
-
- bool IsWave32 = EnableWavefrontSize32
- ? *EnableWavefrontSize32
- : STI.getFeatureBits().test(FeatureWavefrontSize32);
-
- if (STI.getFeatureBits().test(Feature1536VGPRs))
- return IsWave32 ? 24 : 12;
-
- if (hasGFX10_3Insts(STI))
- return IsWave32 ? 16 : 8;
-
- return IsWave32 ? 8 : 4;
-}
-
unsigned getVGPREncodingGranule(const MCSubtargetInfo &STI,
std::optional<bool> EnableWavefrontSize32) {
if (STI.getFeatureBits().test(FeatureGFX90AInsts))
@@ -1407,44 +1360,14 @@ unsigned getVGPREncodingGranule(const MCSubtargetInfo &STI,
unsigned getArchVGPRAllocGranule() { return 4; }
-unsigned getTotalNumVGPRs(const MCSubtargetInfo &STI) {
- if (STI.getFeatureBits().test(FeatureGFX90AInsts))
- return 512;
- if (!isGFX10Plus(STI))
- return 256;
- bool IsWave32 = STI.getFeatureBits().test(FeatureWavefrontSize32);
- if (STI.getFeatureBits().test(Feature1536VGPRs))
- return IsWave32 ? 1536 : 768;
- return IsWave32 ? 1024 : 512;
-}
-
-unsigned getAddressableNumArchVGPRs(const MCSubtargetInfo &STI) {
- const auto &Features = STI.getFeatureBits();
- if (Features.test(Feature1024AddressableVGPRs))
- return Features.test(FeatureWavefrontSize32) ? 1024 : 512;
- return 256;
-}
-
-unsigned getAddressableNumVGPRs(const MCSubtargetInfo &STI,
- unsigned DynamicVGPRBlockSize) {
- const auto &Features = STI.getFeatureBits();
- if (Features.test(FeatureGFX90AInsts))
- return 512;
-
- if (DynamicVGPRBlockSize != 0) {
- // On GFX12 we can allocate at most MaxDynamicVGPRBlocks blocks of VGPRs.
- return MaxDynamicVGPRBlocks *
- getVGPRAllocGranule(STI, DynamicVGPRBlockSize);
- }
- return getAddressableNumArchVGPRs(STI);
-}
-
unsigned getNumWavesPerEUWithNumVGPRs(const MCSubtargetInfo &STI,
unsigned NumVGPRs,
unsigned DynamicVGPRBlockSize) {
+ GPUKind Kind = parseArchAMDGCN(STI.getCPU());
+ bool Wave32 = STI.getFeatureBits().test(FeatureWavefrontSize32);
return getNumWavesPerEUWithNumVGPRs(
- NumVGPRs, getVGPRAllocGranule(STI, DynamicVGPRBlockSize),
- getMaxWavesPerEU(STI), getTotalNumVGPRs(STI));
+ NumVGPRs, getVGPRAllocGranule(Kind, DynamicVGPRBlockSize, Wave32),
+ getMaxWavesPerEU(Kind), getTotalNumVGPRs(Kind, Wave32));
}
unsigned getNumWavesPerEUWithNumVGPRs(unsigned NumVGPRs, unsigned Granule,
@@ -1467,12 +1390,12 @@ unsigned getOccupancyWithNumSGPRs(unsigned SGPRs, unsigned MaxWaves,
}
unsigned getOccupancyWithNumSGPRs(const MCSubtargetInfo &STI, unsigned SGPRs) {
- unsigned MaxWaves = getMaxWavesPerEU(STI);
+ GPUKind Kind = parseArchAMDGCN(STI.getCPU());
+ unsigned MaxWaves = getMaxWavesPerEU(Kind);
if (!isSGPROccupancyLimited(STI))
return MaxWaves;
- GPUKind Kind = parseArchAMDGCN(STI.getCPU());
return getOccupancyWithNumSGPRs(SGPRs, MaxWaves, getTotalNumSGPRs(Kind),
getSGPRAllocGranule(Kind),
getSGPRTrapHandlerReserve(STI));
@@ -1490,14 +1413,16 @@ unsigned getMinNumVGPRs(const MCSubtargetInfo &STI, unsigned WavesPerEU,
if (DynamicVGPREnabled)
return 0;
- unsigned MaxWavesPerEU = getMaxWavesPerEU(STI);
+ GPUKind Kind = parseArchAMDGCN(STI.getCPU());
+ bool Wave32 = STI.getFeatureBits().test(FeatureWavefrontSize32);
+ unsigned MaxWavesPerEU = getMaxWavesPerEU(Kind);
if (WavesPerEU >= MaxWavesPerEU)
return 0;
- unsigned TotNumVGPRs = getTotalNumVGPRs(STI);
+ unsigned TotNumVGPRs = getTotalNumVGPRs(Kind, Wave32);
unsigned AddrsableNumVGPRs =
- getAddressableNumVGPRs(STI, DynamicVGPRBlockSize);
- unsigned Granule = getVGPRAllocGranule(STI, DynamicVGPRBlockSize);
+ getAddressableNumVGPRs(Kind, DynamicVGPRBlockSize, Wave32);
+ unsigned Granule = getVGPRAllocGranule(Kind, DynamicVGPRBlockSize, Wave32);
unsigned MaxNumVGPRs = alignDown(TotNumVGPRs / WavesPerEU, Granule);
if (MaxNumVGPRs == alignDown(TotNumVGPRs / MaxWavesPerEU, Granule))
@@ -1519,13 +1444,15 @@ unsigned getMaxNumVGPRs(const MCSubtargetInfo &STI, unsigned WavesPerEU,
// In dynamic VGPR mode, WavesPerEU does not imply a VGPR limit.
bool DynamicVGPREnabled = (DynamicVGPRBlockSize != 0);
+ GPUKind Kind = parseArchAMDGCN(STI.getCPU());
+ bool Wave32 = STI.getFeatureBits().test(FeatureWavefrontSize32);
unsigned MaxNumVGPRs =
DynamicVGPREnabled
- ? getTotalNumVGPRs(STI)
- : alignDown(getTotalNumVGPRs(STI) / WavesPerEU,
- getVGPRAllocGranule(STI, DynamicVGPRBlockSize));
+ ? getTotalNumVGPRs(Kind, Wave32)
+ : alignDown(getTotalNumVGPRs(Kind, Wave32) / WavesPerEU,
+ getVGPRAllocGranule(Kind, DynamicVGPRBlockSize, Wave32));
unsigned AddressableNumVGPRs =
- getAddressableNumVGPRs(STI, DynamicVGPRBlockSize);
+ getAddressableNumVGPRs(Kind, DynamicVGPRBlockSize, Wave32);
return std::min(MaxNumVGPRs, AddressableNumVGPRs);
}
@@ -1540,9 +1467,12 @@ unsigned getAllocatedNumVGPRBlocks(const MCSubtargetInfo &STI,
unsigned NumVGPRs,
unsigned DynamicVGPRBlockSize,
std::optional<bool> EnableWavefrontSize32) {
+ GPUKind Kind = parseArchAMDGCN(STI.getCPU());
+ bool Wave32 = EnableWavefrontSize32
+ ? *EnableWavefrontSize32
+ : STI.getFeatureBits().test(FeatureWavefrontSize32);
return getGranulatedNumRegisterBlocks(
- NumVGPRs,
- getVGPRAllocGranule(STI, DynamicVGPRBlockSize, EnableWavefrontSize32));
+ NumVGPRs, getVGPRAllocGranule(Kind, DynamicVGPRBlockSize, Wave32));
}
} // end namespace IsaInfo
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index 9dcd1ed9d1441..bc3023d7f59ee 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -183,10 +183,6 @@ unsigned getLocalMemorySize(const MCSubtargetInfo &STI);
/// \p STI.
unsigned getAddressableLocalMemorySize(const MCSubtargetInfo &STI);
-/// \returns Number of execution units per compute unit for given subtarget \p
-/// STI.
-unsigned getEUsPerCU(const MCSubtargetInfo &STI);
-
/// \returns Maximum number of work groups per compute unit for given subtarget
/// \p STI and limited by given \p FlatWorkGroupSize.
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo &STI,
@@ -196,10 +192,6 @@ unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo &STI,
/// STI.
unsigned getMinWavesPerEU(const MCSubtargetInfo &STI);
-/// \returns Maximum number of waves per execution unit for given subtarget \p
-/// STI without any kind of limitation.
-unsigned getMaxWavesPerEU(const MCSubtargetInfo &STI);
-
/// \returns Number of waves per execution unit required to support the given \p
/// FlatWorkGroupSize.
unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo &STI,
@@ -247,14 +239,6 @@ unsigned getNumExtraSGPRs(const MCSubtargetInfo &STI, bool VCCUsed,
/// register counts.
unsigned getNumSGPRBlocks(const MCSubtargetInfo &STI, unsigned NumSGPRs);
-/// \returns VGPR allocation granularity for given subtarget \p STI.
-///
-/// For subtargets which support it, \p EnableWavefrontSize32 should match
-/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
-unsigned
-getVGPRAllocGranule(const MCSubtargetInfo &STI, unsigned DynamicVGPRBlockSize,
- std::optional<bool> EnableWavefrontSize32 = std::nullopt);
-
/// \returns VGPR encoding granularity for given subtarget \p STI.
///
/// For subtargets which support it, \p EnableWavefrontSize32 should match
@@ -267,19 +251,9 @@ unsigned getVGPREncodingGranule(
/// returns the allocation granule for ArchVGPRs.
unsigned getArchVGPRAllocGranule();
-/// \returns Total number of VGPRs for given subtarget \p STI.
-unsigned getTotalNumVGPRs(const MCSubtargetInfo &STI);
-
/// Maximum number of VGPR blocks that can be allocated in dynamic VGPR mode.
-static constexpr unsigned MaxDynamicVGPRBlocks = 8;
-
-/// \returns Addressable number of architectural VGPRs for a given subtarget \p
-/// STI.
-unsigned getAddressableNumArchVGPRs(const MCSubtargetInfo &STI);
-
-/// \returns Addressable number of VGPRs for given subtarget \p STI.
-unsigned getAddressableNumVGPRs(const MCSubtargetInfo &STI,
- unsigned DynamicVGPRBlockSize);
+static constexpr unsigned MaxDynamicVGPRBlocks =
+ AMDGPU::MAX_DYNAMIC_VGPR_BLOCKS;
/// \returns Minimum number of VGPRs that meets given number of waves per
/// execution unit requirement for given subtarget \p STI.
diff --git a/llvm/lib/TargetParser/AMDGPUTargetParser.cpp b/llvm/lib/TargetParser/AMDGPUTargetParser.cpp
index 2558830b4f9ae..45e455791cbf9 100644
--- a/llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+++ b/llvm/lib/TargetParser/AMDGPUTargetParser.cpp
@@ -414,6 +414,175 @@ unsigned AMDGPU::getSGPRAllocGranule(Triple::SubArchType SubArch) {
return 8;
}
+unsigned AMDGPU::getEUsPerCU(GPUKind AK, bool CuMode) {
+ // "Per CU" really means "per whatever functional block the waves of a
+ // workgroup must share".
+ IsaVersion Version = getIsaVersion(getSubArch(AK));
+
+ // GFX12.5 only supports CU mode, which contains four SIMDs.
+ if (Version.Major == 12 && Version.Minor == 5) {
+ assert(CuMode);
+ return 4;
+ }
+
+ // For gfx10+ in CU mode the functional block is the CU, which contains
+ // two SIMDs.
+ if (Version.Major >= 10 && CuMode)
+ return 2;
+
+ // Pre-gfx10 a CU contains four SIMDs. For gfx10 in WGP mode the WGP
+ // contains two CUs, so a total of four SIMDs.
+ return 4;
+}
+
+unsigned AMDGPU::getEUsPerCU(Triple::SubArchType SubArch, bool CuMode) {
+ // "Per CU" really means "per whatever functional block the waves of a
+ // workgroup must share".
+ IsaVersion Version = getIsaVersion(SubArch);
+
+ // GFX12.5 only supports CU mode, which contains four SIMDs.
+ if (Version.Major == 12 && Version.Minor == 5) {
+ assert(CuMode);
+ return 4;
+ }
+
+ // For gfx10+ in CU mode the functional block is the CU, which contains
+ // two SIMDs.
+ if (Version.Major >= 10 && CuMode)
+ return 2;
+
+ // Pre-gfx10 a CU contains four SIMDs. For gfx10 in WGP mode the WGP
+ // contains two CUs, so a total of four SIMDs.
+ return 4;
+}
+
+// GFX10.3-style instructions are present on gfx10.3 and every later
+// generation (gfx11+). This matches the transitive expansion of the
+// FeatureGFX10_3Insts subtarget feature, which gfx11+ imply.
+static bool hasGFX10_3Insts(IsaVersion Version) {
+ return Version.Major >= 11 || (Version.Major == 10 && Version.Minor == 3);
+}
+
+unsigned AMDGPU::getMaxWavesPerEU(GPUKind AK) {
+ // FIXME: Need to take scratch memory into account.
+ if (getArchAttrAMDGCN(AK) & FEATURE_GFX90A_INSTS)
+ return 8;
+ IsaVersion Version = getIsaVersion(getSubArch(AK));
+ if (Version.Major < 10)
+ return 10;
+ return hasGFX10_3Insts(Version) ? 16 : 20;
+}
+
+unsigned AMDGPU::getMaxWavesPerEU(Triple::SubArchType SubArch) {
+ // FIXME: Need to take scratch memory into account.
+ if (getArchAttrAMDGCN(SubArch) & FEATURE_GFX90A_INSTS)
+ return 8;
+ IsaVersion Version = getIsaVersion(SubArch);
+ if (Version.Major < 10)
+ return 10;
+ return hasGFX10_3Insts(Version) ? 16 : 20;
+}
+
+unsigned AMDGPU::getTotalNumVGPRs(GPUKind AK, bool Wave32) {
+ unsigned Features = getArchAttrAMDGCN(AK);
+ if (Features & FEATURE_GFX90A_INSTS)
+ return 512;
+ IsaVersion Version = getIsaVersion(getSubArch(AK));
+ if (Version.Major < 10)
+ return 256;
+ if (Features & FEATURE_1536_VGPRS)
+ return Wave32 ? 1536 : 768;
+ return Wave32 ? 1024 : 512;
+}
+
+unsigned AMDGPU::getTotalNumVGPRs(Triple::SubArchType SubArch, bool Wave32) {
+ unsigned Features = getArchAttrAMDGCN(SubArch);
+ if (Features & FEATURE_GFX90A_INSTS)
+ return 512;
+ IsaVersion Version = getIsaVersion(SubArch);
+ if (Version.Major < 10)
+ return 256;
+ if (Features & FEATURE_1536_VGPRS)
+ return Wave32 ? 1536 : 768;
+ return Wave32 ? 1024 : 512;
+}
+
+unsigned AMDGPU::getVGPRAllocGranule(GPUKind AK, unsigned DynamicVGPRBlockSize,
+ bool Wave32) {
+ unsigned Features = getArchAttrAMDGCN(AK);
+ if (Features & FEATURE_GFX90A_INSTS)
+ return 8;
+
+ if (DynamicVGPRBlockSize != 0)
+ return DynamicVGPRBlockSize;
+
+ if (Features & FEATURE_1536_VGPRS)
+ return Wave32 ? 24 : 12;
+
+ if (hasGFX10_3Insts(getIsaVersion(getSubArch(AK))))
+ return Wave32 ? 16 : 8;
+
+ return Wave32 ? 8 : 4;
+}
+
+unsigned AMDGPU::getVGPRAllocGranule(Triple::SubArchType SubArch,
+ unsigned DynamicVGPRBlockSize,
+ bool Wave32) {
+ unsigned Features = getArchAttrAMDGCN(SubArch);
+ if (Features & FEATURE_GFX90A_INSTS)
+ return 8;
+
+ if (DynamicVGPRBlockSize != 0)
+ return DynamicVGPRBlockSize;
+
+ if (Features & FEATURE_1536_VGPRS)
+ return Wave32 ? 24 : 12;
+
+ if (hasGFX10_3Insts(getIsaVersion(SubArch)))
+ return Wave32 ? 16 : 8;
+
+ return Wave32 ? 8 : 4;
+}
+
+unsigned AMDGPU::getAddressableNumArchVGPRs(GPUKind AK, bool Wave32) {
+ if (getArchAttrAMDGCN(AK) & FEATURE_1024_ADDRESSABLE_VGPRS)
+ return Wave32 ? 1024 : 512;
+ return 256;
+}
+
+unsigned AMDGPU::getAddressableNumArchVGPRs(Triple::SubArchType SubArch,
+ bool Wave32) {
+ if (getArchAttrAMDGCN(SubArch) & FEATURE_1024_ADDRESSABLE_VGPRS)
+ return Wave32 ? 1024 : 512;
+ return 256;
+}
+
+unsigned AMDGPU::getAddressableNumVGPRs(GPUKind AK,
+ unsigned DynamicVGPRBlockSize,
+ bool Wave32) {
+ if (getArchAttrAMDGCN(AK) & FEATURE_GFX90A_INSTS)
+ return 512;
+ if (DynamicVGPRBlockSize != 0) {
+ // On GFX12 we can allocate at most MAX_DYNAMIC_VGPR_BLOCKS blocks of VGPRs.
+ return MAX_DYNAMIC_VGPR_BLOCKS *
+ getVGPRAllocGranule(AK, DynamicVGPRBlockSize, Wave32);
+ }
+ return getAddressableNumArchVGPRs(AK, Wave32);
+}
+
+unsigned AMDGPU::getAddressableNumVGPRs(Triple::SubArchType SubArch,
+ unsigned DynamicVGPRBlockSize,
+ bool Wave32) {
+ if (getArchAttrAMDGCN(SubArch) & FEATURE_GFX90A_INSTS)
+ return 512;
+ if (DynamicVGPRBlockSize != 0) {
+ // On GFX12 we can allocate at most MAX_DYNAMIC_VGPR_BLOCKS blocks of VGPRs.
+ return MAX_DYNAMIC_VGPR_BLOCKS *
+ getVGPRAllocGranule(SubArch, DynamicVGPRBlockSize, Wave32);
+ }
+ return getAddressableNumArchVGPRs(SubArch, Wave32);
+}
+
StringRef AMDGPU::getCanonicalArchName(const Triple &T, StringRef Arch) {
assert(T.isAMDGPU());
auto ProcKind = T.isAMDGCN() ? parseArchAMDGCN(Arch) : parseArchR600(Arch);
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 5a97d6052e765..d59b8b8b813c3 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -2983,6 +2983,114 @@ TEST(TargetParserTest, testAMDGPUParseTargetIDString) {
TargetID::parse(Triple("r600-unknown-unknown"), "cypress").has_value());
}
+TEST(TargetParserTest, testAMDGPUgetEUsPerCU) {
+ // GFX12.5 is CU-mode only and always has four SIMDs. GFX10+ has two SIMDs in
+ // CU mode and four in WGP mode; pre-GFX10 always has four. Second arg is the
+ // CU-mode flag.
+ EXPECT_EQ(AMDGPU::getEUsPerCU(Triple::AMDGPUSubArch1250, true), 4u);
+ EXPECT_EQ(AMDGPU::getEUsPerCU(Triple::AMDGPUSubArch1030, true), 2u);
+ EXPECT_EQ(AMDGPU::getEUsPerCU(Triple::AMDGPUSubArch1030, false), 4u);
+ EXPECT_EQ(AMDGPU::getEUsPerCU(Triple::AMDGPUSubArch600, true), 4u);
+ EXPECT_EQ(AMDGPU::getEUsPerCU(Triple::AMDGPUSubArch900, false), 4u);
+
+ // The GPUKind overloads resolve to the same values.
+ EXPECT_EQ(AMDGPU::getEUsPerCU(AMDGPU::GK_GFX1250, true), 4u);
+ EXPECT_EQ(AMDGPU::getEUsPerCU(AMDGPU::GK_GFX1030, true), 2u);
+ EXPECT_EQ(AMDGPU::getEUsPerCU(AMDGPU::GK_GFX600, false), 4u);
+}
+
+TEST(TargetParserTest, testAMDGPUgetMaxWavesPerEU) {
+ // GFX90A -> 8, pre-GFX10 -> 10, gfx10.1 -> 20; GFX10.3-style instructions
+ // (gfx10.3 and every later generation, gfx11+) -> 16.
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(Triple::AMDGPUSubArch90A), 8u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(Triple::AMDGPUSubArch600), 10u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(Triple::AMDGPUSubArch900), 10u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(Triple::AMDGPUSubArch1010), 20u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(Triple::AMDGPUSubArch1030), 16u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(Triple::AMDGPUSubArch1100), 16u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(Triple::AMDGPUSubArch1250), 16u);
+
+ // The GPUKind overloads resolve to the same values.
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(AMDGPU::GK_GFX90A), 8u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(AMDGPU::GK_GFX900), 10u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(AMDGPU::GK_GFX1010), 20u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(AMDGPU::GK_GFX1030), 16u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(AMDGPU::GK_GFX1100), 16u);
+}
+
+TEST(TargetParserTest, testAMDGPUgetTotalNumVGPRs) {
+ // GFX90A -> 512 and pre-GFX10 -> 256, both independent of wavefront size; the
+ // 1536-VGPR file (GFX11.0.0) -> 1536/768; default GFX10+ -> 1024/512. Second
+ // arg is the wave32 flag.
+ EXPECT_EQ(AMDGPU::getTotalNumVGPRs(Triple::AMDGPUSubArch90A, true), 512u);
+ EXPECT_EQ(AMDGPU::getTotalNumVGPRs(Triple::AMDGPUSubArch90A, false), 512u);
+ EXPECT_EQ(AMDGPU::getTotalNumVGPRs(Triple::AMDGPUSubArch600, true), 256u);
+ EXPECT_EQ(AMDGPU::getTotalNumVGPRs(Triple::AMDGPUSubArch1100, true), 1536u);
+ EXPECT_EQ(AMDGPU::getTotalNumVGPRs(Triple::AMDGPUSubArch1100, false), 768u);
+ EXPECT_EQ(AMDGPU::getTotalNumVGPRs(Triple::AMDGPUSubArch1030, true), 1024u);
+ EXPECT_EQ(AMDGPU::getTotalNumVGPRs(Triple::AMDGPUSubArch1030, false), 512u);
+
+ // The GPUKind overloads resolve to the same values.
+ EXPECT_EQ(AMDGPU::getTotalNumVGPRs(AMDGPU::GK_GFX90A, true), 512u);
+ EXPECT_EQ(AMDGPU::getTotalNumVGPRs(AMDGPU::GK_GFX600, true), 256u);
+ EXPECT_EQ(AMDGPU::getTotalNumVGPRs(AMDGPU::GK_GFX1100, true), 1536u);
+ EXPECT_EQ(AMDGPU::getTotalNumVGPRs(AMDGPU::GK_GFX1030, true), 1024u);
+}
+
+TEST(TargetParserTest, testAMDGPUgetVGPRAllocGranule) {
+ // GFX90A -> 8 regardless of other inputs; a nonzero dynamic block size is
+ // returned verbatim; 1536-VGPR file -> 24/12; GFX10.3 -> 16/8; GFX10 -> 8/4.
+ // Args are (kind, dynamic block size, wave32).
+ EXPECT_EQ(AMDGPU::getVGPRAllocGranule(Triple::AMDGPUSubArch90A, 0, true), 8u);
+ EXPECT_EQ(AMDGPU::getVGPRAllocGranule(Triple::AMDGPUSubArch1010, 16, true),
+ 16u);
+ EXPECT_EQ(AMDGPU::getVGPRAllocGranule(Triple::AMDGPUSubArch1100, 0, true),
+ 24u);
+ EXPECT_EQ(AMDGPU::getVGPRAllocGranule(Triple::AMDGPUSubArch1100, 0, false),
+ 12u);
+ EXPECT_EQ(AMDGPU::getVGPRAllocGranule(Triple::AMDGPUSubArch1030, 0, true),
+ 16u);
+ EXPECT_EQ(AMDGPU::getVGPRAllocGranule(Triple::AMDGPUSubArch1010, 0, true),
+ 8u);
+ EXPECT_EQ(AMDGPU::getVGPRAllocGranule(Triple::AMDGPUSubArch1010, 0, false),
+ 4u);
+
+ // The GPUKind overloads resolve to the same values.
+ EXPECT_EQ(AMDGPU::getVGPRAllocGranule(AMDGPU::GK_GFX90A, 0, true), 8u);
+ EXPECT_EQ(AMDGPU::getVGPRAllocGranule(AMDGPU::GK_GFX1100, 0, true), 24u);
+ EXPECT_EQ(AMDGPU::getVGPRAllocGranule(AMDGPU::GK_GFX1030, 0, true), 16u);
+ EXPECT_EQ(AMDGPU::getVGPRAllocGranule(AMDGPU::GK_GFX1010, 0, true), 8u);
+}
+
+TEST(TargetParserTest, testAMDGPUgetAddressableNumVGPRs) {
+ // getAddressableNumArchVGPRs: the 1024-addressable file (GFX12.5) ->
+ // 1024/512, everything else -> 256. Second arg is the wave32 flag.
+ EXPECT_EQ(AMDGPU::getAddressableNumArchVGPRs(Triple::AMDGPUSubArch1250, true),
+ 1024u);
+ EXPECT_EQ(
+ AMDGPU::getAddressableNumArchVGPRs(Triple::AMDGPUSubArch1250, false),
+ 512u);
+ EXPECT_EQ(AMDGPU::getAddressableNumArchVGPRs(Triple::AMDGPUSubArch1030, true),
+ 256u);
+
+ // getAddressableNumVGPRs: GFX90A -> 512; static mode defers to the arch VGPR
+ // count; dynamic mode -> MAX_DYNAMIC_VGPR_BLOCKS * granule. Args are (kind,
+ // dynamic block size, wave32).
+ EXPECT_EQ(AMDGPU::getAddressableNumVGPRs(Triple::AMDGPUSubArch90A, 0, true),
+ 512u);
+ EXPECT_EQ(AMDGPU::getAddressableNumVGPRs(Triple::AMDGPUSubArch1250, 0, true),
+ 1024u);
+ EXPECT_EQ(AMDGPU::getAddressableNumVGPRs(Triple::AMDGPUSubArch1030, 0, true),
+ 256u);
+ EXPECT_EQ(AMDGPU::getAddressableNumVGPRs(Triple::AMDGPUSubArch1200, 16, true),
+ AMDGPU::MAX_DYNAMIC_VGPR_BLOCKS * 16u);
+
+ // The GPUKind overloads resolve to the same values.
+ EXPECT_EQ(AMDGPU::getAddressableNumVGPRs(AMDGPU::GK_GFX90A, 0, true), 512u);
+ EXPECT_EQ(AMDGPU::getAddressableNumVGPRs(AMDGPU::GK_GFX1250, 0, true), 1024u);
+ EXPECT_EQ(AMDGPU::getAddressableNumVGPRs(AMDGPU::GK_GFX1030, 0, true), 256u);
+}
+
TEST(TargetParserTest, testAMDGPUTargetIDProvidesFor) {
using AMDGPU::TargetID;
Triple AMDHSA("amdgcn-amd-amdhsa");
>From 2d52f7357389324396f12b2e09564a42ea4ec034 Mon Sep 17 00:00:00 2001
From: Soumil Kushwaha <Soumil.Kushwaha at amd.com>
Date: Tue, 21 Jul 2026 14:07:27 -0500
Subject: [PATCH 2/2] reordered tests
---
.../TargetParser/TargetParserTest.cpp | 216 +++++++++---------
1 file changed, 108 insertions(+), 108 deletions(-)
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index d59b8b8b813c3..2df18ec43742b 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -2872,6 +2872,114 @@ TEST(TargetParserTest, testAMDGPUgetSGPRAllocGranule) {
EXPECT_EQ(AMDGPU::getSGPRAllocGranule(AMDGPU::GK_GFX1030), 106u);
}
+TEST(TargetParserTest, testAMDGPUgetEUsPerCU) {
+ // GFX12.5 is CU-mode only and always has four SIMDs. GFX10+ has two SIMDs in
+ // CU mode and four in WGP mode; pre-GFX10 always has four. Second arg is the
+ // CU-mode flag.
+ EXPECT_EQ(AMDGPU::getEUsPerCU(Triple::AMDGPUSubArch1250, true), 4u);
+ EXPECT_EQ(AMDGPU::getEUsPerCU(Triple::AMDGPUSubArch1030, true), 2u);
+ EXPECT_EQ(AMDGPU::getEUsPerCU(Triple::AMDGPUSubArch1030, false), 4u);
+ EXPECT_EQ(AMDGPU::getEUsPerCU(Triple::AMDGPUSubArch600, true), 4u);
+ EXPECT_EQ(AMDGPU::getEUsPerCU(Triple::AMDGPUSubArch900, false), 4u);
+
+ // The GPUKind overloads resolve to the same values.
+ EXPECT_EQ(AMDGPU::getEUsPerCU(AMDGPU::GK_GFX1250, true), 4u);
+ EXPECT_EQ(AMDGPU::getEUsPerCU(AMDGPU::GK_GFX1030, true), 2u);
+ EXPECT_EQ(AMDGPU::getEUsPerCU(AMDGPU::GK_GFX600, false), 4u);
+}
+
+TEST(TargetParserTest, testAMDGPUgetMaxWavesPerEU) {
+ // GFX90A -> 8, pre-GFX10 -> 10, gfx10.1 -> 20; GFX10.3-style instructions
+ // (gfx10.3 and every later generation, gfx11+) -> 16.
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(Triple::AMDGPUSubArch90A), 8u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(Triple::AMDGPUSubArch600), 10u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(Triple::AMDGPUSubArch900), 10u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(Triple::AMDGPUSubArch1010), 20u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(Triple::AMDGPUSubArch1030), 16u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(Triple::AMDGPUSubArch1100), 16u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(Triple::AMDGPUSubArch1250), 16u);
+
+ // The GPUKind overloads resolve to the same values.
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(AMDGPU::GK_GFX90A), 8u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(AMDGPU::GK_GFX900), 10u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(AMDGPU::GK_GFX1010), 20u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(AMDGPU::GK_GFX1030), 16u);
+ EXPECT_EQ(AMDGPU::getMaxWavesPerEU(AMDGPU::GK_GFX1100), 16u);
+}
+
+TEST(TargetParserTest, testAMDGPUgetTotalNumVGPRs) {
+ // GFX90A -> 512 and pre-GFX10 -> 256, both independent of wavefront size; the
+ // 1536-VGPR file (GFX11.0.0) -> 1536/768; default GFX10+ -> 1024/512. Second
+ // arg is the wave32 flag.
+ EXPECT_EQ(AMDGPU::getTotalNumVGPRs(Triple::AMDGPUSubArch90A, true), 512u);
+ EXPECT_EQ(AMDGPU::getTotalNumVGPRs(Triple::AMDGPUSubArch90A, false), 512u);
+ EXPECT_EQ(AMDGPU::getTotalNumVGPRs(Triple::AMDGPUSubArch600, true), 256u);
+ EXPECT_EQ(AMDGPU::getTotalNumVGPRs(Triple::AMDGPUSubArch1100, true), 1536u);
+ EXPECT_EQ(AMDGPU::getTotalNumVGPRs(Triple::AMDGPUSubArch1100, false), 768u);
+ EXPECT_EQ(AMDGPU::getTotalNumVGPRs(Triple::AMDGPUSubArch1030, true), 1024u);
+ EXPECT_EQ(AMDGPU::getTotalNumVGPRs(Triple::AMDGPUSubArch1030, false), 512u);
+
+ // The GPUKind overloads resolve to the same values.
+ EXPECT_EQ(AMDGPU::getTotalNumVGPRs(AMDGPU::GK_GFX90A, true), 512u);
+ EXPECT_EQ(AMDGPU::getTotalNumVGPRs(AMDGPU::GK_GFX600, true), 256u);
+ EXPECT_EQ(AMDGPU::getTotalNumVGPRs(AMDGPU::GK_GFX1100, true), 1536u);
+ EXPECT_EQ(AMDGPU::getTotalNumVGPRs(AMDGPU::GK_GFX1030, true), 1024u);
+}
+
+TEST(TargetParserTest, testAMDGPUgetVGPRAllocGranule) {
+ // GFX90A -> 8 regardless of other inputs; a nonzero dynamic block size is
+ // returned verbatim; 1536-VGPR file -> 24/12; GFX10.3 -> 16/8; GFX10 -> 8/4.
+ // Args are (kind, dynamic block size, wave32).
+ EXPECT_EQ(AMDGPU::getVGPRAllocGranule(Triple::AMDGPUSubArch90A, 0, true), 8u);
+ EXPECT_EQ(AMDGPU::getVGPRAllocGranule(Triple::AMDGPUSubArch1010, 16, true),
+ 16u);
+ EXPECT_EQ(AMDGPU::getVGPRAllocGranule(Triple::AMDGPUSubArch1100, 0, true),
+ 24u);
+ EXPECT_EQ(AMDGPU::getVGPRAllocGranule(Triple::AMDGPUSubArch1100, 0, false),
+ 12u);
+ EXPECT_EQ(AMDGPU::getVGPRAllocGranule(Triple::AMDGPUSubArch1030, 0, true),
+ 16u);
+ EXPECT_EQ(AMDGPU::getVGPRAllocGranule(Triple::AMDGPUSubArch1010, 0, true),
+ 8u);
+ EXPECT_EQ(AMDGPU::getVGPRAllocGranule(Triple::AMDGPUSubArch1010, 0, false),
+ 4u);
+
+ // The GPUKind overloads resolve to the same values.
+ EXPECT_EQ(AMDGPU::getVGPRAllocGranule(AMDGPU::GK_GFX90A, 0, true), 8u);
+ EXPECT_EQ(AMDGPU::getVGPRAllocGranule(AMDGPU::GK_GFX1100, 0, true), 24u);
+ EXPECT_EQ(AMDGPU::getVGPRAllocGranule(AMDGPU::GK_GFX1030, 0, true), 16u);
+ EXPECT_EQ(AMDGPU::getVGPRAllocGranule(AMDGPU::GK_GFX1010, 0, true), 8u);
+}
+
+TEST(TargetParserTest, testAMDGPUgetAddressableNumVGPRs) {
+ // getAddressableNumArchVGPRs: the 1024-addressable file (GFX12.5) ->
+ // 1024/512, everything else -> 256. Second arg is the wave32 flag.
+ EXPECT_EQ(AMDGPU::getAddressableNumArchVGPRs(Triple::AMDGPUSubArch1250, true),
+ 1024u);
+ EXPECT_EQ(
+ AMDGPU::getAddressableNumArchVGPRs(Triple::AMDGPUSubArch1250, false),
+ 512u);
+ EXPECT_EQ(AMDGPU::getAddressableNumArchVGPRs(Triple::AMDGPUSubArch1030, true),
+ 256u);
+
+ // getAddressableNumVGPRs: GFX90A -> 512; static mode defers to the arch VGPR
+ // count; dynamic mode -> MAX_DYNAMIC_VGPR_BLOCKS * granule. Args are (kind,
+ // dynamic block size, wave32).
+ EXPECT_EQ(AMDGPU::getAddressableNumVGPRs(Triple::AMDGPUSubArch90A, 0, true),
+ 512u);
+ EXPECT_EQ(AMDGPU::getAddressableNumVGPRs(Triple::AMDGPUSubArch1250, 0, true),
+ 1024u);
+ EXPECT_EQ(AMDGPU::getAddressableNumVGPRs(Triple::AMDGPUSubArch1030, 0, true),
+ 256u);
+ EXPECT_EQ(AMDGPU::getAddressableNumVGPRs(Triple::AMDGPUSubArch1200, 16, true),
+ AMDGPU::MAX_DYNAMIC_VGPR_BLOCKS * 16u);
+
+ // The GPUKind overloads resolve to the same values.
+ EXPECT_EQ(AMDGPU::getAddressableNumVGPRs(AMDGPU::GK_GFX90A, 0, true), 512u);
+ EXPECT_EQ(AMDGPU::getAddressableNumVGPRs(AMDGPU::GK_GFX1250, 0, true), 1024u);
+ EXPECT_EQ(AMDGPU::getAddressableNumVGPRs(AMDGPU::GK_GFX1030, 0, true), 256u);
+}
+
TEST(TargetParserTest, testAMDGPUParseTargetIDString) {
using AMDGPU::TargetID;
using AMDGPU::TargetIDSetting;
@@ -2983,114 +3091,6 @@ TEST(TargetParserTest, testAMDGPUParseTargetIDString) {
TargetID::parse(Triple("r600-unknown-unknown"), "cypress").has_value());
}
-TEST(TargetParserTest, testAMDGPUgetEUsPerCU) {
- // GFX12.5 is CU-mode only and always has four SIMDs. GFX10+ has two SIMDs in
- // CU mode and four in WGP mode; pre-GFX10 always has four. Second arg is the
- // CU-mode flag.
- EXPECT_EQ(AMDGPU::getEUsPerCU(Triple::AMDGPUSubArch1250, true), 4u);
- EXPECT_EQ(AMDGPU::getEUsPerCU(Triple::AMDGPUSubArch1030, true), 2u);
- EXPECT_EQ(AMDGPU::getEUsPerCU(Triple::AMDGPUSubArch1030, false), 4u);
- EXPECT_EQ(AMDGPU::getEUsPerCU(Triple::AMDGPUSubArch600, true), 4u);
- EXPECT_EQ(AMDGPU::getEUsPerCU(Triple::AMDGPUSubArch900, false), 4u);
-
- // The GPUKind overloads resolve to the same values.
- EXPECT_EQ(AMDGPU::getEUsPerCU(AMDGPU::GK_GFX1250, true), 4u);
- EXPECT_EQ(AMDGPU::getEUsPerCU(AMDGPU::GK_GFX1030, true), 2u);
- EXPECT_EQ(AMDGPU::getEUsPerCU(AMDGPU::GK_GFX600, false), 4u);
-}
-
-TEST(TargetParserTest, testAMDGPUgetMaxWavesPerEU) {
- // GFX90A -> 8, pre-GFX10 -> 10, gfx10.1 -> 20; GFX10.3-style instructions
- // (gfx10.3 and every later generation, gfx11+) -> 16.
- EXPECT_EQ(AMDGPU::getMaxWavesPerEU(Triple::AMDGPUSubArch90A), 8u);
- EXPECT_EQ(AMDGPU::getMaxWavesPerEU(Triple::AMDGPUSubArch600), 10u);
- EXPECT_EQ(AMDGPU::getMaxWavesPerEU(Triple::AMDGPUSubArch900), 10u);
- EXPECT_EQ(AMDGPU::getMaxWavesPerEU(Triple::AMDGPUSubArch1010), 20u);
- EXPECT_EQ(AMDGPU::getMaxWavesPerEU(Triple::AMDGPUSubArch1030), 16u);
- EXPECT_EQ(AMDGPU::getMaxWavesPerEU(Triple::AMDGPUSubArch1100), 16u);
- EXPECT_EQ(AMDGPU::getMaxWavesPerEU(Triple::AMDGPUSubArch1250), 16u);
-
- // The GPUKind overloads resolve to the same values.
- EXPECT_EQ(AMDGPU::getMaxWavesPerEU(AMDGPU::GK_GFX90A), 8u);
- EXPECT_EQ(AMDGPU::getMaxWavesPerEU(AMDGPU::GK_GFX900), 10u);
- EXPECT_EQ(AMDGPU::getMaxWavesPerEU(AMDGPU::GK_GFX1010), 20u);
- EXPECT_EQ(AMDGPU::getMaxWavesPerEU(AMDGPU::GK_GFX1030), 16u);
- EXPECT_EQ(AMDGPU::getMaxWavesPerEU(AMDGPU::GK_GFX1100), 16u);
-}
-
-TEST(TargetParserTest, testAMDGPUgetTotalNumVGPRs) {
- // GFX90A -> 512 and pre-GFX10 -> 256, both independent of wavefront size; the
- // 1536-VGPR file (GFX11.0.0) -> 1536/768; default GFX10+ -> 1024/512. Second
- // arg is the wave32 flag.
- EXPECT_EQ(AMDGPU::getTotalNumVGPRs(Triple::AMDGPUSubArch90A, true), 512u);
- EXPECT_EQ(AMDGPU::getTotalNumVGPRs(Triple::AMDGPUSubArch90A, false), 512u);
- EXPECT_EQ(AMDGPU::getTotalNumVGPRs(Triple::AMDGPUSubArch600, true), 256u);
- EXPECT_EQ(AMDGPU::getTotalNumVGPRs(Triple::AMDGPUSubArch1100, true), 1536u);
- EXPECT_EQ(AMDGPU::getTotalNumVGPRs(Triple::AMDGPUSubArch1100, false), 768u);
- EXPECT_EQ(AMDGPU::getTotalNumVGPRs(Triple::AMDGPUSubArch1030, true), 1024u);
- EXPECT_EQ(AMDGPU::getTotalNumVGPRs(Triple::AMDGPUSubArch1030, false), 512u);
-
- // The GPUKind overloads resolve to the same values.
- EXPECT_EQ(AMDGPU::getTotalNumVGPRs(AMDGPU::GK_GFX90A, true), 512u);
- EXPECT_EQ(AMDGPU::getTotalNumVGPRs(AMDGPU::GK_GFX600, true), 256u);
- EXPECT_EQ(AMDGPU::getTotalNumVGPRs(AMDGPU::GK_GFX1100, true), 1536u);
- EXPECT_EQ(AMDGPU::getTotalNumVGPRs(AMDGPU::GK_GFX1030, true), 1024u);
-}
-
-TEST(TargetParserTest, testAMDGPUgetVGPRAllocGranule) {
- // GFX90A -> 8 regardless of other inputs; a nonzero dynamic block size is
- // returned verbatim; 1536-VGPR file -> 24/12; GFX10.3 -> 16/8; GFX10 -> 8/4.
- // Args are (kind, dynamic block size, wave32).
- EXPECT_EQ(AMDGPU::getVGPRAllocGranule(Triple::AMDGPUSubArch90A, 0, true), 8u);
- EXPECT_EQ(AMDGPU::getVGPRAllocGranule(Triple::AMDGPUSubArch1010, 16, true),
- 16u);
- EXPECT_EQ(AMDGPU::getVGPRAllocGranule(Triple::AMDGPUSubArch1100, 0, true),
- 24u);
- EXPECT_EQ(AMDGPU::getVGPRAllocGranule(Triple::AMDGPUSubArch1100, 0, false),
- 12u);
- EXPECT_EQ(AMDGPU::getVGPRAllocGranule(Triple::AMDGPUSubArch1030, 0, true),
- 16u);
- EXPECT_EQ(AMDGPU::getVGPRAllocGranule(Triple::AMDGPUSubArch1010, 0, true),
- 8u);
- EXPECT_EQ(AMDGPU::getVGPRAllocGranule(Triple::AMDGPUSubArch1010, 0, false),
- 4u);
-
- // The GPUKind overloads resolve to the same values.
- EXPECT_EQ(AMDGPU::getVGPRAllocGranule(AMDGPU::GK_GFX90A, 0, true), 8u);
- EXPECT_EQ(AMDGPU::getVGPRAllocGranule(AMDGPU::GK_GFX1100, 0, true), 24u);
- EXPECT_EQ(AMDGPU::getVGPRAllocGranule(AMDGPU::GK_GFX1030, 0, true), 16u);
- EXPECT_EQ(AMDGPU::getVGPRAllocGranule(AMDGPU::GK_GFX1010, 0, true), 8u);
-}
-
-TEST(TargetParserTest, testAMDGPUgetAddressableNumVGPRs) {
- // getAddressableNumArchVGPRs: the 1024-addressable file (GFX12.5) ->
- // 1024/512, everything else -> 256. Second arg is the wave32 flag.
- EXPECT_EQ(AMDGPU::getAddressableNumArchVGPRs(Triple::AMDGPUSubArch1250, true),
- 1024u);
- EXPECT_EQ(
- AMDGPU::getAddressableNumArchVGPRs(Triple::AMDGPUSubArch1250, false),
- 512u);
- EXPECT_EQ(AMDGPU::getAddressableNumArchVGPRs(Triple::AMDGPUSubArch1030, true),
- 256u);
-
- // getAddressableNumVGPRs: GFX90A -> 512; static mode defers to the arch VGPR
- // count; dynamic mode -> MAX_DYNAMIC_VGPR_BLOCKS * granule. Args are (kind,
- // dynamic block size, wave32).
- EXPECT_EQ(AMDGPU::getAddressableNumVGPRs(Triple::AMDGPUSubArch90A, 0, true),
- 512u);
- EXPECT_EQ(AMDGPU::getAddressableNumVGPRs(Triple::AMDGPUSubArch1250, 0, true),
- 1024u);
- EXPECT_EQ(AMDGPU::getAddressableNumVGPRs(Triple::AMDGPUSubArch1030, 0, true),
- 256u);
- EXPECT_EQ(AMDGPU::getAddressableNumVGPRs(Triple::AMDGPUSubArch1200, 16, true),
- AMDGPU::MAX_DYNAMIC_VGPR_BLOCKS * 16u);
-
- // The GPUKind overloads resolve to the same values.
- EXPECT_EQ(AMDGPU::getAddressableNumVGPRs(AMDGPU::GK_GFX90A, 0, true), 512u);
- EXPECT_EQ(AMDGPU::getAddressableNumVGPRs(AMDGPU::GK_GFX1250, 0, true), 1024u);
- EXPECT_EQ(AMDGPU::getAddressableNumVGPRs(AMDGPU::GK_GFX1030, 0, true), 256u);
-}
-
TEST(TargetParserTest, testAMDGPUTargetIDProvidesFor) {
using AMDGPU::TargetID;
Triple AMDHSA("amdgcn-amd-amdhsa");
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