[llvm] [AArch64] Add SVE lowering for FP_TO_[US]INT_SAT. (PR #207201)
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 22 04:01:57 PDT 2026
https://github.com/sdesmalen-arm updated https://github.com/llvm/llvm-project/pull/207201
>From d5d39dc7331fbdd196afdb5ed2c56b0b28cd8962 Mon Sep 17 00:00:00 2001
From: Sander de Smalen <sander.desmalen at arm.com>
Date: Mon, 20 Jul 2026 15:15:25 +0000
Subject: [PATCH 1/3] Pre-commit fixed-length test.
---
.../AArch64/sve-fixed-length-fp-to-int-sat.ll | 491 ++++++++++++++++++
1 file changed, 491 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int-sat.ll
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int-sat.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int-sat.ll
new file mode 100644
index 0000000000000..cccc98358e416
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int-sat.ll
@@ -0,0 +1,491 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mattr=+sve -aarch64-sve-vector-bits-min=256 | FileCheck %s
+
+target triple = "aarch64"
+
+; Float
+
+define void @test_signed_v8f32_v8i32(ptr %p) {
+; CHECK-LABEL: test_signed_v8f32_v8i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-NEXT: sub x9, sp, #48
+; CHECK-NEXT: mov x29, sp
+; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0
+; CHECK-NEXT: .cfi_def_cfa w29, 16
+; CHECK-NEXT: .cfi_offset w30, -8
+; CHECK-NEXT: .cfi_offset w29, -16
+; CHECK-NEXT: ptrue p0.s, vl8
+; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
+; CHECK-NEXT: mov z1.s, z0.s[7]
+; CHECK-NEXT: mov z2.s, z0.s[6]
+; CHECK-NEXT: mov z3.s, z0.s[5]
+; CHECK-NEXT: fcvtzs w8, s1
+; CHECK-NEXT: mov z1.s, z0.s[4]
+; CHECK-NEXT: fcvtzs w9, s2
+; CHECK-NEXT: fcvtzs w10, s3
+; CHECK-NEXT: mov z2.s, z0.s[3]
+; CHECK-NEXT: mov z3.s, z0.s[2]
+; CHECK-NEXT: fcvtzs w11, s1
+; CHECK-NEXT: mov z1.s, z0.s[1]
+; CHECK-NEXT: fcvtzs w12, s2
+; CHECK-NEXT: stp w9, w8, [sp, #24]
+; CHECK-NEXT: fcvtzs w8, s3
+; CHECK-NEXT: fcvtzs w9, s0
+; CHECK-NEXT: stp w11, w10, [sp, #16]
+; CHECK-NEXT: fcvtzs w10, s1
+; CHECK-NEXT: stp w8, w12, [sp, #8]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: stp w9, w10, [sp]
+; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8]
+; CHECK-NEXT: st1w { z0.s }, p0, [x0]
+; CHECK-NEXT: mov sp, x29
+; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
+; CHECK-NEXT: ret
+ %ld = load <8 x float>, ptr %p
+ %cvt = call <8 x i32> @llvm.fptosi.sat(<8 x float> %ld)
+ store <8 x i32> %cvt, ptr %p
+ ret void
+}
+
+define void @test_signed_v8f32_v8i16(ptr %p) {
+; CHECK-LABEL: test_signed_v8f32_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-NEXT: sub x9, sp, #48
+; CHECK-NEXT: mov x29, sp
+; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0
+; CHECK-NEXT: .cfi_def_cfa w29, 16
+; CHECK-NEXT: .cfi_offset w30, -8
+; CHECK-NEXT: .cfi_offset w29, -16
+; CHECK-NEXT: ptrue p0.s, vl8
+; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
+; CHECK-NEXT: mov z1.s, z0.s[7]
+; CHECK-NEXT: mov z2.s, z0.s[6]
+; CHECK-NEXT: mov z3.s, z0.s[5]
+; CHECK-NEXT: fcvtzs w8, s1
+; CHECK-NEXT: mov z1.s, z0.s[4]
+; CHECK-NEXT: fcvtzs w9, s2
+; CHECK-NEXT: fcvtzs w10, s3
+; CHECK-NEXT: mov z2.s, z0.s[3]
+; CHECK-NEXT: mov z3.s, z0.s[2]
+; CHECK-NEXT: fcvtzs w11, s1
+; CHECK-NEXT: mov z1.s, z0.s[1]
+; CHECK-NEXT: fcvtzs w12, s2
+; CHECK-NEXT: stp w9, w8, [sp, #24]
+; CHECK-NEXT: fcvtzs w8, s3
+; CHECK-NEXT: fcvtzs w9, s0
+; CHECK-NEXT: mov z0.s, #32767 // =0x7fff
+; CHECK-NEXT: stp w11, w10, [sp, #16]
+; CHECK-NEXT: fcvtzs w10, s1
+; CHECK-NEXT: stp w8, w12, [sp, #8]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: stp w9, w10, [sp]
+; CHECK-NEXT: ld1w { z1.s }, p0/z, [x8]
+; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT: mov z1.s, #-32768 // =0xffffffffffff8000
+; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
+; CHECK-NEXT: str q0, [x0]
+; CHECK-NEXT: mov sp, x29
+; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
+; CHECK-NEXT: ret
+ %ld = load <8 x float>, ptr %p
+ %cvt = call <8 x i16> @llvm.fptosi.sat(<8 x float> %ld)
+ store <8 x i16> %cvt, ptr %p
+ ret void
+}
+
+define void @test_signed_v4f32_v4i64(ptr %p) {
+; CHECK-LABEL: test_signed_v4f32_v4i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-NEXT: sub x9, sp, #48
+; CHECK-NEXT: mov x29, sp
+; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0
+; CHECK-NEXT: .cfi_def_cfa w29, 16
+; CHECK-NEXT: .cfi_offset w30, -8
+; CHECK-NEXT: .cfi_offset w29, -16
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: ptrue p0.d, vl4
+; CHECK-NEXT: mov s1, v0.s[3]
+; CHECK-NEXT: mov s2, v0.s[2]
+; CHECK-NEXT: mov s3, v0.s[1]
+; CHECK-NEXT: fcvtzs x11, s0
+; CHECK-NEXT: fcvtzs x8, s1
+; CHECK-NEXT: fcvtzs x9, s2
+; CHECK-NEXT: fcvtzs x10, s3
+; CHECK-NEXT: stp x9, x8, [sp, #16]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: stp x11, x10, [sp]
+; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8]
+; CHECK-NEXT: st1d { z0.d }, p0, [x0]
+; CHECK-NEXT: mov sp, x29
+; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
+; CHECK-NEXT: ret
+ %ld = load <4 x float>, ptr %p
+ %cvt = call <4 x i64> @llvm.fptosi.sat(<4 x float> %ld)
+ store <4 x i64> %cvt, ptr %p
+ ret void
+}
+
+; Double
+
+define void @test_signed_v4f64_v4i32(ptr %p) {
+; CHECK-LABEL: test_signed_v4f64_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d, vl4
+; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
+; CHECK-NEXT: mov z1.d, z0.d[1]
+; CHECK-NEXT: fcvtzs w8, d0
+; CHECK-NEXT: fcvtzs w9, d1
+; CHECK-NEXT: mov z1.d, z0.d[2]
+; CHECK-NEXT: mov z0.d, z0.d[3]
+; CHECK-NEXT: fmov s2, w8
+; CHECK-NEXT: fcvtzs w8, d1
+; CHECK-NEXT: mov v2.s[1], w9
+; CHECK-NEXT: mov v2.s[2], w8
+; CHECK-NEXT: fcvtzs w8, d0
+; CHECK-NEXT: mov v2.s[3], w8
+; CHECK-NEXT: str q2, [x0]
+; CHECK-NEXT: ret
+ %ld = load <4 x double>, ptr %p
+ %cvt = call <4 x i32> @llvm.fptosi.sat(<4 x double> %ld)
+ store <4 x i32> %cvt, ptr %p
+ ret void
+}
+
+define void @test_signed_v8f64_v8i32(ptr %p) {
+; CHECK-LABEL: test_signed_v8f64_v8i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-NEXT: sub x9, sp, #48
+; CHECK-NEXT: mov x29, sp
+; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0
+; CHECK-NEXT: .cfi_def_cfa w29, 16
+; CHECK-NEXT: .cfi_offset w30, -8
+; CHECK-NEXT: .cfi_offset w29, -16
+; CHECK-NEXT: ptrue p0.d, vl4
+; CHECK-NEXT: mov x8, #4 // =0x4
+; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
+; CHECK-NEXT: ld1d { z2.d }, p0/z, [x0]
+; CHECK-NEXT: ptrue p0.s, vl8
+; CHECK-NEXT: mov z1.d, z0.d[3]
+; CHECK-NEXT: mov z3.d, z0.d[2]
+; CHECK-NEXT: fcvtzs w10, d0
+; CHECK-NEXT: fcvtzs w8, d1
+; CHECK-NEXT: mov z1.d, z0.d[1]
+; CHECK-NEXT: fcvtzs w9, d3
+; CHECK-NEXT: mov z3.d, z2.d[3]
+; CHECK-NEXT: mov z0.d, z2.d[2]
+; CHECK-NEXT: fcvtzs w11, d1
+; CHECK-NEXT: mov z1.d, z2.d[1]
+; CHECK-NEXT: fcvtzs w12, d3
+; CHECK-NEXT: stp w9, w8, [sp, #24]
+; CHECK-NEXT: fcvtzs w8, d0
+; CHECK-NEXT: fcvtzs w9, d2
+; CHECK-NEXT: stp w10, w11, [sp, #16]
+; CHECK-NEXT: fcvtzs w10, d1
+; CHECK-NEXT: stp w8, w12, [sp, #8]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: stp w9, w10, [sp]
+; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8]
+; CHECK-NEXT: st1w { z0.s }, p0, [x0]
+; CHECK-NEXT: mov sp, x29
+; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
+; CHECK-NEXT: ret
+ %ld = load <8 x double>, ptr %p
+ %cvt = call <8 x i32> @llvm.fptosi.sat(<8 x double> %ld)
+ store <8 x i32> %cvt, ptr %p
+ ret void
+}
+
+define void @test_signed_v8f64_v8i16(ptr %p) {
+; CHECK-LABEL: test_signed_v8f64_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d, vl4
+; CHECK-NEXT: mov x8, #4 // =0x4
+; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
+; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0]
+; CHECK-NEXT: mov w8, #32767 // =0x7fff
+; CHECK-NEXT: fcvtzs w9, d0
+; CHECK-NEXT: mov z2.d, z1.d[1]
+; CHECK-NEXT: fcvtzs w12, d1
+; CHECK-NEXT: fcvtzs w10, d2
+; CHECK-NEXT: mov z2.d, z1.d[2]
+; CHECK-NEXT: mov z1.d, z1.d[3]
+; CHECK-NEXT: cmp w9, w8
+; CHECK-NEXT: csel w11, w9, w8, lt
+; CHECK-NEXT: mov w9, #-32768 // =0xffff8000
+; CHECK-NEXT: cmn w11, #8, lsl #12 // =32768
+; CHECK-NEXT: fcvtzs w13, d2
+; CHECK-NEXT: csel w11, w11, w9, gt
+; CHECK-NEXT: cmp w10, w8
+; CHECK-NEXT: csel w10, w10, w8, lt
+; CHECK-NEXT: cmn w10, #8, lsl #12 // =32768
+; CHECK-NEXT: csel w10, w10, w9, gt
+; CHECK-NEXT: cmp w12, w8
+; CHECK-NEXT: csel w12, w12, w8, lt
+; CHECK-NEXT: cmn w12, #8, lsl #12 // =32768
+; CHECK-NEXT: csel w12, w12, w9, gt
+; CHECK-NEXT: cmp w13, w8
+; CHECK-NEXT: fmov s2, w12
+; CHECK-NEXT: csel w12, w13, w8, lt
+; CHECK-NEXT: cmn w12, #8, lsl #12 // =32768
+; CHECK-NEXT: csel w12, w12, w9, gt
+; CHECK-NEXT: mov v2.h[1], w10
+; CHECK-NEXT: fcvtzs w10, d1
+; CHECK-NEXT: mov z1.d, z0.d[1]
+; CHECK-NEXT: mov v2.h[2], w12
+; CHECK-NEXT: cmp w10, w8
+; CHECK-NEXT: csel w10, w10, w8, lt
+; CHECK-NEXT: cmn w10, #8, lsl #12 // =32768
+; CHECK-NEXT: csel w10, w10, w9, gt
+; CHECK-NEXT: mov v2.h[3], w10
+; CHECK-NEXT: fcvtzs w10, d1
+; CHECK-NEXT: mov z1.d, z0.d[2]
+; CHECK-NEXT: mov z0.d, z0.d[3]
+; CHECK-NEXT: mov v2.h[4], w11
+; CHECK-NEXT: cmp w10, w8
+; CHECK-NEXT: fcvtzs w11, d1
+; CHECK-NEXT: csel w10, w10, w8, lt
+; CHECK-NEXT: cmn w10, #8, lsl #12 // =32768
+; CHECK-NEXT: csel w10, w10, w9, gt
+; CHECK-NEXT: mov v2.h[5], w10
+; CHECK-NEXT: cmp w11, w8
+; CHECK-NEXT: fcvtzs w10, d0
+; CHECK-NEXT: csel w11, w11, w8, lt
+; CHECK-NEXT: cmn w11, #8, lsl #12 // =32768
+; CHECK-NEXT: csel w11, w11, w9, gt
+; CHECK-NEXT: mov v2.h[6], w11
+; CHECK-NEXT: cmp w10, w8
+; CHECK-NEXT: csel w8, w10, w8, lt
+; CHECK-NEXT: cmn w8, #8, lsl #12 // =32768
+; CHECK-NEXT: csel w8, w8, w9, gt
+; CHECK-NEXT: mov v2.h[7], w8
+; CHECK-NEXT: str q2, [x0]
+; CHECK-NEXT: ret
+ %ld = load <8 x double>, ptr %p
+ %cvt = call <8 x i16> @llvm.fptosi.sat(<8 x double> %ld)
+ store <8 x i16> %cvt, ptr %p
+ ret void
+}
+
+define void @test_signed_v4f64_v4i64(ptr %p) {
+; CHECK-LABEL: test_signed_v4f64_v4i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-NEXT: sub x9, sp, #48
+; CHECK-NEXT: mov x29, sp
+; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0
+; CHECK-NEXT: .cfi_def_cfa w29, 16
+; CHECK-NEXT: .cfi_offset w30, -8
+; CHECK-NEXT: .cfi_offset w29, -16
+; CHECK-NEXT: ptrue p0.d, vl4
+; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
+; CHECK-NEXT: mov z1.d, z0.d[3]
+; CHECK-NEXT: mov z2.d, z0.d[2]
+; CHECK-NEXT: fcvtzs x10, d0
+; CHECK-NEXT: fcvtzs x8, d1
+; CHECK-NEXT: mov z1.d, z0.d[1]
+; CHECK-NEXT: fcvtzs x9, d2
+; CHECK-NEXT: fcvtzs x11, d1
+; CHECK-NEXT: stp x9, x8, [sp, #16]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: stp x10, x11, [sp]
+; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8]
+; CHECK-NEXT: st1d { z0.d }, p0, [x0]
+; CHECK-NEXT: mov sp, x29
+; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
+; CHECK-NEXT: ret
+ %ld = load <4 x double>, ptr %p
+ %cvt = call <4 x i64> @llvm.fptosi.sat(<4 x double> %ld)
+ store <4 x i64> %cvt, ptr %p
+ ret void
+}
+
+
+; half
+
+define void @test_signed_v16f16_v16i16(ptr %p) {
+; CHECK-LABEL: test_signed_v16f16_v16i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-NEXT: sub x9, sp, #48
+; CHECK-NEXT: mov x29, sp
+; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0
+; CHECK-NEXT: .cfi_def_cfa w29, 16
+; CHECK-NEXT: .cfi_offset w30, -8
+; CHECK-NEXT: .cfi_offset w29, -16
+; CHECK-NEXT: ptrue p0.h, vl16
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
+; CHECK-NEXT: mov z1.h, z0.h[15]
+; CHECK-NEXT: mov z2.h, z0.h[14]
+; CHECK-NEXT: fcvtzs h3, h0
+; CHECK-NEXT: mov z4.h, z0.h[13]
+; CHECK-NEXT: mov z5.h, z0.h[12]
+; CHECK-NEXT: mov z6.h, z0.h[11]
+; CHECK-NEXT: mov z7.h, z0.h[10]
+; CHECK-NEXT: fcvtzs h1, h1
+; CHECK-NEXT: fcvtzs h2, h2
+; CHECK-NEXT: str h3, [sp]
+; CHECK-NEXT: mov z3.h, z0.h[9]
+; CHECK-NEXT: fcvtzs h4, h4
+; CHECK-NEXT: fcvtzs h5, h5
+; CHECK-NEXT: fcvtzs h6, h6
+; CHECK-NEXT: fcvtzs h7, h7
+; CHECK-NEXT: str h1, [sp, #30]
+; CHECK-NEXT: mov z1.h, z0.h[8]
+; CHECK-NEXT: fcvtzs h3, h3
+; CHECK-NEXT: str h2, [sp, #28]
+; CHECK-NEXT: mov z2.h, z0.h[7]
+; CHECK-NEXT: str h4, [sp, #26]
+; CHECK-NEXT: mov z4.h, z0.h[6]
+; CHECK-NEXT: fcvtzs h1, h1
+; CHECK-NEXT: str h5, [sp, #24]
+; CHECK-NEXT: mov z5.h, z0.h[5]
+; CHECK-NEXT: fcvtzs h2, h2
+; CHECK-NEXT: str h6, [sp, #22]
+; CHECK-NEXT: mov z6.h, z0.h[4]
+; CHECK-NEXT: str h7, [sp, #20]
+; CHECK-NEXT: mov z7.h, z0.h[3]
+; CHECK-NEXT: fcvtzs h4, h4
+; CHECK-NEXT: str h3, [sp, #18]
+; CHECK-NEXT: mov z3.h, z0.h[2]
+; CHECK-NEXT: mov z0.h, z0.h[1]
+; CHECK-NEXT: fcvtzs h5, h5
+; CHECK-NEXT: str h1, [sp, #16]
+; CHECK-NEXT: fcvtzs h1, h6
+; CHECK-NEXT: str h2, [sp, #14]
+; CHECK-NEXT: fcvtzs h2, h7
+; CHECK-NEXT: fcvtzs h3, h3
+; CHECK-NEXT: fcvtzs h0, h0
+; CHECK-NEXT: str h4, [sp, #12]
+; CHECK-NEXT: str h5, [sp, #10]
+; CHECK-NEXT: str h1, [sp, #8]
+; CHECK-NEXT: str h2, [sp, #6]
+; CHECK-NEXT: str h3, [sp, #4]
+; CHECK-NEXT: str h0, [sp, #2]
+; CHECK-NEXT: ld1h { z0.h }, p0/z, [x8]
+; CHECK-NEXT: st1h { z0.h }, p0, [x0]
+; CHECK-NEXT: mov sp, x29
+; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
+; CHECK-NEXT: ret
+ %ld = load <16 x half>, ptr %p
+ %cvt = call <16 x i16> @llvm.fptosi.sat(<16 x half> %ld)
+ store <16 x i16> %cvt, ptr %p
+ ret void
+}
+
+define void @test_signed_v8f16_v8i32(ptr %p) {
+; CHECK-LABEL: test_signed_v8f16_v8i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-NEXT: sub x9, sp, #48
+; CHECK-NEXT: mov x29, sp
+; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0
+; CHECK-NEXT: .cfi_def_cfa w29, 16
+; CHECK-NEXT: .cfi_offset w30, -8
+; CHECK-NEXT: .cfi_offset w29, -16
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: ptrue p0.s, vl8
+; CHECK-NEXT: mov h1, v0.h[7]
+; CHECK-NEXT: mov h2, v0.h[6]
+; CHECK-NEXT: mov h3, v0.h[5]
+; CHECK-NEXT: mov h4, v0.h[4]
+; CHECK-NEXT: fcvtzs w8, h1
+; CHECK-NEXT: mov h1, v0.h[3]
+; CHECK-NEXT: fcvtzs w9, h2
+; CHECK-NEXT: mov h2, v0.h[2]
+; CHECK-NEXT: fcvtzs w10, h3
+; CHECK-NEXT: mov h3, v0.h[1]
+; CHECK-NEXT: fcvtzs w11, h4
+; CHECK-NEXT: fcvtzs w12, h1
+; CHECK-NEXT: stp w9, w8, [sp, #24]
+; CHECK-NEXT: fcvtzs w8, h2
+; CHECK-NEXT: fcvtzs w9, h3
+; CHECK-NEXT: stp w11, w10, [sp, #16]
+; CHECK-NEXT: fcvtzs w10, h0
+; CHECK-NEXT: stp w8, w12, [sp, #8]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: stp w10, w9, [sp]
+; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8]
+; CHECK-NEXT: st1w { z0.s }, p0, [x0]
+; CHECK-NEXT: mov sp, x29
+; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
+; CHECK-NEXT: ret
+ %ld = load <8 x half>, ptr %p
+ %cvt = call <8 x i32> @llvm.fptosi.sat(<8 x half> %ld)
+ store <8 x i32> %cvt, ptr %p
+ ret void
+}
+
+define void @test_signed_v16f16_v16i32(ptr %p) {
+; CHECK-LABEL: test_signed_v16f16_v16i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-NEXT: sub x9, sp, #80
+; CHECK-NEXT: mov x29, sp
+; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0
+; CHECK-NEXT: .cfi_def_cfa w29, 16
+; CHECK-NEXT: .cfi_offset w30, -8
+; CHECK-NEXT: .cfi_offset w29, -16
+; CHECK-NEXT: ptrue p0.h, vl16
+; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
+; CHECK-NEXT: ptrue p0.s, vl8
+; CHECK-NEXT: mov h1, v0.h[7]
+; CHECK-NEXT: mov h2, v0.h[6]
+; CHECK-NEXT: mov h3, v0.h[5]
+; CHECK-NEXT: mov h4, v0.h[4]
+; CHECK-NEXT: mov h5, v0.h[3]
+; CHECK-NEXT: fcvtzs w8, h1
+; CHECK-NEXT: mov h1, v0.h[2]
+; CHECK-NEXT: fcvtzs w9, h2
+; CHECK-NEXT: fcvtzs w10, h3
+; CHECK-NEXT: mov h3, v0.h[1]
+; CHECK-NEXT: fcvtzs w11, h4
+; CHECK-NEXT: movprfx z2, z0
+; CHECK-NEXT: ext z2.b, z2.b, z0.b, #16
+; CHECK-NEXT: fcvtzs w12, h5
+; CHECK-NEXT: stp w9, w8, [sp, #56]
+; CHECK-NEXT: fcvtzs w8, h1
+; CHECK-NEXT: mov h4, v2.h[7]
+; CHECK-NEXT: mov h1, v2.h[6]
+; CHECK-NEXT: fcvtzs w9, h3
+; CHECK-NEXT: mov h3, v2.h[5]
+; CHECK-NEXT: stp w11, w10, [sp, #48]
+; CHECK-NEXT: fcvtzs w10, h0
+; CHECK-NEXT: mov h0, v2.h[4]
+; CHECK-NEXT: stp w8, w12, [sp, #40]
+; CHECK-NEXT: fcvtzs w11, h4
+; CHECK-NEXT: mov h4, v2.h[3]
+; CHECK-NEXT: fcvtzs w12, h1
+; CHECK-NEXT: mov h1, v2.h[2]
+; CHECK-NEXT: fcvtzs w8, h3
+; CHECK-NEXT: mov h3, v2.h[1]
+; CHECK-NEXT: stp w10, w9, [sp, #32]
+; CHECK-NEXT: fcvtzs w9, h0
+; CHECK-NEXT: fcvtzs w10, h4
+; CHECK-NEXT: stp w12, w11, [sp, #24]
+; CHECK-NEXT: fcvtzs w11, h1
+; CHECK-NEXT: fcvtzs w12, h3
+; CHECK-NEXT: stp w9, w8, [sp, #16]
+; CHECK-NEXT: fcvtzs w8, h2
+; CHECK-NEXT: stp w11, w10, [sp, #8]
+; CHECK-NEXT: stp w8, w12, [sp]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8]
+; CHECK-NEXT: add x8, sp, #32
+; CHECK-NEXT: ld1w { z1.s }, p0/z, [x8]
+; CHECK-NEXT: mov x8, #8 // =0x8
+; CHECK-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2]
+; CHECK-NEXT: st1w { z1.s }, p0, [x0]
+; CHECK-NEXT: mov sp, x29
+; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
+; CHECK-NEXT: ret
+ %ld = load <16 x half>, ptr %p
+ %cvt = call <16 x i32> @llvm.fptosi.sat(<16 x half> %ld)
+ store <16 x i32> %cvt, ptr %p
+ ret void
+}
>From 2825aca353e80a40676ba4e49424efda48435c5b Mon Sep 17 00:00:00 2001
From: Sander de Smalen <sander.desmalen at arm.com>
Date: Tue, 23 Jun 2026 14:38:52 +0000
Subject: [PATCH 2/3] [AArch64] Add SVE lowering for FP_TO_[US]INT_SAT.
---
.../Target/AArch64/AArch64ISelLowering.cpp | 39 +-
.../AArch64/sve-fixed-length-fp-to-int-sat.ll | 398 +---
.../AArch64/sve-fixed-vector-llrint.ll | 842 +++------
.../CodeGen/AArch64/sve-fixed-vector-lrint.ll | 1608 +++++------------
llvm/test/CodeGen/AArch64/sve-fptosi-sat.ll | 446 ++---
llvm/test/CodeGen/AArch64/sve-fptoui-sat.ll | 356 +---
llvm/test/CodeGen/AArch64/sve-llrint.ll | 1599 ++++------------
llvm/test/CodeGen/AArch64/sve-lrint.ll | 1599 ++++------------
8 files changed, 1666 insertions(+), 5221 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 9872ec9a4a1fe..6b12415db14dd 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1675,6 +1675,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SINT_TO_FP, VT, Custom);
setOperationAction(ISD::FP_TO_UINT, VT, Custom);
setOperationAction(ISD::FP_TO_SINT, VT, Custom);
+ setOperationAction(ISD::FP_TO_UINT_SAT, VT, Custom);
+ setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom);
setOperationAction(ISD::MLOAD, VT, Custom);
setOperationAction(ISD::MSTORE, VT, Legal);
setOperationAction(ISD::MUL, VT, Custom);
@@ -2608,6 +2610,8 @@ void AArch64TargetLowering::addTypeForFixedLengthSVE(MVT VT) {
setOperationAction(ISD::FP_ROUND, VT, Default);
setOperationAction(ISD::FP_TO_SINT, VT, Default);
setOperationAction(ISD::FP_TO_UINT, VT, Default);
+ setOperationAction(ISD::FP_TO_UINT_SAT, VT, Custom);
+ setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom);
setOperationAction(ISD::FRINT, VT, Default);
setOperationAction(ISD::LRINT, VT, Default);
setOperationAction(ISD::LLRINT, VT, Default);
@@ -5192,20 +5196,18 @@ AArch64TargetLowering::LowerVectorFP_TO_INT_SAT(SDValue Op,
assert(SatWidth <= DstElementWidth &&
"Saturation width cannot exceed result width");
- // TODO: Consider lowering to SVE operations, as in LowerVectorFP_TO_INT.
- // Currently, the `llvm.fpto[su]i.sat.*` intrinsics don't accept scalable
- // types, so this is hard to reach.
- if (DstVT.isScalableVector())
- return SDValue();
-
const EVT SrcElementVT = SrcVT.getVectorElementType();
if (SrcElementVT != MVT::f64 && SrcElementVT != MVT::f32 &&
SrcElementVT != MVT::f16 && SrcElementVT != MVT::bf16)
return SDValue();
+ if (SDValue Res = tryLowerFPToIntToSVE(Op, DAG))
+ return Res;
+
// Returns true if the operation can be matched by an isel pattern directly.
auto CanHandleNatively = [&DstVT, &SatWidth](EVT SrcVT) -> bool {
- return SrcVT.getScalarSizeInBits() == DstVT.getScalarSizeInBits() &&
+ return SrcVT != MVT::nxv2f32 &&
+ SrcVT.getScalarSizeInBits() == DstVT.getScalarSizeInBits() &&
SrcVT.getScalarSizeInBits() == SatWidth;
};
@@ -5215,7 +5217,7 @@ AArch64TargetLowering::LowerVectorFP_TO_INT_SAT(SDValue Op,
(SrcVT.getScalarSizeInBits() < SatWidth ||
// NEON has no vector MIN/MAX for i64, so it's simpler to scalarize
// (at least until sqxtn is selected).
- SrcVT.getVectorElementType() == MVT::f64);
+ (SrcVT == MVT::v1f64 || SrcVT == MVT::v2f64));
};
// Try to promote the operation to a wider type if SrcVT < DstVT,
@@ -34731,8 +34733,10 @@ AArch64TargetLowering::LowerGET_ACTIVE_LANE_MASK(SDValue Op,
static unsigned getSVEOpcodeForFPToInt(unsigned Opc) {
switch (Opc) {
+ case ISD::FP_TO_UINT_SAT:
case ISD::FP_TO_UINT:
return AArch64ISD::FCVTZU_MERGE_PASSTHRU;
+ case ISD::FP_TO_SINT_SAT:
case ISD::FP_TO_SINT:
return AArch64ISD::FCVTZS_MERGE_PASSTHRU;
default:
@@ -34746,15 +34750,25 @@ SDValue AArch64TargetLowering::tryLowerFPToIntToSVE(SDValue Op,
if (Op->isStrictFPOpcode())
return SDValue();
+ unsigned Opc = Op.getOpcode();
EVT InVT = Op.getOperand(0).getValueType();
EVT VT = Op.getValueType();
+ // bf16 inputs need promotion before conversion.
+ if (InVT.getVectorElementType() == MVT::bf16)
+ return SDValue();
+
+ // Only saturation to the destination type is natively supported.
+ if ((Opc == ISD::FP_TO_UINT_SAT || Opc == ISD::FP_TO_SINT_SAT) &&
+ VT.getVectorElementType() != cast<VTSDNode>(Op.getOperand(1))->getVT())
+ return SDValue();
+
SDLoc DL(Op);
if (VT.isScalableVector()) {
// Optimize the i1 case by using setcc.
if (VT.getVectorElementType() == MVT::i1) {
EVT CvtVT = getPromotedVTForPredicate(VT);
- SDValue Cvt = DAG.getNode(Op.getOpcode(), DL, CvtVT, Op.getOperand(0));
+ SDValue Cvt = DAG.getNode(Opc, DL, CvtVT, Op.getOperand(0));
SDValue Zero = DAG.getConstant(0, DL, CvtVT);
return DAG.getSetCC(DL, VT, Cvt, Zero, ISD::SETNE);
}
@@ -34767,10 +34781,15 @@ SDValue AArch64TargetLowering::tryLowerFPToIntToSVE(SDValue Op,
Operands.push_back(getPredicateForVector(DAG, DL, VT));
Operands.push_back(Op.getOperand(0));
Operands.push_back(DAG.getPOISON(VT));
- return DAG.getNode(getSVEOpcodeForFPToInt(Op.getOpcode()), DL, VT, Operands,
+ return DAG.getNode(getSVEOpcodeForFPToInt(Opc), DL, VT, Operands,
Op->getFlags());
}
+ // FIXME: LowerFixedLengthFPToIntToSVE doesn't properly implement
+ // saturation yet.
+ if (VT.getScalarSizeInBits() < InVT.getScalarSizeInBits())
+ return SDValue();
+
bool UseSVE = !Subtarget->isNeonAvailable();
if (useSVEForFixedLengthVectorVT(VT, UseSVE) ||
useSVEForFixedLengthVectorVT(InVT, UseSVE))
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int-sat.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int-sat.ll
index cccc98358e416..67fcb506c64b2 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int-sat.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int-sat.ll
@@ -8,39 +8,10 @@ target triple = "aarch64"
define void @test_signed_v8f32_v8i32(ptr %p) {
; CHECK-LABEL: test_signed_v8f32_v8i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-NEXT: sub x9, sp, #48
-; CHECK-NEXT: mov x29, sp
-; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0
-; CHECK-NEXT: .cfi_def_cfa w29, 16
-; CHECK-NEXT: .cfi_offset w30, -8
-; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: ptrue p0.s, vl8
; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
-; CHECK-NEXT: mov z1.s, z0.s[7]
-; CHECK-NEXT: mov z2.s, z0.s[6]
-; CHECK-NEXT: mov z3.s, z0.s[5]
-; CHECK-NEXT: fcvtzs w8, s1
-; CHECK-NEXT: mov z1.s, z0.s[4]
-; CHECK-NEXT: fcvtzs w9, s2
-; CHECK-NEXT: fcvtzs w10, s3
-; CHECK-NEXT: mov z2.s, z0.s[3]
-; CHECK-NEXT: mov z3.s, z0.s[2]
-; CHECK-NEXT: fcvtzs w11, s1
-; CHECK-NEXT: mov z1.s, z0.s[1]
-; CHECK-NEXT: fcvtzs w12, s2
-; CHECK-NEXT: stp w9, w8, [sp, #24]
-; CHECK-NEXT: fcvtzs w8, s3
-; CHECK-NEXT: fcvtzs w9, s0
-; CHECK-NEXT: stp w11, w10, [sp, #16]
-; CHECK-NEXT: fcvtzs w10, s1
-; CHECK-NEXT: stp w8, w12, [sp, #8]
-; CHECK-NEXT: mov x8, sp
-; CHECK-NEXT: stp w9, w10, [sp]
-; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8]
+; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
; CHECK-NEXT: st1w { z0.s }, p0, [x0]
-; CHECK-NEXT: mov sp, x29
-; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret
%ld = load <8 x float>, ptr %p
%cvt = call <8 x i32> @llvm.fptosi.sat(<8 x float> %ld)
@@ -51,44 +22,15 @@ define void @test_signed_v8f32_v8i32(ptr %p) {
define void @test_signed_v8f32_v8i16(ptr %p) {
; CHECK-LABEL: test_signed_v8f32_v8i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-NEXT: sub x9, sp, #48
-; CHECK-NEXT: mov x29, sp
-; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0
-; CHECK-NEXT: .cfi_def_cfa w29, 16
-; CHECK-NEXT: .cfi_offset w30, -8
-; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: ptrue p0.s, vl8
+; CHECK-NEXT: mov z1.s, #32767 // =0x7fff
; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
-; CHECK-NEXT: mov z1.s, z0.s[7]
-; CHECK-NEXT: mov z2.s, z0.s[6]
-; CHECK-NEXT: mov z3.s, z0.s[5]
-; CHECK-NEXT: fcvtzs w8, s1
-; CHECK-NEXT: mov z1.s, z0.s[4]
-; CHECK-NEXT: fcvtzs w9, s2
-; CHECK-NEXT: fcvtzs w10, s3
-; CHECK-NEXT: mov z2.s, z0.s[3]
-; CHECK-NEXT: mov z3.s, z0.s[2]
-; CHECK-NEXT: fcvtzs w11, s1
-; CHECK-NEXT: mov z1.s, z0.s[1]
-; CHECK-NEXT: fcvtzs w12, s2
-; CHECK-NEXT: stp w9, w8, [sp, #24]
-; CHECK-NEXT: fcvtzs w8, s3
-; CHECK-NEXT: fcvtzs w9, s0
-; CHECK-NEXT: mov z0.s, #32767 // =0x7fff
-; CHECK-NEXT: stp w11, w10, [sp, #16]
-; CHECK-NEXT: fcvtzs w10, s1
-; CHECK-NEXT: stp w8, w12, [sp, #8]
-; CHECK-NEXT: mov x8, sp
-; CHECK-NEXT: stp w9, w10, [sp]
-; CHECK-NEXT: ld1w { z1.s }, p0/z, [x8]
+; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT: mov z1.s, #-32768 // =0xffffffffffff8000
; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK-NEXT: str q0, [x0]
-; CHECK-NEXT: mov sp, x29
-; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret
%ld = load <8 x float>, ptr %p
%cvt = call <8 x i16> @llvm.fptosi.sat(<8 x float> %ld)
@@ -99,29 +41,11 @@ define void @test_signed_v8f32_v8i16(ptr %p) {
define void @test_signed_v4f32_v4i64(ptr %p) {
; CHECK-LABEL: test_signed_v4f32_v4i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-NEXT: sub x9, sp, #48
-; CHECK-NEXT: mov x29, sp
-; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0
-; CHECK-NEXT: .cfi_def_cfa w29, 16
-; CHECK-NEXT: .cfi_offset w30, -8
-; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ptrue p0.d, vl4
-; CHECK-NEXT: mov s1, v0.s[3]
-; CHECK-NEXT: mov s2, v0.s[2]
-; CHECK-NEXT: mov s3, v0.s[1]
-; CHECK-NEXT: fcvtzs x11, s0
-; CHECK-NEXT: fcvtzs x8, s1
-; CHECK-NEXT: fcvtzs x9, s2
-; CHECK-NEXT: fcvtzs x10, s3
-; CHECK-NEXT: stp x9, x8, [sp, #16]
-; CHECK-NEXT: mov x8, sp
-; CHECK-NEXT: stp x11, x10, [sp]
-; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8]
+; CHECK-NEXT: uunpklo z0.d, z0.s
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
-; CHECK-NEXT: mov sp, x29
-; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret
%ld = load <4 x float>, ptr %p
%cvt = call <4 x i64> @llvm.fptosi.sat(<4 x float> %ld)
@@ -135,19 +59,14 @@ define void @test_signed_v4f64_v4i32(ptr %p) {
; CHECK-LABEL: test_signed_v4f64_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d, vl4
+; CHECK-NEXT: mov z1.d, #0x7fffffff
+; CHECK-NEXT: mov z2.d, #0xffffffff80000000
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
-; CHECK-NEXT: mov z1.d, z0.d[1]
-; CHECK-NEXT: fcvtzs w8, d0
-; CHECK-NEXT: fcvtzs w9, d1
-; CHECK-NEXT: mov z1.d, z0.d[2]
-; CHECK-NEXT: mov z0.d, z0.d[3]
-; CHECK-NEXT: fmov s2, w8
-; CHECK-NEXT: fcvtzs w8, d1
-; CHECK-NEXT: mov v2.s[1], w9
-; CHECK-NEXT: mov v2.s[2], w8
-; CHECK-NEXT: fcvtzs w8, d0
-; CHECK-NEXT: mov v2.s[3], w8
-; CHECK-NEXT: str q2, [x0]
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: smax z0.d, p0/m, z0.d, z2.d
+; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
+; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
%ld = load <4 x double>, ptr %p
%cvt = call <4 x i32> @llvm.fptosi.sat(<4 x double> %ld)
@@ -158,41 +77,24 @@ define void @test_signed_v4f64_v4i32(ptr %p) {
define void @test_signed_v8f64_v8i32(ptr %p) {
; CHECK-LABEL: test_signed_v8f64_v8i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-NEXT: sub x9, sp, #48
-; CHECK-NEXT: mov x29, sp
-; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0
-; CHECK-NEXT: .cfi_def_cfa w29, 16
-; CHECK-NEXT: .cfi_offset w30, -8
-; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: ptrue p0.d, vl4
; CHECK-NEXT: mov x8, #4 // =0x4
+; CHECK-NEXT: mov z2.d, #0x7fffffff
+; CHECK-NEXT: mov z3.d, #0xffffffff80000000
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
-; CHECK-NEXT: ld1d { z2.d }, p0/z, [x0]
+; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0]
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
+; CHECK-NEXT: smin z0.d, p0/m, z0.d, z2.d
+; CHECK-NEXT: smin z1.d, p0/m, z1.d, z2.d
+; CHECK-NEXT: smax z0.d, p0/m, z0.d, z3.d
+; CHECK-NEXT: smax z1.d, p0/m, z1.d, z3.d
+; CHECK-NEXT: ptrue p0.s, vl4
+; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
+; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s
+; CHECK-NEXT: splice z1.s, p0, z1.s, z0.s
; CHECK-NEXT: ptrue p0.s, vl8
-; CHECK-NEXT: mov z1.d, z0.d[3]
-; CHECK-NEXT: mov z3.d, z0.d[2]
-; CHECK-NEXT: fcvtzs w10, d0
-; CHECK-NEXT: fcvtzs w8, d1
-; CHECK-NEXT: mov z1.d, z0.d[1]
-; CHECK-NEXT: fcvtzs w9, d3
-; CHECK-NEXT: mov z3.d, z2.d[3]
-; CHECK-NEXT: mov z0.d, z2.d[2]
-; CHECK-NEXT: fcvtzs w11, d1
-; CHECK-NEXT: mov z1.d, z2.d[1]
-; CHECK-NEXT: fcvtzs w12, d3
-; CHECK-NEXT: stp w9, w8, [sp, #24]
-; CHECK-NEXT: fcvtzs w8, d0
-; CHECK-NEXT: fcvtzs w9, d2
-; CHECK-NEXT: stp w10, w11, [sp, #16]
-; CHECK-NEXT: fcvtzs w10, d1
-; CHECK-NEXT: stp w8, w12, [sp, #8]
-; CHECK-NEXT: mov x8, sp
-; CHECK-NEXT: stp w9, w10, [sp]
-; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8]
-; CHECK-NEXT: st1w { z0.s }, p0, [x0]
-; CHECK-NEXT: mov sp, x29
-; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
+; CHECK-NEXT: st1w { z1.s }, p0, [x0]
; CHECK-NEXT: ret
%ld = load <8 x double>, ptr %p
%cvt = call <8 x i32> @llvm.fptosi.sat(<8 x double> %ld)
@@ -205,65 +107,22 @@ define void @test_signed_v8f64_v8i16(ptr %p) {
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d, vl4
; CHECK-NEXT: mov x8, #4 // =0x4
+; CHECK-NEXT: mov z2.d, #32767 // =0x7fff
+; CHECK-NEXT: mov z3.d, #-32768 // =0xffffffffffff8000
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0]
-; CHECK-NEXT: mov w8, #32767 // =0x7fff
-; CHECK-NEXT: fcvtzs w9, d0
-; CHECK-NEXT: mov z2.d, z1.d[1]
-; CHECK-NEXT: fcvtzs w12, d1
-; CHECK-NEXT: fcvtzs w10, d2
-; CHECK-NEXT: mov z2.d, z1.d[2]
-; CHECK-NEXT: mov z1.d, z1.d[3]
-; CHECK-NEXT: cmp w9, w8
-; CHECK-NEXT: csel w11, w9, w8, lt
-; CHECK-NEXT: mov w9, #-32768 // =0xffff8000
-; CHECK-NEXT: cmn w11, #8, lsl #12 // =32768
-; CHECK-NEXT: fcvtzs w13, d2
-; CHECK-NEXT: csel w11, w11, w9, gt
-; CHECK-NEXT: cmp w10, w8
-; CHECK-NEXT: csel w10, w10, w8, lt
-; CHECK-NEXT: cmn w10, #8, lsl #12 // =32768
-; CHECK-NEXT: csel w10, w10, w9, gt
-; CHECK-NEXT: cmp w12, w8
-; CHECK-NEXT: csel w12, w12, w8, lt
-; CHECK-NEXT: cmn w12, #8, lsl #12 // =32768
-; CHECK-NEXT: csel w12, w12, w9, gt
-; CHECK-NEXT: cmp w13, w8
-; CHECK-NEXT: fmov s2, w12
-; CHECK-NEXT: csel w12, w13, w8, lt
-; CHECK-NEXT: cmn w12, #8, lsl #12 // =32768
-; CHECK-NEXT: csel w12, w12, w9, gt
-; CHECK-NEXT: mov v2.h[1], w10
-; CHECK-NEXT: fcvtzs w10, d1
-; CHECK-NEXT: mov z1.d, z0.d[1]
-; CHECK-NEXT: mov v2.h[2], w12
-; CHECK-NEXT: cmp w10, w8
-; CHECK-NEXT: csel w10, w10, w8, lt
-; CHECK-NEXT: cmn w10, #8, lsl #12 // =32768
-; CHECK-NEXT: csel w10, w10, w9, gt
-; CHECK-NEXT: mov v2.h[3], w10
-; CHECK-NEXT: fcvtzs w10, d1
-; CHECK-NEXT: mov z1.d, z0.d[2]
-; CHECK-NEXT: mov z0.d, z0.d[3]
-; CHECK-NEXT: mov v2.h[4], w11
-; CHECK-NEXT: cmp w10, w8
-; CHECK-NEXT: fcvtzs w11, d1
-; CHECK-NEXT: csel w10, w10, w8, lt
-; CHECK-NEXT: cmn w10, #8, lsl #12 // =32768
-; CHECK-NEXT: csel w10, w10, w9, gt
-; CHECK-NEXT: mov v2.h[5], w10
-; CHECK-NEXT: cmp w11, w8
-; CHECK-NEXT: fcvtzs w10, d0
-; CHECK-NEXT: csel w11, w11, w8, lt
-; CHECK-NEXT: cmn w11, #8, lsl #12 // =32768
-; CHECK-NEXT: csel w11, w11, w9, gt
-; CHECK-NEXT: mov v2.h[6], w11
-; CHECK-NEXT: cmp w10, w8
-; CHECK-NEXT: csel w8, w10, w8, lt
-; CHECK-NEXT: cmn w8, #8, lsl #12 // =32768
-; CHECK-NEXT: csel w8, w8, w9, gt
-; CHECK-NEXT: mov v2.h[7], w8
-; CHECK-NEXT: str q2, [x0]
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
+; CHECK-NEXT: smin z0.d, p0/m, z0.d, z2.d
+; CHECK-NEXT: smin z1.d, p0/m, z1.d, z2.d
+; CHECK-NEXT: smax z0.d, p0/m, z0.d, z3.d
+; CHECK-NEXT: smax z1.d, p0/m, z1.d, z3.d
+; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
+; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s
+; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
+; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h
+; CHECK-NEXT: mov v1.d[1], v0.d[0]
+; CHECK-NEXT: str q1, [x0]
; CHECK-NEXT: ret
%ld = load <8 x double>, ptr %p
%cvt = call <8 x i16> @llvm.fptosi.sat(<8 x double> %ld)
@@ -274,29 +133,10 @@ define void @test_signed_v8f64_v8i16(ptr %p) {
define void @test_signed_v4f64_v4i64(ptr %p) {
; CHECK-LABEL: test_signed_v4f64_v4i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-NEXT: sub x9, sp, #48
-; CHECK-NEXT: mov x29, sp
-; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0
-; CHECK-NEXT: .cfi_def_cfa w29, 16
-; CHECK-NEXT: .cfi_offset w30, -8
-; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: ptrue p0.d, vl4
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
-; CHECK-NEXT: mov z1.d, z0.d[3]
-; CHECK-NEXT: mov z2.d, z0.d[2]
-; CHECK-NEXT: fcvtzs x10, d0
-; CHECK-NEXT: fcvtzs x8, d1
-; CHECK-NEXT: mov z1.d, z0.d[1]
-; CHECK-NEXT: fcvtzs x9, d2
-; CHECK-NEXT: fcvtzs x11, d1
-; CHECK-NEXT: stp x9, x8, [sp, #16]
-; CHECK-NEXT: mov x8, sp
-; CHECK-NEXT: stp x10, x11, [sp]
-; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8]
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
-; CHECK-NEXT: mov sp, x29
-; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret
%ld = load <4 x double>, ptr %p
%cvt = call <4 x i64> @llvm.fptosi.sat(<4 x double> %ld)
@@ -310,67 +150,10 @@ define void @test_signed_v4f64_v4i64(ptr %p) {
define void @test_signed_v16f16_v16i16(ptr %p) {
; CHECK-LABEL: test_signed_v16f16_v16i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-NEXT: sub x9, sp, #48
-; CHECK-NEXT: mov x29, sp
-; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0
-; CHECK-NEXT: .cfi_def_cfa w29, 16
-; CHECK-NEXT: .cfi_offset w30, -8
-; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: ptrue p0.h, vl16
-; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
-; CHECK-NEXT: mov z1.h, z0.h[15]
-; CHECK-NEXT: mov z2.h, z0.h[14]
-; CHECK-NEXT: fcvtzs h3, h0
-; CHECK-NEXT: mov z4.h, z0.h[13]
-; CHECK-NEXT: mov z5.h, z0.h[12]
-; CHECK-NEXT: mov z6.h, z0.h[11]
-; CHECK-NEXT: mov z7.h, z0.h[10]
-; CHECK-NEXT: fcvtzs h1, h1
-; CHECK-NEXT: fcvtzs h2, h2
-; CHECK-NEXT: str h3, [sp]
-; CHECK-NEXT: mov z3.h, z0.h[9]
-; CHECK-NEXT: fcvtzs h4, h4
-; CHECK-NEXT: fcvtzs h5, h5
-; CHECK-NEXT: fcvtzs h6, h6
-; CHECK-NEXT: fcvtzs h7, h7
-; CHECK-NEXT: str h1, [sp, #30]
-; CHECK-NEXT: mov z1.h, z0.h[8]
-; CHECK-NEXT: fcvtzs h3, h3
-; CHECK-NEXT: str h2, [sp, #28]
-; CHECK-NEXT: mov z2.h, z0.h[7]
-; CHECK-NEXT: str h4, [sp, #26]
-; CHECK-NEXT: mov z4.h, z0.h[6]
-; CHECK-NEXT: fcvtzs h1, h1
-; CHECK-NEXT: str h5, [sp, #24]
-; CHECK-NEXT: mov z5.h, z0.h[5]
-; CHECK-NEXT: fcvtzs h2, h2
-; CHECK-NEXT: str h6, [sp, #22]
-; CHECK-NEXT: mov z6.h, z0.h[4]
-; CHECK-NEXT: str h7, [sp, #20]
-; CHECK-NEXT: mov z7.h, z0.h[3]
-; CHECK-NEXT: fcvtzs h4, h4
-; CHECK-NEXT: str h3, [sp, #18]
-; CHECK-NEXT: mov z3.h, z0.h[2]
-; CHECK-NEXT: mov z0.h, z0.h[1]
-; CHECK-NEXT: fcvtzs h5, h5
-; CHECK-NEXT: str h1, [sp, #16]
-; CHECK-NEXT: fcvtzs h1, h6
-; CHECK-NEXT: str h2, [sp, #14]
-; CHECK-NEXT: fcvtzs h2, h7
-; CHECK-NEXT: fcvtzs h3, h3
-; CHECK-NEXT: fcvtzs h0, h0
-; CHECK-NEXT: str h4, [sp, #12]
-; CHECK-NEXT: str h5, [sp, #10]
-; CHECK-NEXT: str h1, [sp, #8]
-; CHECK-NEXT: str h2, [sp, #6]
-; CHECK-NEXT: str h3, [sp, #4]
-; CHECK-NEXT: str h0, [sp, #2]
-; CHECK-NEXT: ld1h { z0.h }, p0/z, [x8]
+; CHECK-NEXT: fcvtzs z0.h, p0/m, z0.h
; CHECK-NEXT: st1h { z0.h }, p0, [x0]
-; CHECK-NEXT: mov sp, x29
-; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret
%ld = load <16 x half>, ptr %p
%cvt = call <16 x i16> @llvm.fptosi.sat(<16 x half> %ld)
@@ -381,39 +164,11 @@ define void @test_signed_v16f16_v16i16(ptr %p) {
define void @test_signed_v8f16_v8i32(ptr %p) {
; CHECK-LABEL: test_signed_v8f16_v8i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-NEXT: sub x9, sp, #48
-; CHECK-NEXT: mov x29, sp
-; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0
-; CHECK-NEXT: .cfi_def_cfa w29, 16
-; CHECK-NEXT: .cfi_offset w30, -8
-; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ptrue p0.s, vl8
-; CHECK-NEXT: mov h1, v0.h[7]
-; CHECK-NEXT: mov h2, v0.h[6]
-; CHECK-NEXT: mov h3, v0.h[5]
-; CHECK-NEXT: mov h4, v0.h[4]
-; CHECK-NEXT: fcvtzs w8, h1
-; CHECK-NEXT: mov h1, v0.h[3]
-; CHECK-NEXT: fcvtzs w9, h2
-; CHECK-NEXT: mov h2, v0.h[2]
-; CHECK-NEXT: fcvtzs w10, h3
-; CHECK-NEXT: mov h3, v0.h[1]
-; CHECK-NEXT: fcvtzs w11, h4
-; CHECK-NEXT: fcvtzs w12, h1
-; CHECK-NEXT: stp w9, w8, [sp, #24]
-; CHECK-NEXT: fcvtzs w8, h2
-; CHECK-NEXT: fcvtzs w9, h3
-; CHECK-NEXT: stp w11, w10, [sp, #16]
-; CHECK-NEXT: fcvtzs w10, h0
-; CHECK-NEXT: stp w8, w12, [sp, #8]
-; CHECK-NEXT: mov x8, sp
-; CHECK-NEXT: stp w10, w9, [sp]
-; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8]
+; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h
; CHECK-NEXT: st1w { z0.s }, p0, [x0]
-; CHECK-NEXT: mov sp, x29
-; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret
%ld = load <8 x half>, ptr %p
%cvt = call <8 x i32> @llvm.fptosi.sat(<8 x half> %ld)
@@ -424,65 +179,18 @@ define void @test_signed_v8f16_v8i32(ptr %p) {
define void @test_signed_v16f16_v16i32(ptr %p) {
; CHECK-LABEL: test_signed_v16f16_v16i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-NEXT: sub x9, sp, #80
-; CHECK-NEXT: mov x29, sp
-; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0
-; CHECK-NEXT: .cfi_def_cfa w29, 16
-; CHECK-NEXT: .cfi_offset w30, -8
-; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: ptrue p0.h, vl16
+; CHECK-NEXT: mov x8, #8 // =0x8
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
; CHECK-NEXT: ptrue p0.s, vl8
-; CHECK-NEXT: mov h1, v0.h[7]
-; CHECK-NEXT: mov h2, v0.h[6]
-; CHECK-NEXT: mov h3, v0.h[5]
-; CHECK-NEXT: mov h4, v0.h[4]
-; CHECK-NEXT: mov h5, v0.h[3]
-; CHECK-NEXT: fcvtzs w8, h1
-; CHECK-NEXT: mov h1, v0.h[2]
-; CHECK-NEXT: fcvtzs w9, h2
-; CHECK-NEXT: fcvtzs w10, h3
-; CHECK-NEXT: mov h3, v0.h[1]
-; CHECK-NEXT: fcvtzs w11, h4
-; CHECK-NEXT: movprfx z2, z0
-; CHECK-NEXT: ext z2.b, z2.b, z0.b, #16
-; CHECK-NEXT: fcvtzs w12, h5
-; CHECK-NEXT: stp w9, w8, [sp, #56]
-; CHECK-NEXT: fcvtzs w8, h1
-; CHECK-NEXT: mov h4, v2.h[7]
-; CHECK-NEXT: mov h1, v2.h[6]
-; CHECK-NEXT: fcvtzs w9, h3
-; CHECK-NEXT: mov h3, v2.h[5]
-; CHECK-NEXT: stp w11, w10, [sp, #48]
-; CHECK-NEXT: fcvtzs w10, h0
-; CHECK-NEXT: mov h0, v2.h[4]
-; CHECK-NEXT: stp w8, w12, [sp, #40]
-; CHECK-NEXT: fcvtzs w11, h4
-; CHECK-NEXT: mov h4, v2.h[3]
-; CHECK-NEXT: fcvtzs w12, h1
-; CHECK-NEXT: mov h1, v2.h[2]
-; CHECK-NEXT: fcvtzs w8, h3
-; CHECK-NEXT: mov h3, v2.h[1]
-; CHECK-NEXT: stp w10, w9, [sp, #32]
-; CHECK-NEXT: fcvtzs w9, h0
-; CHECK-NEXT: fcvtzs w10, h4
-; CHECK-NEXT: stp w12, w11, [sp, #24]
-; CHECK-NEXT: fcvtzs w11, h1
-; CHECK-NEXT: fcvtzs w12, h3
-; CHECK-NEXT: stp w9, w8, [sp, #16]
-; CHECK-NEXT: fcvtzs w8, h2
-; CHECK-NEXT: stp w11, w10, [sp, #8]
-; CHECK-NEXT: stp w8, w12, [sp]
-; CHECK-NEXT: mov x8, sp
-; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8]
-; CHECK-NEXT: add x8, sp, #32
-; CHECK-NEXT: ld1w { z1.s }, p0/z, [x8]
-; CHECK-NEXT: mov x8, #8 // =0x8
-; CHECK-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2]
-; CHECK-NEXT: st1w { z1.s }, p0, [x0]
-; CHECK-NEXT: mov sp, x29
-; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
+; CHECK-NEXT: movprfx z1, z0
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: uunpklo z1.s, z1.h
+; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h
+; CHECK-NEXT: fcvtzs z1.s, p0/m, z1.h
+; CHECK-NEXT: st1w { z0.s }, p0, [x0]
+; CHECK-NEXT: st1w { z1.s }, p0, [x0, x8, lsl #2]
; CHECK-NEXT: ret
%ld = load <16 x half>, ptr %p
%cvt = call <16 x i32> @llvm.fptosi.sat(<16 x half> %ld)
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll b/llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll
index fe4219c99b551..f6e1053fdc14d 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll
@@ -34,17 +34,14 @@ define <4 x i64> @llrint_v4i64_v4f16(<4 x half> %x) nounwind {
; CHECK-LABEL: llrint_v4i64_v4f16:
; CHECK: // %bb.0:
; CHECK-NEXT: frintx v0.4h, v0.4h
-; CHECK-NEXT: mov h1, v0.h[2]
-; CHECK-NEXT: mov h2, v0.h[3]
-; CHECK-NEXT: mov h3, v0.h[1]
-; CHECK-NEXT: fcvtzs x9, h0
-; CHECK-NEXT: fcvtzs x8, h1
-; CHECK-NEXT: fcvtzs x10, h2
-; CHECK-NEXT: fcvtzs x11, h3
-; CHECK-NEXT: fmov d0, x9
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: mov v0.d[1], x11
-; CHECK-NEXT: mov v1.d[1], x10
+; CHECK-NEXT: ptrue p0.d, vl4
+; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: uunpklo z0.d, z0.s
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
+; CHECK-NEXT: movprfx z1, z0
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT: ret
%a = call <4 x i64> @llvm.llrint.v4i64.v4f16(<4 x half> %x)
ret <4 x i64> %a
@@ -56,29 +53,23 @@ define <8 x i64> @llrint_v8i64_v8f16(<8 x half> %x) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: frintx v0.4h, v0.4h
+; CHECK-NEXT: ptrue p0.d, vl4
; CHECK-NEXT: frintx v1.4h, v1.4h
-; CHECK-NEXT: mov h3, v0.h[2]
-; CHECK-NEXT: mov h4, v0.h[1]
-; CHECK-NEXT: mov h5, v0.h[3]
-; CHECK-NEXT: fcvtzs x8, h0
-; CHECK-NEXT: mov h2, v1.h[2]
-; CHECK-NEXT: mov h6, v1.h[3]
-; CHECK-NEXT: mov h7, v1.h[1]
-; CHECK-NEXT: fcvtzs x10, h1
-; CHECK-NEXT: fcvtzs x11, h3
-; CHECK-NEXT: fcvtzs x12, h4
-; CHECK-NEXT: fcvtzs x13, h5
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: fcvtzs x9, h2
-; CHECK-NEXT: fcvtzs x14, h6
-; CHECK-NEXT: fcvtzs x15, h7
-; CHECK-NEXT: fmov d2, x10
-; CHECK-NEXT: fmov d1, x11
-; CHECK-NEXT: mov v0.d[1], x12
-; CHECK-NEXT: fmov d3, x9
-; CHECK-NEXT: mov v1.d[1], x13
-; CHECK-NEXT: mov v2.d[1], x15
-; CHECK-NEXT: mov v3.d[1], x14
+; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: uunpklo z1.s, z1.h
+; CHECK-NEXT: uunpklo z0.d, z0.s
+; CHECK-NEXT: uunpklo z1.d, z1.s
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
+; CHECK-NEXT: movprfx z2, z1
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z1.h
+; CHECK-NEXT: movprfx z1, z0
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
+; CHECK-NEXT: movprfx z3, z2
+; CHECK-NEXT: ext z3.b, z3.b, z2.b, #16
+; CHECK-NEXT: // kill: def $q2 killed $q2 killed $z2
+; CHECK-NEXT: // kill: def $q3 killed $q3 killed $z3
; CHECK-NEXT: ret
%a = call <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half> %x)
ret <8 x i64> %a
@@ -88,56 +79,43 @@ declare <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half>)
define <16 x i64> @llrint_v16i64_v16f16(<16 x half> %x) nounwind {
; CHECK-LABEL: llrint_v16i64_v16f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov d2, v1.d[1]
-; CHECK-NEXT: frintx v1.4h, v1.4h
-; CHECK-NEXT: mov d3, v0.d[1]
+; CHECK-NEXT: mov d2, v0.d[1]
+; CHECK-NEXT: mov d3, v1.d[1]
; CHECK-NEXT: frintx v0.4h, v0.4h
+; CHECK-NEXT: frintx v1.4h, v1.4h
+; CHECK-NEXT: ptrue p0.d, vl4
; CHECK-NEXT: frintx v2.4h, v2.4h
-; CHECK-NEXT: mov h5, v1.h[1]
; CHECK-NEXT: frintx v3.4h, v3.4h
-; CHECK-NEXT: mov h4, v1.h[2]
-; CHECK-NEXT: mov h6, v0.h[2]
-; CHECK-NEXT: fcvtzs x8, h1
-; CHECK-NEXT: mov h7, v0.h[3]
-; CHECK-NEXT: mov h16, v0.h[1]
-; CHECK-NEXT: fcvtzs x9, h0
-; CHECK-NEXT: mov h1, v1.h[3]
-; CHECK-NEXT: mov h0, v2.h[3]
-; CHECK-NEXT: mov h17, v2.h[2]
-; CHECK-NEXT: fcvtzs x12, h5
-; CHECK-NEXT: mov h5, v3.h[2]
-; CHECK-NEXT: fcvtzs x10, h4
-; CHECK-NEXT: fcvtzs x11, h2
-; CHECK-NEXT: mov h18, v3.h[3]
-; CHECK-NEXT: fcvtzs x14, h3
-; CHECK-NEXT: mov h3, v3.h[1]
-; CHECK-NEXT: mov h2, v2.h[1]
-; CHECK-NEXT: fcvtzs x13, h6
-; CHECK-NEXT: fmov d4, x8
-; CHECK-NEXT: fcvtzs x8, h0
-; CHECK-NEXT: fmov d0, x9
-; CHECK-NEXT: fcvtzs x9, h17
-; CHECK-NEXT: fcvtzs x16, h5
-; CHECK-NEXT: fcvtzs x15, h16
-; CHECK-NEXT: fcvtzs x17, h7
-; CHECK-NEXT: fmov d6, x11
-; CHECK-NEXT: fcvtzs x11, h18
-; CHECK-NEXT: fcvtzs x18, h3
-; CHECK-NEXT: fmov d5, x10
-; CHECK-NEXT: fcvtzs x10, h2
-; CHECK-NEXT: fcvtzs x0, h1
-; CHECK-NEXT: fmov d2, x14
-; CHECK-NEXT: fmov d1, x13
-; CHECK-NEXT: fmov d7, x9
-; CHECK-NEXT: fmov d3, x16
-; CHECK-NEXT: mov v0.d[1], x15
-; CHECK-NEXT: mov v4.d[1], x12
-; CHECK-NEXT: mov v1.d[1], x17
-; CHECK-NEXT: mov v2.d[1], x18
-; CHECK-NEXT: mov v5.d[1], x0
-; CHECK-NEXT: mov v3.d[1], x11
-; CHECK-NEXT: mov v6.d[1], x10
-; CHECK-NEXT: mov v7.d[1], x8
+; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: uunpklo z1.s, z1.h
+; CHECK-NEXT: uunpklo z2.s, z2.h
+; CHECK-NEXT: uunpklo z3.s, z3.h
+; CHECK-NEXT: uunpklo z0.d, z0.s
+; CHECK-NEXT: uunpklo z1.d, z1.s
+; CHECK-NEXT: uunpklo z2.d, z2.s
+; CHECK-NEXT: uunpklo z3.d, z3.s
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
+; CHECK-NEXT: movprfx z4, z1
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z1.h
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.h
+; CHECK-NEXT: movprfx z6, z3
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z3.h
+; CHECK-NEXT: movprfx z1, z0
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-NEXT: movprfx z5, z4
+; CHECK-NEXT: ext z5.b, z5.b, z4.b, #16
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT: // kill: def $q4 killed $q4 killed $z4
+; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
+; CHECK-NEXT: movprfx z3, z2
+; CHECK-NEXT: ext z3.b, z3.b, z2.b, #16
+; CHECK-NEXT: movprfx z7, z6
+; CHECK-NEXT: ext z7.b, z7.b, z6.b, #16
+; CHECK-NEXT: // kill: def $q2 killed $q2 killed $z2
+; CHECK-NEXT: // kill: def $q5 killed $q5 killed $z5
+; CHECK-NEXT: // kill: def $q6 killed $q6 killed $z6
+; CHECK-NEXT: // kill: def $q3 killed $q3 killed $z3
+; CHECK-NEXT: // kill: def $q7 killed $q7 killed $z7
; CHECK-NEXT: ret
%a = call <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half> %x)
ret <16 x i64> %a
@@ -147,128 +125,58 @@ declare <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half>)
define <32 x i64> @llrint_v32i64_v32f16(<32 x half> %x) nounwind {
; CHECK-LABEL: llrint_v32i64_v32f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-NEXT: sub x9, sp, #272
-; CHECK-NEXT: mov x29, sp
-; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0
-; CHECK-NEXT: mov d5, v0.d[1]
+; CHECK-NEXT: mov d4, v3.d[1]
+; CHECK-NEXT: mov d5, v2.d[1]
+; CHECK-NEXT: mov x9, #28 // =0x1c
+; CHECK-NEXT: mov d6, v1.d[1]
+; CHECK-NEXT: frintx v3.4h, v3.4h
+; CHECK-NEXT: mov d7, v0.d[1]
+; CHECK-NEXT: frintx v2.4h, v2.4h
+; CHECK-NEXT: frintx v1.4h, v1.4h
; CHECK-NEXT: frintx v0.4h, v0.4h
-; CHECK-NEXT: frintx v4.4h, v1.4h
-; CHECK-NEXT: mov d1, v1.d[1]
; CHECK-NEXT: ptrue p0.d, vl4
+; CHECK-NEXT: frintx v4.4h, v4.4h
; CHECK-NEXT: frintx v5.4h, v5.4h
-; CHECK-NEXT: mov h6, v0.h[3]
-; CHECK-NEXT: mov h7, v0.h[2]
-; CHECK-NEXT: mov h16, v0.h[1]
-; CHECK-NEXT: fcvtzs x12, h0
-; CHECK-NEXT: frintx v1.4h, v1.4h
-; CHECK-NEXT: frintx v0.4h, v2.4h
-; CHECK-NEXT: mov d2, v2.d[1]
-; CHECK-NEXT: mov h17, v5.h[3]
-; CHECK-NEXT: fcvtzs x9, h6
-; CHECK-NEXT: mov h6, v5.h[2]
-; CHECK-NEXT: fcvtzs x10, h7
-; CHECK-NEXT: fcvtzs x11, h16
-; CHECK-NEXT: mov h7, v5.h[1]
-; CHECK-NEXT: mov h16, v4.h[3]
-; CHECK-NEXT: frintx v2.4h, v2.4h
-; CHECK-NEXT: fcvtzs x13, h17
-; CHECK-NEXT: stp x10, x9, [sp, #48]
-; CHECK-NEXT: fcvtzs x9, h6
-; CHECK-NEXT: mov h6, v4.h[2]
-; CHECK-NEXT: fcvtzs x10, h7
-; CHECK-NEXT: mov h7, v4.h[1]
-; CHECK-NEXT: stp x12, x11, [sp, #32]
-; CHECK-NEXT: fcvtzs x11, h5
-; CHECK-NEXT: fcvtzs x12, h16
-; CHECK-NEXT: mov h5, v1.h[3]
-; CHECK-NEXT: stp x9, x13, [sp, #16]
-; CHECK-NEXT: fcvtzs x13, h6
-; CHECK-NEXT: mov h6, v1.h[2]
-; CHECK-NEXT: fcvtzs x9, h7
-; CHECK-NEXT: mov h7, v0.h[3]
-; CHECK-NEXT: stp x11, x10, [sp]
-; CHECK-NEXT: fcvtzs x10, h4
-; CHECK-NEXT: mov h4, v1.h[1]
-; CHECK-NEXT: fcvtzs x11, h5
-; CHECK-NEXT: mov h5, v0.h[2]
-; CHECK-NEXT: stp x13, x12, [sp, #112]
-; CHECK-NEXT: fcvtzs x12, h6
-; CHECK-NEXT: frintx v6.4h, v3.4h
-; CHECK-NEXT: fcvtzs x13, h7
-; CHECK-NEXT: mov d3, v3.d[1]
-; CHECK-NEXT: stp x10, x9, [sp, #96]
-; CHECK-NEXT: fcvtzs x9, h4
-; CHECK-NEXT: mov h4, v0.h[1]
-; CHECK-NEXT: fcvtzs x10, h1
-; CHECK-NEXT: mov h1, v2.h[3]
-; CHECK-NEXT: stp x12, x11, [sp, #80]
-; CHECK-NEXT: fcvtzs x11, h5
-; CHECK-NEXT: mov h5, v2.h[2]
-; CHECK-NEXT: fcvtzs x12, h4
-; CHECK-NEXT: mov h4, v2.h[1]
-; CHECK-NEXT: stp x10, x9, [sp, #64]
-; CHECK-NEXT: fcvtzs x9, h0
-; CHECK-NEXT: fcvtzs x10, h1
-; CHECK-NEXT: mov h0, v6.h[3]
-; CHECK-NEXT: frintx v1.4h, v3.4h
-; CHECK-NEXT: stp x11, x13, [sp, #176]
-; CHECK-NEXT: fcvtzs x11, h5
-; CHECK-NEXT: mov h3, v6.h[2]
-; CHECK-NEXT: fcvtzs x13, h4
-; CHECK-NEXT: mov h4, v6.h[1]
-; CHECK-NEXT: stp x9, x12, [sp, #160]
-; CHECK-NEXT: fcvtzs x9, h2
-; CHECK-NEXT: fcvtzs x12, h0
-; CHECK-NEXT: mov h0, v1.h[3]
-; CHECK-NEXT: mov h2, v1.h[2]
-; CHECK-NEXT: stp x11, x10, [sp, #144]
-; CHECK-NEXT: fcvtzs x10, h3
-; CHECK-NEXT: mov h3, v1.h[1]
-; CHECK-NEXT: fcvtzs x11, h4
-; CHECK-NEXT: stp x9, x13, [sp, #128]
-; CHECK-NEXT: fcvtzs x9, h6
-; CHECK-NEXT: fcvtzs x13, h0
-; CHECK-NEXT: stp x10, x12, [sp, #240]
-; CHECK-NEXT: fcvtzs x10, h2
-; CHECK-NEXT: fcvtzs x12, h3
-; CHECK-NEXT: stp x9, x11, [sp, #224]
-; CHECK-NEXT: fcvtzs x9, h1
-; CHECK-NEXT: stp x10, x13, [sp, #208]
-; CHECK-NEXT: add x10, sp, #96
-; CHECK-NEXT: stp x9, x12, [sp, #192]
-; CHECK-NEXT: add x9, sp, #32
-; CHECK-NEXT: ld1d { z0.d }, p0/z, [x9]
-; CHECK-NEXT: mov x9, sp
-; CHECK-NEXT: ld1d { z2.d }, p0/z, [x10]
-; CHECK-NEXT: ld1d { z1.d }, p0/z, [x9]
-; CHECK-NEXT: add x9, sp, #192
-; CHECK-NEXT: add x10, sp, #64
-; CHECK-NEXT: ld1d { z3.d }, p0/z, [x9]
-; CHECK-NEXT: add x9, sp, #224
-; CHECK-NEXT: ld1d { z4.d }, p0/z, [x10]
-; CHECK-NEXT: add x10, sp, #128
-; CHECK-NEXT: ld1d { z5.d }, p0/z, [x9]
-; CHECK-NEXT: add x9, sp, #160
-; CHECK-NEXT: ld1d { z6.d }, p0/z, [x10]
-; CHECK-NEXT: mov x10, #28 // =0x1c
-; CHECK-NEXT: ld1d { z7.d }, p0/z, [x9]
+; CHECK-NEXT: frintx v6.4h, v6.4h
+; CHECK-NEXT: uunpklo z3.s, z3.h
+; CHECK-NEXT: frintx v7.4h, v7.4h
+; CHECK-NEXT: uunpklo z2.s, z2.h
+; CHECK-NEXT: uunpklo z1.s, z1.h
+; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: uunpklo z4.s, z4.h
+; CHECK-NEXT: uunpklo z5.s, z5.h
+; CHECK-NEXT: uunpklo z6.s, z6.h
+; CHECK-NEXT: uunpklo z3.d, z3.s
+; CHECK-NEXT: uunpklo z7.s, z7.h
+; CHECK-NEXT: uunpklo z2.d, z2.s
+; CHECK-NEXT: uunpklo z1.d, z1.s
+; CHECK-NEXT: uunpklo z0.d, z0.s
+; CHECK-NEXT: uunpklo z4.d, z4.s
+; CHECK-NEXT: uunpklo z5.d, z5.s
+; CHECK-NEXT: uunpklo z6.d, z6.s
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.h
+; CHECK-NEXT: uunpklo z7.d, z7.s
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.h
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.h
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.h
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.h
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.h
+; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.h
+; CHECK-NEXT: st1d { z4.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #24 // =0x18
-; CHECK-NEXT: st1d { z3.d }, p0, [x8, x10, lsl #3]
-; CHECK-NEXT: st1d { z5.d }, p0, [x8, x9, lsl #3]
+; CHECK-NEXT: st1d { z3.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #20 // =0x14
-; CHECK-NEXT: st1d { z6.d }, p0, [x8, x9, lsl #3]
+; CHECK-NEXT: st1d { z5.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #16 // =0x10
-; CHECK-NEXT: st1d { z7.d }, p0, [x8, x9, lsl #3]
+; CHECK-NEXT: st1d { z2.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #12 // =0xc
-; CHECK-NEXT: st1d { z4.d }, p0, [x8, x9, lsl #3]
+; CHECK-NEXT: st1d { z6.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #8 // =0x8
-; CHECK-NEXT: st1d { z2.d }, p0, [x8, x9, lsl #3]
-; CHECK-NEXT: mov x9, #4 // =0x4
; CHECK-NEXT: st1d { z1.d }, p0, [x8, x9, lsl #3]
+; CHECK-NEXT: mov x9, #4 // =0x4
+; CHECK-NEXT: st1d { z7.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: st1d { z0.d }, p0, [x8]
-; CHECK-NEXT: mov sp, x29
-; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret
%a = call <32 x i64> @llvm.llrint.v32i64.v32f16(<32 x half> %x)
ret <32 x i64> %a
@@ -304,17 +212,13 @@ define <4 x i64> @llrint_v4i64_v4f32(<4 x float> %x) nounwind {
; CHECK-LABEL: llrint_v4i64_v4f32:
; CHECK: // %bb.0:
; CHECK-NEXT: frintx v0.4s, v0.4s
-; CHECK-NEXT: mov s1, v0.s[2]
-; CHECK-NEXT: mov s2, v0.s[3]
-; CHECK-NEXT: mov s3, v0.s[1]
-; CHECK-NEXT: fcvtzs x9, s0
-; CHECK-NEXT: fcvtzs x8, s1
-; CHECK-NEXT: fcvtzs x10, s2
-; CHECK-NEXT: fcvtzs x11, s3
-; CHECK-NEXT: fmov d0, x9
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: mov v0.d[1], x11
-; CHECK-NEXT: mov v1.d[1], x10
+; CHECK-NEXT: ptrue p0.d, vl4
+; CHECK-NEXT: uunpklo z0.d, z0.s
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-NEXT: movprfx z1, z0
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT: ret
%a = call <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float> %x)
ret <4 x i64> %a
@@ -326,28 +230,20 @@ define <8 x i64> @llrint_v8i64_v8f32(<8 x float> %x) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: frintx v1.4s, v1.4s
; CHECK-NEXT: frintx v0.4s, v0.4s
-; CHECK-NEXT: mov s2, v1.s[2]
-; CHECK-NEXT: mov s3, v0.s[2]
-; CHECK-NEXT: mov s4, v0.s[1]
-; CHECK-NEXT: mov s5, v1.s[3]
-; CHECK-NEXT: mov s6, v1.s[1]
-; CHECK-NEXT: mov s7, v0.s[3]
-; CHECK-NEXT: fcvtzs x8, s0
-; CHECK-NEXT: fcvtzs x10, s1
-; CHECK-NEXT: fcvtzs x9, s2
-; CHECK-NEXT: fcvtzs x11, s3
-; CHECK-NEXT: fcvtzs x12, s4
-; CHECK-NEXT: fcvtzs x13, s5
-; CHECK-NEXT: fcvtzs x14, s6
-; CHECK-NEXT: fcvtzs x15, s7
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: fmov d2, x10
-; CHECK-NEXT: fmov d3, x9
-; CHECK-NEXT: fmov d1, x11
-; CHECK-NEXT: mov v0.d[1], x12
-; CHECK-NEXT: mov v2.d[1], x14
-; CHECK-NEXT: mov v1.d[1], x15
-; CHECK-NEXT: mov v3.d[1], x13
+; CHECK-NEXT: ptrue p0.d, vl4
+; CHECK-NEXT: uunpklo z1.d, z1.s
+; CHECK-NEXT: uunpklo z0.d, z0.s
+; CHECK-NEXT: movprfx z2, z1
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z1.s
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-NEXT: movprfx z1, z0
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-NEXT: movprfx z3, z2
+; CHECK-NEXT: ext z3.b, z3.b, z2.b, #16
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT: // kill: def $q2 killed $q2 killed $z2
+; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
+; CHECK-NEXT: // kill: def $q3 killed $q3 killed $z3
; CHECK-NEXT: ret
%a = call <8 x i64> @llvm.llrint.v8i64.v8f32(<8 x float> %x)
ret <8 x i64> %a
@@ -357,54 +253,37 @@ declare <8 x i64> @llvm.llrint.v8i64.v8f32(<8 x float>)
define <16 x i64> @llrint_v16i64_v16f32(<16 x float> %x) nounwind {
; CHECK-LABEL: llrint_v16i64_v16f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: frintx v3.4s, v3.4s
-; CHECK-NEXT: frintx v2.4s, v2.4s
; CHECK-NEXT: frintx v1.4s, v1.4s
; CHECK-NEXT: frintx v0.4s, v0.4s
-; CHECK-NEXT: mov s4, v3.s[2]
-; CHECK-NEXT: mov s5, v2.s[2]
-; CHECK-NEXT: mov s6, v2.s[1]
-; CHECK-NEXT: mov s7, v1.s[2]
-; CHECK-NEXT: fcvtzs x8, s3
-; CHECK-NEXT: mov s16, v0.s[2]
-; CHECK-NEXT: fcvtzs x9, s2
-; CHECK-NEXT: mov s17, v1.s[3]
-; CHECK-NEXT: mov s18, v0.s[1]
-; CHECK-NEXT: mov s19, v3.s[3]
-; CHECK-NEXT: fcvtzs x14, s1
-; CHECK-NEXT: mov s1, v1.s[1]
-; CHECK-NEXT: fcvtzs x10, s4
-; CHECK-NEXT: fcvtzs x11, s5
-; CHECK-NEXT: mov s5, v0.s[3]
-; CHECK-NEXT: mov s3, v3.s[1]
-; CHECK-NEXT: mov s2, v2.s[3]
-; CHECK-NEXT: fcvtzs x12, s6
-; CHECK-NEXT: fcvtzs x13, s7
-; CHECK-NEXT: fcvtzs x15, s16
-; CHECK-NEXT: fmov d6, x8
-; CHECK-NEXT: fcvtzs x8, s0
-; CHECK-NEXT: fmov d4, x9
-; CHECK-NEXT: fcvtzs x9, s17
-; CHECK-NEXT: fcvtzs x16, s5
-; CHECK-NEXT: fcvtzs x17, s18
-; CHECK-NEXT: fmov d7, x10
-; CHECK-NEXT: fmov d5, x11
-; CHECK-NEXT: fcvtzs x10, s1
-; CHECK-NEXT: fcvtzs x11, s19
-; CHECK-NEXT: fcvtzs x18, s3
-; CHECK-NEXT: fcvtzs x0, s2
-; CHECK-NEXT: fmov d3, x13
-; CHECK-NEXT: fmov d1, x15
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: fmov d2, x14
-; CHECK-NEXT: mov v4.d[1], x12
-; CHECK-NEXT: mov v3.d[1], x9
-; CHECK-NEXT: mov v7.d[1], x11
-; CHECK-NEXT: mov v0.d[1], x17
-; CHECK-NEXT: mov v1.d[1], x16
-; CHECK-NEXT: mov v2.d[1], x10
-; CHECK-NEXT: mov v5.d[1], x0
-; CHECK-NEXT: mov v6.d[1], x18
+; CHECK-NEXT: frintx v3.4s, v3.4s
+; CHECK-NEXT: frintx v2.4s, v2.4s
+; CHECK-NEXT: ptrue p0.d, vl4
+; CHECK-NEXT: uunpklo z1.d, z1.s
+; CHECK-NEXT: uunpklo z0.d, z0.s
+; CHECK-NEXT: uunpklo z3.d, z3.s
+; CHECK-NEXT: uunpklo z4.d, z2.s
+; CHECK-NEXT: movprfx z2, z1
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z1.s
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-NEXT: movprfx z6, z3
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z3.s
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.s
+; CHECK-NEXT: movprfx z1, z0
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-NEXT: movprfx z3, z2
+; CHECK-NEXT: ext z3.b, z3.b, z2.b, #16
+; CHECK-NEXT: movprfx z7, z6
+; CHECK-NEXT: ext z7.b, z7.b, z6.b, #16
+; CHECK-NEXT: movprfx z5, z4
+; CHECK-NEXT: ext z5.b, z5.b, z4.b, #16
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT: // kill: def $q2 killed $q2 killed $z2
+; CHECK-NEXT: // kill: def $q4 killed $q4 killed $z4
+; CHECK-NEXT: // kill: def $q6 killed $q6 killed $z6
+; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
+; CHECK-NEXT: // kill: def $q3 killed $q3 killed $z3
+; CHECK-NEXT: // kill: def $q7 killed $q7 killed $z7
+; CHECK-NEXT: // kill: def $q5 killed $q5 killed $z5
; CHECK-NEXT: ret
%a = call <16 x i64> @llvm.llrint.v16i64.v16f32(<16 x float> %x)
ret <16 x i64> %a
@@ -414,124 +293,46 @@ declare <16 x i64> @llvm.llrint.v16i64.v16f32(<16 x float>)
define <32 x i64> @llrint_v32i64_v32f32(<32 x float> %x) nounwind {
; CHECK-LABEL: llrint_v32i64_v32f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-NEXT: sub x9, sp, #272
-; CHECK-NEXT: mov x29, sp
-; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0
-; CHECK-NEXT: frintx v0.4s, v0.4s
-; CHECK-NEXT: frintx v1.4s, v1.4s
+; CHECK-NEXT: frintx v7.4s, v7.4s
+; CHECK-NEXT: frintx v6.4s, v6.4s
+; CHECK-NEXT: mov x9, #28 // =0x1c
+; CHECK-NEXT: frintx v5.4s, v5.4s
+; CHECK-NEXT: frintx v4.4s, v4.4s
+; CHECK-NEXT: frintx v3.4s, v3.4s
; CHECK-NEXT: frintx v2.4s, v2.4s
; CHECK-NEXT: ptrue p0.d, vl4
-; CHECK-NEXT: mov s16, v0.s[3]
-; CHECK-NEXT: mov s17, v0.s[2]
-; CHECK-NEXT: mov s18, v0.s[1]
-; CHECK-NEXT: fcvtzs x12, s0
-; CHECK-NEXT: frintx v0.4s, v3.4s
-; CHECK-NEXT: mov s3, v2.s[3]
-; CHECK-NEXT: fcvtzs x9, s16
-; CHECK-NEXT: mov s16, v1.s[3]
-; CHECK-NEXT: fcvtzs x10, s17
-; CHECK-NEXT: mov s17, v1.s[2]
-; CHECK-NEXT: fcvtzs x11, s18
-; CHECK-NEXT: mov s18, v1.s[1]
-; CHECK-NEXT: fcvtzs x13, s16
-; CHECK-NEXT: stp x10, x9, [sp, #16]
-; CHECK-NEXT: mov s16, v2.s[2]
-; CHECK-NEXT: fcvtzs x9, s17
-; CHECK-NEXT: fcvtzs x10, s18
-; CHECK-NEXT: mov s17, v2.s[1]
-; CHECK-NEXT: stp x12, x11, [sp]
-; CHECK-NEXT: fcvtzs x11, s1
-; CHECK-NEXT: frintx v1.4s, v4.4s
-; CHECK-NEXT: fcvtzs x12, s3
-; CHECK-NEXT: mov s3, v0.s[3]
-; CHECK-NEXT: mov s4, v0.s[2]
-; CHECK-NEXT: stp x9, x13, [sp, #48]
-; CHECK-NEXT: fcvtzs x13, s16
-; CHECK-NEXT: fcvtzs x9, s17
-; CHECK-NEXT: mov s16, v0.s[1]
-; CHECK-NEXT: stp x11, x10, [sp, #32]
-; CHECK-NEXT: fcvtzs x10, s2
-; CHECK-NEXT: frintx v2.4s, v5.4s
-; CHECK-NEXT: fcvtzs x11, s3
-; CHECK-NEXT: mov s3, v1.s[3]
-; CHECK-NEXT: mov s5, v1.s[1]
-; CHECK-NEXT: stp x13, x12, [sp, #80]
-; CHECK-NEXT: fcvtzs x12, s4
-; CHECK-NEXT: mov s4, v1.s[2]
-; CHECK-NEXT: fcvtzs x13, s16
-; CHECK-NEXT: stp x10, x9, [sp, #64]
-; CHECK-NEXT: fcvtzs x9, s0
-; CHECK-NEXT: mov s0, v2.s[3]
-; CHECK-NEXT: fcvtzs x10, s3
-; CHECK-NEXT: frintx v3.4s, v6.4s
-; CHECK-NEXT: stp x12, x11, [sp, #112]
-; CHECK-NEXT: fcvtzs x11, s4
-; CHECK-NEXT: mov s4, v2.s[2]
-; CHECK-NEXT: fcvtzs x12, s5
-; CHECK-NEXT: mov s5, v2.s[1]
-; CHECK-NEXT: stp x9, x13, [sp, #96]
-; CHECK-NEXT: fcvtzs x9, s1
-; CHECK-NEXT: fcvtzs x13, s0
-; CHECK-NEXT: mov s0, v3.s[3]
-; CHECK-NEXT: frintx v1.4s, v7.4s
-; CHECK-NEXT: stp x11, x10, [sp, #144]
-; CHECK-NEXT: fcvtzs x10, s4
-; CHECK-NEXT: mov s4, v3.s[2]
-; CHECK-NEXT: fcvtzs x11, s5
-; CHECK-NEXT: mov s5, v3.s[1]
-; CHECK-NEXT: stp x9, x12, [sp, #128]
-; CHECK-NEXT: fcvtzs x9, s2
-; CHECK-NEXT: fcvtzs x12, s0
-; CHECK-NEXT: mov s0, v1.s[3]
-; CHECK-NEXT: mov s2, v1.s[2]
-; CHECK-NEXT: stp x10, x13, [sp, #176]
-; CHECK-NEXT: fcvtzs x10, s4
-; CHECK-NEXT: mov s4, v1.s[1]
-; CHECK-NEXT: fcvtzs x13, s5
-; CHECK-NEXT: stp x9, x11, [sp, #160]
-; CHECK-NEXT: fcvtzs x9, s3
-; CHECK-NEXT: fcvtzs x11, s0
-; CHECK-NEXT: stp x10, x12, [sp, #208]
-; CHECK-NEXT: fcvtzs x10, s2
-; CHECK-NEXT: fcvtzs x12, s4
-; CHECK-NEXT: stp x9, x13, [sp, #192]
-; CHECK-NEXT: fcvtzs x9, s1
-; CHECK-NEXT: stp x10, x11, [sp, #240]
-; CHECK-NEXT: add x10, sp, #64
-; CHECK-NEXT: stp x9, x12, [sp, #224]
-; CHECK-NEXT: mov x9, sp
-; CHECK-NEXT: ld1d { z0.d }, p0/z, [x9]
-; CHECK-NEXT: add x9, sp, #32
-; CHECK-NEXT: ld1d { z2.d }, p0/z, [x10]
-; CHECK-NEXT: ld1d { z1.d }, p0/z, [x9]
-; CHECK-NEXT: add x9, sp, #224
-; CHECK-NEXT: add x10, sp, #96
-; CHECK-NEXT: ld1d { z3.d }, p0/z, [x9]
-; CHECK-NEXT: add x9, sp, #192
-; CHECK-NEXT: ld1d { z4.d }, p0/z, [x10]
-; CHECK-NEXT: add x10, sp, #160
-; CHECK-NEXT: ld1d { z5.d }, p0/z, [x9]
-; CHECK-NEXT: add x9, sp, #128
-; CHECK-NEXT: ld1d { z6.d }, p0/z, [x10]
-; CHECK-NEXT: mov x10, #28 // =0x1c
-; CHECK-NEXT: ld1d { z7.d }, p0/z, [x9]
+; CHECK-NEXT: frintx v1.4s, v1.4s
+; CHECK-NEXT: frintx v0.4s, v0.4s
+; CHECK-NEXT: uunpklo z7.d, z7.s
+; CHECK-NEXT: uunpklo z6.d, z6.s
+; CHECK-NEXT: uunpklo z5.d, z5.s
+; CHECK-NEXT: uunpklo z4.d, z4.s
+; CHECK-NEXT: uunpklo z3.d, z3.s
+; CHECK-NEXT: uunpklo z2.d, z2.s
+; CHECK-NEXT: uunpklo z1.d, z1.s
+; CHECK-NEXT: uunpklo z0.d, z0.s
+; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.s
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.s
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.s
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.s
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.s
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.s
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.s
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-NEXT: st1d { z7.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #24 // =0x18
-; CHECK-NEXT: st1d { z3.d }, p0, [x8, x10, lsl #3]
-; CHECK-NEXT: st1d { z5.d }, p0, [x8, x9, lsl #3]
-; CHECK-NEXT: mov x9, #20 // =0x14
; CHECK-NEXT: st1d { z6.d }, p0, [x8, x9, lsl #3]
+; CHECK-NEXT: mov x9, #20 // =0x14
+; CHECK-NEXT: st1d { z5.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #16 // =0x10
-; CHECK-NEXT: st1d { z7.d }, p0, [x8, x9, lsl #3]
-; CHECK-NEXT: mov x9, #12 // =0xc
; CHECK-NEXT: st1d { z4.d }, p0, [x8, x9, lsl #3]
+; CHECK-NEXT: mov x9, #12 // =0xc
+; CHECK-NEXT: st1d { z3.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #8 // =0x8
; CHECK-NEXT: st1d { z2.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #4 // =0x4
; CHECK-NEXT: st1d { z1.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: st1d { z0.d }, p0, [x8]
-; CHECK-NEXT: mov sp, x29
-; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret
%a = call <32 x i64> @llvm.llrint.v32i64.v32f32(<32 x float> %x)
ret <32 x i64> %a
@@ -569,15 +370,11 @@ define <4 x i64> @llrint_v4i64_v4f64(<4 x double> %x) nounwind {
; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d
; CHECK-NEXT: ptrue p0.d, vl4
; CHECK-NEXT: frintx z0.d, p0/m, z0.d
-; CHECK-NEXT: mov z1.d, z0.d[3]
-; CHECK-NEXT: mov z2.d, z0.d[2]
-; CHECK-NEXT: mov z3.d, z0.d[1]
-; CHECK-NEXT: fcvtzs d0, d0
-; CHECK-NEXT: fcvtzs x8, d1
-; CHECK-NEXT: fcvtzs d1, d2
-; CHECK-NEXT: fcvtzs x9, d3
-; CHECK-NEXT: mov v0.d[1], x9
-; CHECK-NEXT: mov v1.d[1], x8
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: movprfx z1, z0
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT: ret
%a = call <4 x i64> @llvm.llrint.v4i64.v4f64(<4 x double> %x)
ret <4 x i64> %a
@@ -597,24 +394,16 @@ define <8 x i64> @llrint_v8i64_v8f64(<8 x double> %x) nounwind {
; CHECK-NEXT: ptrue p0.d, vl4
; CHECK-NEXT: frintx z2.d, p0/m, z2.d
; CHECK-NEXT: frintx z0.d, p0/m, z0.d
-; CHECK-NEXT: mov z1.d, z2.d[3]
-; CHECK-NEXT: mov z3.d, z0.d[3]
-; CHECK-NEXT: mov z4.d, z0.d[1]
-; CHECK-NEXT: mov z5.d, z2.d[2]
-; CHECK-NEXT: mov z6.d, z0.d[2]
-; CHECK-NEXT: mov z7.d, z2.d[1]
-; CHECK-NEXT: fcvtzs d2, d2
-; CHECK-NEXT: fcvtzs d0, d0
-; CHECK-NEXT: fcvtzs x8, d1
-; CHECK-NEXT: fcvtzs x9, d3
-; CHECK-NEXT: fcvtzs x10, d4
-; CHECK-NEXT: fcvtzs d3, d5
-; CHECK-NEXT: fcvtzs d1, d6
-; CHECK-NEXT: fcvtzs x11, d7
-; CHECK-NEXT: mov v0.d[1], x10
-; CHECK-NEXT: mov v2.d[1], x11
-; CHECK-NEXT: mov v1.d[1], x9
-; CHECK-NEXT: mov v3.d[1], x8
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: movprfx z1, z0
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-NEXT: movprfx z3, z2
+; CHECK-NEXT: ext z3.b, z3.b, z2.b, #16
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT: // kill: def $q2 killed $q2 killed $z2
+; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
+; CHECK-NEXT: // kill: def $q3 killed $q3 killed $z3
; CHECK-NEXT: ret
%a = call <8 x i64> @llvm.llrint.v8i64.v8f64(<8 x double> %x)
ret <8 x i64> %a
@@ -628,56 +417,40 @@ define <16 x i64> @llrint_v16f64(<16 x double> %x) nounwind {
; CHECK-NEXT: // kill: def $q6 killed $q6 def $z6
; CHECK-NEXT: // kill: def $q4 killed $q4 def $z4
; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
+; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: // kill: def $q7 killed $q7 def $z7
; CHECK-NEXT: // kill: def $q5 killed $q5 def $z5
; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3
-; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT: splice z6.d, p0, z6.d, z7.d
+; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d
; CHECK-NEXT: splice z2.d, p0, z2.d, z3.d
; CHECK-NEXT: splice z4.d, p0, z4.d, z5.d
-; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: splice z6.d, p0, z6.d, z7.d
; CHECK-NEXT: ptrue p0.d, vl4
-; CHECK-NEXT: frintx z6.d, p0/m, z6.d
-; CHECK-NEXT: frintx z4.d, p0/m, z4.d
; CHECK-NEXT: frintx z2.d, p0/m, z2.d
; CHECK-NEXT: frintx z0.d, p0/m, z0.d
-; CHECK-NEXT: mov z1.d, z6.d[3]
-; CHECK-NEXT: mov z3.d, z4.d[3]
-; CHECK-NEXT: mov z5.d, z2.d[3]
-; CHECK-NEXT: mov z16.d, z4.d[1]
-; CHECK-NEXT: mov z7.d, z0.d[3]
-; CHECK-NEXT: mov z17.d, z0.d[2]
-; CHECK-NEXT: mov z18.d, z4.d[2]
-; CHECK-NEXT: mov z19.d, z6.d[1]
-; CHECK-NEXT: fcvtzs d4, d4
-; CHECK-NEXT: fcvtzs x8, d1
-; CHECK-NEXT: mov z1.d, z2.d[1]
-; CHECK-NEXT: fcvtzs x9, d3
-; CHECK-NEXT: mov z3.d, z0.d[1]
-; CHECK-NEXT: fcvtzs x10, d5
-; CHECK-NEXT: mov z5.d, z6.d[2]
-; CHECK-NEXT: fcvtzs x12, d16
-; CHECK-NEXT: mov z16.d, z2.d[2]
-; CHECK-NEXT: fcvtzs x11, d7
-; CHECK-NEXT: fcvtzs x13, d1
-; CHECK-NEXT: fcvtzs d1, d17
-; CHECK-NEXT: fcvtzs d0, d0
-; CHECK-NEXT: fcvtzs x14, d3
-; CHECK-NEXT: fcvtzs d7, d5
-; CHECK-NEXT: fcvtzs d2, d2
-; CHECK-NEXT: fcvtzs d3, d16
-; CHECK-NEXT: fcvtzs d5, d18
-; CHECK-NEXT: fcvtzs x15, d19
-; CHECK-NEXT: fcvtzs d6, d6
-; CHECK-NEXT: mov v4.d[1], x12
-; CHECK-NEXT: mov v1.d[1], x11
-; CHECK-NEXT: mov v0.d[1], x14
-; CHECK-NEXT: mov v2.d[1], x13
-; CHECK-NEXT: mov v7.d[1], x8
-; CHECK-NEXT: mov v3.d[1], x10
-; CHECK-NEXT: mov v5.d[1], x9
-; CHECK-NEXT: mov v6.d[1], x15
+; CHECK-NEXT: frintx z4.d, p0/m, z4.d
+; CHECK-NEXT: frintx z6.d, p0/m, z6.d
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.d
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.d
+; CHECK-NEXT: movprfx z1, z0
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-NEXT: movprfx z3, z2
+; CHECK-NEXT: ext z3.b, z3.b, z2.b, #16
+; CHECK-NEXT: movprfx z5, z4
+; CHECK-NEXT: ext z5.b, z5.b, z4.b, #16
+; CHECK-NEXT: movprfx z7, z6
+; CHECK-NEXT: ext z7.b, z7.b, z6.b, #16
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT: // kill: def $q2 killed $q2 killed $z2
+; CHECK-NEXT: // kill: def $q4 killed $q4 killed $z4
+; CHECK-NEXT: // kill: def $q6 killed $q6 killed $z6
+; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
+; CHECK-NEXT: // kill: def $q3 killed $q3 killed $z3
+; CHECK-NEXT: // kill: def $q5 killed $q5 killed $z5
+; CHECK-NEXT: // kill: def $q7 killed $q7 killed $z7
; CHECK-NEXT: ret
%a = call <16 x i64> @llvm.llrint.v16i64.v16f64(<16 x double> %x)
ret <16 x i64> %a
@@ -687,148 +460,59 @@ declare <16 x i64> @llvm.llrint.v16i64.v16f64(<16 x double>)
define <32 x i64> @llrint_v32f64(<32 x double> %x) nounwind {
; CHECK-LABEL: llrint_v32f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-NEXT: sub x9, sp, #272
-; CHECK-NEXT: mov x29, sp
-; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0
-; CHECK-NEXT: ptrue p1.d, vl2
-; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
-; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3
-; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
-; CHECK-NEXT: // kill: def $q7 killed $q7 def $z7
+; CHECK-NEXT: ldp q17, q16, [sp, #96]
+; CHECK-NEXT: ptrue p0.d, vl2
+; CHECK-NEXT: ldp q19, q18, [sp, #64]
+; CHECK-NEXT: ptrue p1.d, vl4
; CHECK-NEXT: // kill: def $q6 killed $q6 def $z6
+; CHECK-NEXT: // kill: def $q7 killed $q7 def $z7
; CHECK-NEXT: // kill: def $q4 killed $q4 def $z4
; CHECK-NEXT: // kill: def $q5 killed $q5 def $z5
-; CHECK-NEXT: ptrue p0.d, vl4
-; CHECK-NEXT: splice z0.d, p1, z0.d, z1.d
-; CHECK-NEXT: splice z2.d, p1, z2.d, z3.d
-; CHECK-NEXT: splice z4.d, p1, z4.d, z5.d
-; CHECK-NEXT: splice z6.d, p1, z6.d, z7.d
-; CHECK-NEXT: ldp q5, q19, [x29, #16]
-; CHECK-NEXT: movprfx z3, z0
-; CHECK-NEXT: frintx z3.d, p0/m, z0.d
-; CHECK-NEXT: movprfx z16, z2
-; CHECK-NEXT: frintx z16.d, p0/m, z2.d
-; CHECK-NEXT: frintx z4.d, p0/m, z4.d
-; CHECK-NEXT: splice z5.d, p1, z5.d, z19.d
-; CHECK-NEXT: frintx z6.d, p0/m, z6.d
-; CHECK-NEXT: ldp q2, q17, [x29, #48]
-; CHECK-NEXT: ldp q0, q1, [x29, #112]
-; CHECK-NEXT: mov z18.d, z3.d[3]
-; CHECK-NEXT: mov z7.d, z3.d[2]
-; CHECK-NEXT: fcvtzs x9, d3
-; CHECK-NEXT: mov z3.d, z3.d[1]
-; CHECK-NEXT: mov z20.d, z16.d[3]
-; CHECK-NEXT: fcvtzs x12, d16
-; CHECK-NEXT: splice z2.d, p1, z2.d, z17.d
-; CHECK-NEXT: frintx z5.d, p0/m, z5.d
-; CHECK-NEXT: splice z0.d, p1, z0.d, z1.d
-; CHECK-NEXT: fcvtzs x10, d18
-; CHECK-NEXT: fcvtzs x11, d7
-; CHECK-NEXT: mov z18.d, z16.d[2]
-; CHECK-NEXT: mov z7.d, z16.d[1]
-; CHECK-NEXT: fcvtzs x13, d3
-; CHECK-NEXT: str x9, [sp, #128]
-; CHECK-NEXT: fcvtzs x9, d20
-; CHECK-NEXT: mov z16.d, z4.d[3]
-; CHECK-NEXT: ldp q3, q19, [x29, #80]
-; CHECK-NEXT: frintx z2.d, p0/m, z2.d
-; CHECK-NEXT: stp x11, x10, [sp, #144]
-; CHECK-NEXT: fcvtzs x10, d18
-; CHECK-NEXT: fcvtzs x11, d7
-; CHECK-NEXT: mov z18.d, z4.d[2]
-; CHECK-NEXT: mov z7.d, z4.d[1]
-; CHECK-NEXT: str x13, [sp, #136]
-; CHECK-NEXT: fcvtzs x13, d16
-; CHECK-NEXT: mov z16.d, z6.d[3]
-; CHECK-NEXT: splice z3.d, p1, z3.d, z19.d
-; CHECK-NEXT: mov z1.d, z5.d[1]
-; CHECK-NEXT: frintx z0.d, p0/m, z0.d
-; CHECK-NEXT: stp x10, x9, [sp, #176]
-; CHECK-NEXT: fcvtzs x9, d18
-; CHECK-NEXT: fcvtzs x10, d4
-; CHECK-NEXT: stp x12, x11, [sp, #160]
-; CHECK-NEXT: fcvtzs x11, d7
-; CHECK-NEXT: mov z4.d, z6.d[2]
-; CHECK-NEXT: mov z7.d, z6.d[1]
-; CHECK-NEXT: fcvtzs x12, d6
-; CHECK-NEXT: mov z6.d, z5.d[2]
-; CHECK-NEXT: frintx z3.d, p0/m, z3.d
-; CHECK-NEXT: stp x9, x13, [sp, #208]
-; CHECK-NEXT: fcvtzs x9, d16
-; CHECK-NEXT: fcvtzs x13, d4
-; CHECK-NEXT: stp x10, x11, [sp, #192]
-; CHECK-NEXT: fcvtzs x10, d7
-; CHECK-NEXT: mov z4.d, z5.d[3]
-; CHECK-NEXT: fcvtzs x11, d4
-; CHECK-NEXT: stp x13, x9, [sp, #240]
-; CHECK-NEXT: fcvtzs x9, d6
-; CHECK-NEXT: stp x12, x10, [sp, #224]
-; CHECK-NEXT: fcvtzs x10, d5
-; CHECK-NEXT: fcvtzs x12, d1
-; CHECK-NEXT: mov z4.d, z2.d[3]
-; CHECK-NEXT: mov z5.d, z2.d[2]
-; CHECK-NEXT: mov z1.d, z2.d[1]
-; CHECK-NEXT: fcvtzs x13, d2
-; CHECK-NEXT: mov z2.d, z3.d[2]
-; CHECK-NEXT: stp x9, x11, [sp, #16]
-; CHECK-NEXT: fcvtzs x9, d4
-; CHECK-NEXT: fcvtzs x11, d5
-; CHECK-NEXT: stp x10, x12, [sp]
-; CHECK-NEXT: fcvtzs x10, d1
-; CHECK-NEXT: mov z4.d, z3.d[3]
-; CHECK-NEXT: mov z1.d, z3.d[1]
-; CHECK-NEXT: fcvtzs x12, d4
-; CHECK-NEXT: stp x11, x9, [sp, #48]
-; CHECK-NEXT: fcvtzs x9, d2
-; CHECK-NEXT: fcvtzs x11, d3
-; CHECK-NEXT: stp x13, x10, [sp, #32]
-; CHECK-NEXT: fcvtzs x10, d1
-; CHECK-NEXT: mov z2.d, z0.d[3]
-; CHECK-NEXT: mov z3.d, z0.d[2]
-; CHECK-NEXT: mov z1.d, z0.d[1]
-; CHECK-NEXT: stp x9, x12, [sp, #80]
-; CHECK-NEXT: fcvtzs x12, d0
-; CHECK-NEXT: fcvtzs x13, d2
-; CHECK-NEXT: fcvtzs x9, d3
-; CHECK-NEXT: stp x11, x10, [sp, #64]
-; CHECK-NEXT: fcvtzs x10, d1
-; CHECK-NEXT: stp x9, x13, [sp, #112]
-; CHECK-NEXT: add x9, sp, #128
-; CHECK-NEXT: stp x12, x10, [sp, #96]
-; CHECK-NEXT: add x10, sp, #192
-; CHECK-NEXT: ld1d { z0.d }, p0/z, [x9]
-; CHECK-NEXT: add x9, sp, #160
-; CHECK-NEXT: ld1d { z2.d }, p0/z, [x10]
-; CHECK-NEXT: ld1d { z1.d }, p0/z, [x9]
-; CHECK-NEXT: add x9, sp, #96
-; CHECK-NEXT: add x10, sp, #224
-; CHECK-NEXT: ld1d { z3.d }, p0/z, [x9]
-; CHECK-NEXT: add x9, sp, #64
-; CHECK-NEXT: ld1d { z4.d }, p0/z, [x10]
-; CHECK-NEXT: add x10, sp, #32
-; CHECK-NEXT: ld1d { z5.d }, p0/z, [x9]
-; CHECK-NEXT: mov x9, sp
-; CHECK-NEXT: ld1d { z6.d }, p0/z, [x10]
-; CHECK-NEXT: mov x10, #28 // =0x1c
-; CHECK-NEXT: ld1d { z7.d }, p0/z, [x9]
+; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
+; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3
+; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-NEXT: mov x9, #28 // =0x1c
+; CHECK-NEXT: splice z17.d, p0, z17.d, z16.d
+; CHECK-NEXT: ldp q20, q16, [sp, #32]
+; CHECK-NEXT: splice z19.d, p0, z19.d, z18.d
+; CHECK-NEXT: ldp q21, q18, [sp]
+; CHECK-NEXT: splice z6.d, p0, z6.d, z7.d
+; CHECK-NEXT: splice z4.d, p0, z4.d, z5.d
+; CHECK-NEXT: splice z2.d, p0, z2.d, z3.d
+; CHECK-NEXT: splice z20.d, p0, z20.d, z16.d
+; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: splice z21.d, p0, z21.d, z18.d
+; CHECK-NEXT: frintx z17.d, p1/m, z17.d
+; CHECK-NEXT: frintx z19.d, p1/m, z19.d
+; CHECK-NEXT: frintx z6.d, p1/m, z6.d
+; CHECK-NEXT: frintx z4.d, p1/m, z4.d
+; CHECK-NEXT: frintx z2.d, p1/m, z2.d
+; CHECK-NEXT: frintx z20.d, p1/m, z20.d
+; CHECK-NEXT: frintx z0.d, p1/m, z0.d
+; CHECK-NEXT: frintx z21.d, p1/m, z21.d
+; CHECK-NEXT: fcvtzs z17.d, p1/m, z17.d
+; CHECK-NEXT: fcvtzs z19.d, p1/m, z19.d
+; CHECK-NEXT: fcvtzs z6.d, p1/m, z6.d
+; CHECK-NEXT: fcvtzs z4.d, p1/m, z4.d
+; CHECK-NEXT: fcvtzs z2.d, p1/m, z2.d
+; CHECK-NEXT: fcvtzs z20.d, p1/m, z20.d
+; CHECK-NEXT: fcvtzs z0.d, p1/m, z0.d
+; CHECK-NEXT: fcvtzs z21.d, p1/m, z21.d
+; CHECK-NEXT: st1d { z17.d }, p1, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #24 // =0x18
-; CHECK-NEXT: st1d { z3.d }, p0, [x8, x10, lsl #3]
-; CHECK-NEXT: st1d { z5.d }, p0, [x8, x9, lsl #3]
+; CHECK-NEXT: st1d { z19.d }, p1, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #20 // =0x14
-; CHECK-NEXT: st1d { z6.d }, p0, [x8, x9, lsl #3]
+; CHECK-NEXT: st1d { z20.d }, p1, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #16 // =0x10
-; CHECK-NEXT: st1d { z7.d }, p0, [x8, x9, lsl #3]
+; CHECK-NEXT: st1d { z21.d }, p1, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #12 // =0xc
-; CHECK-NEXT: st1d { z4.d }, p0, [x8, x9, lsl #3]
+; CHECK-NEXT: st1d { z6.d }, p1, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #8 // =0x8
-; CHECK-NEXT: st1d { z2.d }, p0, [x8, x9, lsl #3]
+; CHECK-NEXT: st1d { z4.d }, p1, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #4 // =0x4
-; CHECK-NEXT: st1d { z1.d }, p0, [x8, x9, lsl #3]
-; CHECK-NEXT: st1d { z0.d }, p0, [x8]
-; CHECK-NEXT: mov sp, x29
-; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
+; CHECK-NEXT: st1d { z2.d }, p1, [x8, x9, lsl #3]
+; CHECK-NEXT: st1d { z0.d }, p1, [x8]
; CHECK-NEXT: ret
%a = call <32 x i64> @llvm.llrint.v32i64.v16f64(<32 x double> %x)
ret <32 x i64> %a
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll b/llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll
index 9b6aab6d33db7..3fa0c094a6ca8 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll
@@ -64,17 +64,14 @@ define <4 x iXLen> @lrint_v4f16(<4 x half> %x) nounwind {
; CHECK-i64-LABEL: lrint_v4f16:
; CHECK-i64: // %bb.0:
; CHECK-i64-NEXT: frintx v0.4h, v0.4h
-; CHECK-i64-NEXT: mov h1, v0.h[2]
-; CHECK-i64-NEXT: mov h2, v0.h[3]
-; CHECK-i64-NEXT: mov h3, v0.h[1]
-; CHECK-i64-NEXT: fcvtzs x9, h0
-; CHECK-i64-NEXT: fcvtzs x8, h1
-; CHECK-i64-NEXT: fcvtzs x10, h2
-; CHECK-i64-NEXT: fcvtzs x11, h3
-; CHECK-i64-NEXT: fmov d0, x9
-; CHECK-i64-NEXT: fmov d1, x8
-; CHECK-i64-NEXT: mov v0.d[1], x11
-; CHECK-i64-NEXT: mov v1.d[1], x10
+; CHECK-i64-NEXT: ptrue p0.d, vl4
+; CHECK-i64-NEXT: uunpklo z0.s, z0.h
+; CHECK-i64-NEXT: uunpklo z0.d, z0.s
+; CHECK-i64-NEXT: fcvtzs z0.d, p0/m, z0.h
+; CHECK-i64-NEXT: movprfx z1, z0
+; CHECK-i64-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-i64-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-i64-NEXT: // kill: def $q1 killed $q1 killed $z1
; CHECK-i64-NEXT: ret
%a = call <4 x iXLen> @llvm.lrint.v4iXLen.v4f16(<4 x half> %x)
ret <4 x iXLen> %a
@@ -84,59 +81,37 @@ declare <4 x iXLen> @llvm.lrint.v4iXLen.v4f16(<4 x half>)
define <8 x iXLen> @lrint_v8f16(<8 x half> %x) nounwind {
; CHECK-i32-LABEL: lrint_v8f16:
; CHECK-i32: // %bb.0:
-; CHECK-i32-NEXT: frintx v2.8h, v0.8h
-; CHECK-i32-NEXT: mov h0, v2.h[4]
-; CHECK-i32-NEXT: mov h1, v2.h[5]
-; CHECK-i32-NEXT: mov h3, v2.h[1]
-; CHECK-i32-NEXT: fcvtzs w9, h2
-; CHECK-i32-NEXT: mov h4, v2.h[6]
-; CHECK-i32-NEXT: fcvtzs w8, h0
-; CHECK-i32-NEXT: mov h0, v2.h[2]
-; CHECK-i32-NEXT: fcvtzs w10, h1
-; CHECK-i32-NEXT: fcvtzs w11, h3
-; CHECK-i32-NEXT: mov h3, v2.h[7]
-; CHECK-i32-NEXT: fcvtzs w12, h4
-; CHECK-i32-NEXT: mov h2, v2.h[3]
-; CHECK-i32-NEXT: fmov s1, w8
-; CHECK-i32-NEXT: fcvtzs w8, h0
-; CHECK-i32-NEXT: fmov s0, w9
-; CHECK-i32-NEXT: fcvtzs w9, h3
-; CHECK-i32-NEXT: mov v0.s[1], w11
-; CHECK-i32-NEXT: mov v1.s[1], w10
-; CHECK-i32-NEXT: fcvtzs w10, h2
-; CHECK-i32-NEXT: mov v0.s[2], w8
-; CHECK-i32-NEXT: mov v1.s[2], w12
-; CHECK-i32-NEXT: mov v0.s[3], w10
-; CHECK-i32-NEXT: mov v1.s[3], w9
+; CHECK-i32-NEXT: frintx v0.8h, v0.8h
+; CHECK-i32-NEXT: ptrue p0.s, vl8
+; CHECK-i32-NEXT: uunpklo z0.s, z0.h
+; CHECK-i32-NEXT: fcvtzs z0.s, p0/m, z0.h
+; CHECK-i32-NEXT: movprfx z1, z0
+; CHECK-i32-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-i32-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-i32-NEXT: // kill: def $q1 killed $q1 killed $z1
; CHECK-i32-NEXT: ret
;
; CHECK-i64-LABEL: lrint_v8f16:
; CHECK-i64: // %bb.0:
; CHECK-i64-NEXT: mov d1, v0.d[1]
; CHECK-i64-NEXT: frintx v0.4h, v0.4h
+; CHECK-i64-NEXT: ptrue p0.d, vl4
; CHECK-i64-NEXT: frintx v1.4h, v1.4h
-; CHECK-i64-NEXT: mov h3, v0.h[2]
-; CHECK-i64-NEXT: mov h4, v0.h[1]
-; CHECK-i64-NEXT: mov h5, v0.h[3]
-; CHECK-i64-NEXT: fcvtzs x8, h0
-; CHECK-i64-NEXT: mov h2, v1.h[2]
-; CHECK-i64-NEXT: mov h6, v1.h[3]
-; CHECK-i64-NEXT: mov h7, v1.h[1]
-; CHECK-i64-NEXT: fcvtzs x10, h1
-; CHECK-i64-NEXT: fcvtzs x11, h3
-; CHECK-i64-NEXT: fcvtzs x12, h4
-; CHECK-i64-NEXT: fcvtzs x13, h5
-; CHECK-i64-NEXT: fmov d0, x8
-; CHECK-i64-NEXT: fcvtzs x9, h2
-; CHECK-i64-NEXT: fcvtzs x14, h6
-; CHECK-i64-NEXT: fcvtzs x15, h7
-; CHECK-i64-NEXT: fmov d2, x10
-; CHECK-i64-NEXT: fmov d1, x11
-; CHECK-i64-NEXT: mov v0.d[1], x12
-; CHECK-i64-NEXT: fmov d3, x9
-; CHECK-i64-NEXT: mov v1.d[1], x13
-; CHECK-i64-NEXT: mov v2.d[1], x15
-; CHECK-i64-NEXT: mov v3.d[1], x14
+; CHECK-i64-NEXT: uunpklo z0.s, z0.h
+; CHECK-i64-NEXT: uunpklo z1.s, z1.h
+; CHECK-i64-NEXT: uunpklo z0.d, z0.s
+; CHECK-i64-NEXT: uunpklo z1.d, z1.s
+; CHECK-i64-NEXT: fcvtzs z0.d, p0/m, z0.h
+; CHECK-i64-NEXT: movprfx z2, z1
+; CHECK-i64-NEXT: fcvtzs z2.d, p0/m, z1.h
+; CHECK-i64-NEXT: movprfx z1, z0
+; CHECK-i64-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-i64-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-i64-NEXT: // kill: def $q1 killed $q1 killed $z1
+; CHECK-i64-NEXT: movprfx z3, z2
+; CHECK-i64-NEXT: ext z3.b, z3.b, z2.b, #16
+; CHECK-i64-NEXT: // kill: def $q2 killed $q2 killed $z2
+; CHECK-i64-NEXT: // kill: def $q3 killed $q3 killed $z3
; CHECK-i64-NEXT: ret
%a = call <8 x iXLen> @llvm.lrint.v8iXLen.v8f16(<8 x half> %x)
ret <8 x iXLen> %a
@@ -147,107 +122,62 @@ define <16 x iXLen> @lrint_v16f16(<16 x half> %x) nounwind {
; CHECK-i32-LABEL: lrint_v16f16:
; CHECK-i32: // %bb.0:
; CHECK-i32-NEXT: frintx v1.8h, v1.8h
-; CHECK-i32-NEXT: frintx v4.8h, v0.8h
-; CHECK-i32-NEXT: mov h0, v1.h[6]
-; CHECK-i32-NEXT: mov h2, v1.h[5]
-; CHECK-i32-NEXT: mov h3, v1.h[4]
-; CHECK-i32-NEXT: mov h5, v4.h[4]
-; CHECK-i32-NEXT: mov h7, v4.h[1]
-; CHECK-i32-NEXT: fcvtzs w10, h1
-; CHECK-i32-NEXT: fcvtzs w13, h4
-; CHECK-i32-NEXT: mov h6, v1.h[2]
-; CHECK-i32-NEXT: mov h16, v1.h[3]
-; CHECK-i32-NEXT: mov h17, v4.h[7]
-; CHECK-i32-NEXT: fcvtzs w8, h0
-; CHECK-i32-NEXT: mov h0, v1.h[1]
-; CHECK-i32-NEXT: fcvtzs w9, h2
-; CHECK-i32-NEXT: mov h2, v4.h[5]
-; CHECK-i32-NEXT: fcvtzs w11, h3
-; CHECK-i32-NEXT: mov h3, v4.h[6]
-; CHECK-i32-NEXT: fcvtzs w12, h5
-; CHECK-i32-NEXT: mov h5, v4.h[2]
-; CHECK-i32-NEXT: fcvtzs w14, h7
-; CHECK-i32-NEXT: mov h7, v1.h[7]
-; CHECK-i32-NEXT: fcvtzs w17, h6
-; CHECK-i32-NEXT: mov h4, v4.h[3]
-; CHECK-i32-NEXT: fcvtzs w15, h0
-; CHECK-i32-NEXT: fmov s0, w13
-; CHECK-i32-NEXT: fcvtzs w16, h2
-; CHECK-i32-NEXT: fmov s2, w10
-; CHECK-i32-NEXT: fcvtzs w10, h3
-; CHECK-i32-NEXT: fmov s3, w11
-; CHECK-i32-NEXT: fmov s1, w12
-; CHECK-i32-NEXT: fcvtzs w18, h5
-; CHECK-i32-NEXT: mov v0.s[1], w14
-; CHECK-i32-NEXT: fcvtzs w11, h16
-; CHECK-i32-NEXT: fcvtzs w12, h17
-; CHECK-i32-NEXT: mov v2.s[1], w15
-; CHECK-i32-NEXT: fcvtzs w13, h4
-; CHECK-i32-NEXT: mov v1.s[1], w16
-; CHECK-i32-NEXT: mov v3.s[1], w9
-; CHECK-i32-NEXT: fcvtzs w9, h7
-; CHECK-i32-NEXT: mov v0.s[2], w18
-; CHECK-i32-NEXT: mov v2.s[2], w17
-; CHECK-i32-NEXT: mov v1.s[2], w10
-; CHECK-i32-NEXT: mov v3.s[2], w8
-; CHECK-i32-NEXT: mov v0.s[3], w13
-; CHECK-i32-NEXT: mov v2.s[3], w11
-; CHECK-i32-NEXT: mov v1.s[3], w12
-; CHECK-i32-NEXT: mov v3.s[3], w9
+; CHECK-i32-NEXT: frintx v0.8h, v0.8h
+; CHECK-i32-NEXT: ptrue p0.s, vl8
+; CHECK-i32-NEXT: uunpklo z1.s, z1.h
+; CHECK-i32-NEXT: uunpklo z0.s, z0.h
+; CHECK-i32-NEXT: movprfx z2, z1
+; CHECK-i32-NEXT: fcvtzs z2.s, p0/m, z1.h
+; CHECK-i32-NEXT: fcvtzs z0.s, p0/m, z0.h
+; CHECK-i32-NEXT: movprfx z1, z0
+; CHECK-i32-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-i32-NEXT: movprfx z3, z2
+; CHECK-i32-NEXT: ext z3.b, z3.b, z2.b, #16
+; CHECK-i32-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-i32-NEXT: // kill: def $q2 killed $q2 killed $z2
+; CHECK-i32-NEXT: // kill: def $q1 killed $q1 killed $z1
+; CHECK-i32-NEXT: // kill: def $q3 killed $q3 killed $z3
; CHECK-i32-NEXT: ret
;
; CHECK-i64-LABEL: lrint_v16f16:
; CHECK-i64: // %bb.0:
-; CHECK-i64-NEXT: mov d2, v1.d[1]
-; CHECK-i64-NEXT: frintx v1.4h, v1.4h
-; CHECK-i64-NEXT: mov d3, v0.d[1]
+; CHECK-i64-NEXT: mov d2, v0.d[1]
+; CHECK-i64-NEXT: mov d3, v1.d[1]
; CHECK-i64-NEXT: frintx v0.4h, v0.4h
+; CHECK-i64-NEXT: frintx v1.4h, v1.4h
+; CHECK-i64-NEXT: ptrue p0.d, vl4
; CHECK-i64-NEXT: frintx v2.4h, v2.4h
-; CHECK-i64-NEXT: mov h5, v1.h[1]
; CHECK-i64-NEXT: frintx v3.4h, v3.4h
-; CHECK-i64-NEXT: mov h4, v1.h[2]
-; CHECK-i64-NEXT: mov h6, v0.h[2]
-; CHECK-i64-NEXT: fcvtzs x8, h1
-; CHECK-i64-NEXT: mov h7, v0.h[3]
-; CHECK-i64-NEXT: mov h16, v0.h[1]
-; CHECK-i64-NEXT: fcvtzs x9, h0
-; CHECK-i64-NEXT: mov h1, v1.h[3]
-; CHECK-i64-NEXT: mov h0, v2.h[3]
-; CHECK-i64-NEXT: mov h17, v2.h[2]
-; CHECK-i64-NEXT: fcvtzs x12, h5
-; CHECK-i64-NEXT: mov h5, v3.h[2]
-; CHECK-i64-NEXT: fcvtzs x10, h4
-; CHECK-i64-NEXT: fcvtzs x11, h2
-; CHECK-i64-NEXT: mov h18, v3.h[3]
-; CHECK-i64-NEXT: fcvtzs x14, h3
-; CHECK-i64-NEXT: mov h3, v3.h[1]
-; CHECK-i64-NEXT: mov h2, v2.h[1]
-; CHECK-i64-NEXT: fcvtzs x13, h6
-; CHECK-i64-NEXT: fmov d4, x8
-; CHECK-i64-NEXT: fcvtzs x8, h0
-; CHECK-i64-NEXT: fmov d0, x9
-; CHECK-i64-NEXT: fcvtzs x9, h17
-; CHECK-i64-NEXT: fcvtzs x16, h5
-; CHECK-i64-NEXT: fcvtzs x15, h16
-; CHECK-i64-NEXT: fcvtzs x17, h7
-; CHECK-i64-NEXT: fmov d6, x11
-; CHECK-i64-NEXT: fcvtzs x11, h18
-; CHECK-i64-NEXT: fcvtzs x18, h3
-; CHECK-i64-NEXT: fmov d5, x10
-; CHECK-i64-NEXT: fcvtzs x10, h2
-; CHECK-i64-NEXT: fcvtzs x0, h1
-; CHECK-i64-NEXT: fmov d2, x14
-; CHECK-i64-NEXT: fmov d1, x13
-; CHECK-i64-NEXT: fmov d7, x9
-; CHECK-i64-NEXT: fmov d3, x16
-; CHECK-i64-NEXT: mov v0.d[1], x15
-; CHECK-i64-NEXT: mov v4.d[1], x12
-; CHECK-i64-NEXT: mov v1.d[1], x17
-; CHECK-i64-NEXT: mov v2.d[1], x18
-; CHECK-i64-NEXT: mov v5.d[1], x0
-; CHECK-i64-NEXT: mov v3.d[1], x11
-; CHECK-i64-NEXT: mov v6.d[1], x10
-; CHECK-i64-NEXT: mov v7.d[1], x8
+; CHECK-i64-NEXT: uunpklo z0.s, z0.h
+; CHECK-i64-NEXT: uunpklo z1.s, z1.h
+; CHECK-i64-NEXT: uunpklo z2.s, z2.h
+; CHECK-i64-NEXT: uunpklo z3.s, z3.h
+; CHECK-i64-NEXT: uunpklo z0.d, z0.s
+; CHECK-i64-NEXT: uunpklo z1.d, z1.s
+; CHECK-i64-NEXT: uunpklo z2.d, z2.s
+; CHECK-i64-NEXT: uunpklo z3.d, z3.s
+; CHECK-i64-NEXT: fcvtzs z0.d, p0/m, z0.h
+; CHECK-i64-NEXT: movprfx z4, z1
+; CHECK-i64-NEXT: fcvtzs z4.d, p0/m, z1.h
+; CHECK-i64-NEXT: fcvtzs z2.d, p0/m, z2.h
+; CHECK-i64-NEXT: movprfx z6, z3
+; CHECK-i64-NEXT: fcvtzs z6.d, p0/m, z3.h
+; CHECK-i64-NEXT: movprfx z1, z0
+; CHECK-i64-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-i64-NEXT: movprfx z5, z4
+; CHECK-i64-NEXT: ext z5.b, z5.b, z4.b, #16
+; CHECK-i64-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-i64-NEXT: // kill: def $q4 killed $q4 killed $z4
+; CHECK-i64-NEXT: // kill: def $q1 killed $q1 killed $z1
+; CHECK-i64-NEXT: movprfx z3, z2
+; CHECK-i64-NEXT: ext z3.b, z3.b, z2.b, #16
+; CHECK-i64-NEXT: movprfx z7, z6
+; CHECK-i64-NEXT: ext z7.b, z7.b, z6.b, #16
+; CHECK-i64-NEXT: // kill: def $q2 killed $q2 killed $z2
+; CHECK-i64-NEXT: // kill: def $q5 killed $q5 killed $z5
+; CHECK-i64-NEXT: // kill: def $q6 killed $q6 killed $z6
+; CHECK-i64-NEXT: // kill: def $q3 killed $q3 killed $z3
+; CHECK-i64-NEXT: // kill: def $q7 killed $q7 killed $z7
; CHECK-i64-NEXT: ret
%a = call <16 x iXLen> @llvm.lrint.v16iXLen.v16f16(<16 x half> %x)
ret <16 x iXLen> %a
@@ -257,230 +187,93 @@ declare <16 x iXLen> @llvm.lrint.v16iXLen.v16f16(<16 x half>)
define <32 x iXLen> @lrint_v32f16(<32 x half> %x) nounwind {
; CHECK-i32-LABEL: lrint_v32f16:
; CHECK-i32: // %bb.0:
-; CHECK-i32-NEXT: stp x20, x19, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-i32-NEXT: frintx v1.8h, v1.8h
+; CHECK-i32-NEXT: frintx v0.8h, v0.8h
; CHECK-i32-NEXT: frintx v3.8h, v3.8h
; CHECK-i32-NEXT: frintx v2.8h, v2.8h
-; CHECK-i32-NEXT: frintx v1.8h, v1.8h
-; CHECK-i32-NEXT: mov h16, v3.h[3]
-; CHECK-i32-NEXT: mov h17, v3.h[2]
-; CHECK-i32-NEXT: mov h4, v3.h[7]
-; CHECK-i32-NEXT: mov h5, v3.h[6]
-; CHECK-i32-NEXT: mov h6, v3.h[5]
-; CHECK-i32-NEXT: mov h7, v3.h[4]
-; CHECK-i32-NEXT: mov h18, v3.h[1]
-; CHECK-i32-NEXT: fcvtzs w13, h3
-; CHECK-i32-NEXT: mov h3, v2.h[7]
-; CHECK-i32-NEXT: mov h19, v2.h[4]
-; CHECK-i32-NEXT: fcvtzs w18, h2
-; CHECK-i32-NEXT: mov h20, v2.h[3]
-; CHECK-i32-NEXT: fcvtzs w9, h16
-; CHECK-i32-NEXT: fcvtzs w11, h17
-; CHECK-i32-NEXT: mov h16, v2.h[1]
-; CHECK-i32-NEXT: frintx v17.8h, v0.8h
-; CHECK-i32-NEXT: fcvtzs w8, h4
-; CHECK-i32-NEXT: mov h4, v2.h[6]
-; CHECK-i32-NEXT: mov h0, v1.h[6]
-; CHECK-i32-NEXT: fcvtzs w10, h5
-; CHECK-i32-NEXT: mov h5, v2.h[5]
-; CHECK-i32-NEXT: mov h21, v2.h[2]
-; CHECK-i32-NEXT: mov h2, v1.h[4]
-; CHECK-i32-NEXT: fcvtzs w15, h7
-; CHECK-i32-NEXT: fcvtzs w1, h16
-; CHECK-i32-NEXT: fcvtzs w12, h6
-; CHECK-i32-NEXT: fcvtzs w17, h19
-; CHECK-i32-NEXT: mov h16, v17.h[4]
-; CHECK-i32-NEXT: fcvtzs w14, h18
-; CHECK-i32-NEXT: fmov s6, w13
-; CHECK-i32-NEXT: fcvtzs w13, h3
-; CHECK-i32-NEXT: fcvtzs w16, h4
-; CHECK-i32-NEXT: mov h3, v1.h[5]
-; CHECK-i32-NEXT: mov h18, v17.h[5]
-; CHECK-i32-NEXT: fmov s4, w18
-; CHECK-i32-NEXT: fcvtzs w18, h0
-; CHECK-i32-NEXT: mov h0, v17.h[1]
-; CHECK-i32-NEXT: mov h19, v1.h[1]
-; CHECK-i32-NEXT: fcvtzs w2, h2
-; CHECK-i32-NEXT: mov h2, v1.h[2]
-; CHECK-i32-NEXT: fcvtzs w4, h1
-; CHECK-i32-NEXT: fcvtzs w6, h16
-; CHECK-i32-NEXT: fcvtzs w7, h17
-; CHECK-i32-NEXT: fmov s7, w15
-; CHECK-i32-NEXT: fcvtzs w0, h5
-; CHECK-i32-NEXT: fcvtzs w15, h20
-; CHECK-i32-NEXT: fcvtzs w3, h3
-; CHECK-i32-NEXT: mov h20, v17.h[6]
-; CHECK-i32-NEXT: fcvtzs w5, h18
-; CHECK-i32-NEXT: mov h18, v17.h[2]
-; CHECK-i32-NEXT: fcvtzs w19, h0
-; CHECK-i32-NEXT: fcvtzs w20, h19
-; CHECK-i32-NEXT: fmov s5, w17
-; CHECK-i32-NEXT: fcvtzs w17, h21
-; CHECK-i32-NEXT: mov h16, v1.h[7]
-; CHECK-i32-NEXT: fmov s3, w2
-; CHECK-i32-NEXT: mov h21, v1.h[3]
-; CHECK-i32-NEXT: fcvtzs w2, h2
-; CHECK-i32-NEXT: fmov s2, w4
-; CHECK-i32-NEXT: fmov s1, w6
-; CHECK-i32-NEXT: fmov s0, w7
-; CHECK-i32-NEXT: mov h19, v17.h[7]
-; CHECK-i32-NEXT: fcvtzs w4, h20
-; CHECK-i32-NEXT: fcvtzs w6, h18
-; CHECK-i32-NEXT: mov h17, v17.h[3]
-; CHECK-i32-NEXT: mov v3.s[1], w3
-; CHECK-i32-NEXT: mov v1.s[1], w5
-; CHECK-i32-NEXT: mov v2.s[1], w20
-; CHECK-i32-NEXT: mov v4.s[1], w1
-; CHECK-i32-NEXT: mov v0.s[1], w19
-; CHECK-i32-NEXT: mov v5.s[1], w0
-; CHECK-i32-NEXT: mov v6.s[1], w14
-; CHECK-i32-NEXT: mov v7.s[1], w12
-; CHECK-i32-NEXT: fcvtzs w12, h16
-; CHECK-i32-NEXT: fcvtzs w14, h21
-; CHECK-i32-NEXT: fcvtzs w0, h19
-; CHECK-i32-NEXT: fcvtzs w1, h17
-; CHECK-i32-NEXT: mov v3.s[2], w18
-; CHECK-i32-NEXT: mov v1.s[2], w4
-; CHECK-i32-NEXT: mov v2.s[2], w2
-; CHECK-i32-NEXT: mov v4.s[2], w17
-; CHECK-i32-NEXT: mov v0.s[2], w6
-; CHECK-i32-NEXT: mov v5.s[2], w16
-; CHECK-i32-NEXT: mov v6.s[2], w11
-; CHECK-i32-NEXT: mov v7.s[2], w10
-; CHECK-i32-NEXT: mov v3.s[3], w12
-; CHECK-i32-NEXT: mov v1.s[3], w0
-; CHECK-i32-NEXT: mov v2.s[3], w14
-; CHECK-i32-NEXT: mov v4.s[3], w15
-; CHECK-i32-NEXT: mov v0.s[3], w1
-; CHECK-i32-NEXT: mov v5.s[3], w13
-; CHECK-i32-NEXT: mov v6.s[3], w9
-; CHECK-i32-NEXT: mov v7.s[3], w8
-; CHECK-i32-NEXT: ldp x20, x19, [sp], #16 // 16-byte Folded Reload
+; CHECK-i32-NEXT: ptrue p0.s, vl8
+; CHECK-i32-NEXT: uunpklo z1.s, z1.h
+; CHECK-i32-NEXT: uunpklo z0.s, z0.h
+; CHECK-i32-NEXT: uunpklo z3.s, z3.h
+; CHECK-i32-NEXT: uunpklo z4.s, z2.h
+; CHECK-i32-NEXT: movprfx z2, z1
+; CHECK-i32-NEXT: fcvtzs z2.s, p0/m, z1.h
+; CHECK-i32-NEXT: fcvtzs z0.s, p0/m, z0.h
+; CHECK-i32-NEXT: movprfx z6, z3
+; CHECK-i32-NEXT: fcvtzs z6.s, p0/m, z3.h
+; CHECK-i32-NEXT: fcvtzs z4.s, p0/m, z4.h
+; CHECK-i32-NEXT: movprfx z1, z0
+; CHECK-i32-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-i32-NEXT: movprfx z3, z2
+; CHECK-i32-NEXT: ext z3.b, z3.b, z2.b, #16
+; CHECK-i32-NEXT: movprfx z7, z6
+; CHECK-i32-NEXT: ext z7.b, z7.b, z6.b, #16
+; CHECK-i32-NEXT: movprfx z5, z4
+; CHECK-i32-NEXT: ext z5.b, z5.b, z4.b, #16
+; CHECK-i32-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-i32-NEXT: // kill: def $q2 killed $q2 killed $z2
+; CHECK-i32-NEXT: // kill: def $q4 killed $q4 killed $z4
+; CHECK-i32-NEXT: // kill: def $q6 killed $q6 killed $z6
+; CHECK-i32-NEXT: // kill: def $q1 killed $q1 killed $z1
+; CHECK-i32-NEXT: // kill: def $q3 killed $q3 killed $z3
+; CHECK-i32-NEXT: // kill: def $q7 killed $q7 killed $z7
+; CHECK-i32-NEXT: // kill: def $q5 killed $q5 killed $z5
; CHECK-i32-NEXT: ret
;
; CHECK-i64-LABEL: lrint_v32f16:
; CHECK-i64: // %bb.0:
-; CHECK-i64-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-i64-NEXT: sub x9, sp, #272
-; CHECK-i64-NEXT: mov x29, sp
-; CHECK-i64-NEXT: and sp, x9, #0xffffffffffffffe0
-; CHECK-i64-NEXT: mov d5, v0.d[1]
+; CHECK-i64-NEXT: mov d4, v3.d[1]
+; CHECK-i64-NEXT: mov d5, v2.d[1]
+; CHECK-i64-NEXT: mov x9, #28 // =0x1c
+; CHECK-i64-NEXT: mov d6, v1.d[1]
+; CHECK-i64-NEXT: frintx v3.4h, v3.4h
+; CHECK-i64-NEXT: mov d7, v0.d[1]
+; CHECK-i64-NEXT: frintx v2.4h, v2.4h
+; CHECK-i64-NEXT: frintx v1.4h, v1.4h
; CHECK-i64-NEXT: frintx v0.4h, v0.4h
-; CHECK-i64-NEXT: frintx v4.4h, v1.4h
-; CHECK-i64-NEXT: mov d1, v1.d[1]
; CHECK-i64-NEXT: ptrue p0.d, vl4
+; CHECK-i64-NEXT: frintx v4.4h, v4.4h
; CHECK-i64-NEXT: frintx v5.4h, v5.4h
-; CHECK-i64-NEXT: mov h6, v0.h[3]
-; CHECK-i64-NEXT: mov h7, v0.h[2]
-; CHECK-i64-NEXT: mov h16, v0.h[1]
-; CHECK-i64-NEXT: fcvtzs x12, h0
-; CHECK-i64-NEXT: frintx v1.4h, v1.4h
-; CHECK-i64-NEXT: frintx v0.4h, v2.4h
-; CHECK-i64-NEXT: mov d2, v2.d[1]
-; CHECK-i64-NEXT: mov h17, v5.h[3]
-; CHECK-i64-NEXT: fcvtzs x9, h6
-; CHECK-i64-NEXT: mov h6, v5.h[2]
-; CHECK-i64-NEXT: fcvtzs x10, h7
-; CHECK-i64-NEXT: fcvtzs x11, h16
-; CHECK-i64-NEXT: mov h7, v5.h[1]
-; CHECK-i64-NEXT: mov h16, v4.h[3]
-; CHECK-i64-NEXT: frintx v2.4h, v2.4h
-; CHECK-i64-NEXT: fcvtzs x13, h17
-; CHECK-i64-NEXT: stp x10, x9, [sp, #48]
-; CHECK-i64-NEXT: fcvtzs x9, h6
-; CHECK-i64-NEXT: mov h6, v4.h[2]
-; CHECK-i64-NEXT: fcvtzs x10, h7
-; CHECK-i64-NEXT: mov h7, v4.h[1]
-; CHECK-i64-NEXT: stp x12, x11, [sp, #32]
-; CHECK-i64-NEXT: fcvtzs x11, h5
-; CHECK-i64-NEXT: fcvtzs x12, h16
-; CHECK-i64-NEXT: mov h5, v1.h[3]
-; CHECK-i64-NEXT: stp x9, x13, [sp, #16]
-; CHECK-i64-NEXT: fcvtzs x13, h6
-; CHECK-i64-NEXT: mov h6, v1.h[2]
-; CHECK-i64-NEXT: fcvtzs x9, h7
-; CHECK-i64-NEXT: mov h7, v0.h[3]
-; CHECK-i64-NEXT: stp x11, x10, [sp]
-; CHECK-i64-NEXT: fcvtzs x10, h4
-; CHECK-i64-NEXT: mov h4, v1.h[1]
-; CHECK-i64-NEXT: fcvtzs x11, h5
-; CHECK-i64-NEXT: mov h5, v0.h[2]
-; CHECK-i64-NEXT: stp x13, x12, [sp, #112]
-; CHECK-i64-NEXT: fcvtzs x12, h6
-; CHECK-i64-NEXT: frintx v6.4h, v3.4h
-; CHECK-i64-NEXT: fcvtzs x13, h7
-; CHECK-i64-NEXT: mov d3, v3.d[1]
-; CHECK-i64-NEXT: stp x10, x9, [sp, #96]
-; CHECK-i64-NEXT: fcvtzs x9, h4
-; CHECK-i64-NEXT: mov h4, v0.h[1]
-; CHECK-i64-NEXT: fcvtzs x10, h1
-; CHECK-i64-NEXT: mov h1, v2.h[3]
-; CHECK-i64-NEXT: stp x12, x11, [sp, #80]
-; CHECK-i64-NEXT: fcvtzs x11, h5
-; CHECK-i64-NEXT: mov h5, v2.h[2]
-; CHECK-i64-NEXT: fcvtzs x12, h4
-; CHECK-i64-NEXT: mov h4, v2.h[1]
-; CHECK-i64-NEXT: stp x10, x9, [sp, #64]
-; CHECK-i64-NEXT: fcvtzs x9, h0
-; CHECK-i64-NEXT: fcvtzs x10, h1
-; CHECK-i64-NEXT: mov h0, v6.h[3]
-; CHECK-i64-NEXT: frintx v1.4h, v3.4h
-; CHECK-i64-NEXT: stp x11, x13, [sp, #176]
-; CHECK-i64-NEXT: fcvtzs x11, h5
-; CHECK-i64-NEXT: mov h3, v6.h[2]
-; CHECK-i64-NEXT: fcvtzs x13, h4
-; CHECK-i64-NEXT: mov h4, v6.h[1]
-; CHECK-i64-NEXT: stp x9, x12, [sp, #160]
-; CHECK-i64-NEXT: fcvtzs x9, h2
-; CHECK-i64-NEXT: fcvtzs x12, h0
-; CHECK-i64-NEXT: mov h0, v1.h[3]
-; CHECK-i64-NEXT: mov h2, v1.h[2]
-; CHECK-i64-NEXT: stp x11, x10, [sp, #144]
-; CHECK-i64-NEXT: fcvtzs x10, h3
-; CHECK-i64-NEXT: mov h3, v1.h[1]
-; CHECK-i64-NEXT: fcvtzs x11, h4
-; CHECK-i64-NEXT: stp x9, x13, [sp, #128]
-; CHECK-i64-NEXT: fcvtzs x9, h6
-; CHECK-i64-NEXT: fcvtzs x13, h0
-; CHECK-i64-NEXT: stp x10, x12, [sp, #240]
-; CHECK-i64-NEXT: fcvtzs x10, h2
-; CHECK-i64-NEXT: fcvtzs x12, h3
-; CHECK-i64-NEXT: stp x9, x11, [sp, #224]
-; CHECK-i64-NEXT: fcvtzs x9, h1
-; CHECK-i64-NEXT: stp x10, x13, [sp, #208]
-; CHECK-i64-NEXT: add x10, sp, #96
-; CHECK-i64-NEXT: stp x9, x12, [sp, #192]
-; CHECK-i64-NEXT: add x9, sp, #32
-; CHECK-i64-NEXT: ld1d { z0.d }, p0/z, [x9]
-; CHECK-i64-NEXT: mov x9, sp
-; CHECK-i64-NEXT: ld1d { z2.d }, p0/z, [x10]
-; CHECK-i64-NEXT: ld1d { z1.d }, p0/z, [x9]
-; CHECK-i64-NEXT: add x9, sp, #192
-; CHECK-i64-NEXT: add x10, sp, #64
-; CHECK-i64-NEXT: ld1d { z3.d }, p0/z, [x9]
-; CHECK-i64-NEXT: add x9, sp, #224
-; CHECK-i64-NEXT: ld1d { z4.d }, p0/z, [x10]
-; CHECK-i64-NEXT: add x10, sp, #128
-; CHECK-i64-NEXT: ld1d { z5.d }, p0/z, [x9]
-; CHECK-i64-NEXT: add x9, sp, #160
-; CHECK-i64-NEXT: ld1d { z6.d }, p0/z, [x10]
-; CHECK-i64-NEXT: mov x10, #28 // =0x1c
-; CHECK-i64-NEXT: ld1d { z7.d }, p0/z, [x9]
+; CHECK-i64-NEXT: frintx v6.4h, v6.4h
+; CHECK-i64-NEXT: uunpklo z3.s, z3.h
+; CHECK-i64-NEXT: frintx v7.4h, v7.4h
+; CHECK-i64-NEXT: uunpklo z2.s, z2.h
+; CHECK-i64-NEXT: uunpklo z1.s, z1.h
+; CHECK-i64-NEXT: uunpklo z0.s, z0.h
+; CHECK-i64-NEXT: uunpklo z4.s, z4.h
+; CHECK-i64-NEXT: uunpklo z5.s, z5.h
+; CHECK-i64-NEXT: uunpklo z6.s, z6.h
+; CHECK-i64-NEXT: uunpklo z3.d, z3.s
+; CHECK-i64-NEXT: uunpklo z7.s, z7.h
+; CHECK-i64-NEXT: uunpklo z2.d, z2.s
+; CHECK-i64-NEXT: uunpklo z1.d, z1.s
+; CHECK-i64-NEXT: uunpklo z0.d, z0.s
+; CHECK-i64-NEXT: uunpklo z4.d, z4.s
+; CHECK-i64-NEXT: uunpklo z5.d, z5.s
+; CHECK-i64-NEXT: uunpklo z6.d, z6.s
+; CHECK-i64-NEXT: fcvtzs z3.d, p0/m, z3.h
+; CHECK-i64-NEXT: uunpklo z7.d, z7.s
+; CHECK-i64-NEXT: fcvtzs z2.d, p0/m, z2.h
+; CHECK-i64-NEXT: fcvtzs z1.d, p0/m, z1.h
+; CHECK-i64-NEXT: fcvtzs z0.d, p0/m, z0.h
+; CHECK-i64-NEXT: fcvtzs z4.d, p0/m, z4.h
+; CHECK-i64-NEXT: fcvtzs z5.d, p0/m, z5.h
+; CHECK-i64-NEXT: fcvtzs z6.d, p0/m, z6.h
+; CHECK-i64-NEXT: fcvtzs z7.d, p0/m, z7.h
+; CHECK-i64-NEXT: st1d { z4.d }, p0, [x8, x9, lsl #3]
; CHECK-i64-NEXT: mov x9, #24 // =0x18
-; CHECK-i64-NEXT: st1d { z3.d }, p0, [x8, x10, lsl #3]
-; CHECK-i64-NEXT: st1d { z5.d }, p0, [x8, x9, lsl #3]
+; CHECK-i64-NEXT: st1d { z3.d }, p0, [x8, x9, lsl #3]
; CHECK-i64-NEXT: mov x9, #20 // =0x14
-; CHECK-i64-NEXT: st1d { z6.d }, p0, [x8, x9, lsl #3]
+; CHECK-i64-NEXT: st1d { z5.d }, p0, [x8, x9, lsl #3]
; CHECK-i64-NEXT: mov x9, #16 // =0x10
-; CHECK-i64-NEXT: st1d { z7.d }, p0, [x8, x9, lsl #3]
+; CHECK-i64-NEXT: st1d { z2.d }, p0, [x8, x9, lsl #3]
; CHECK-i64-NEXT: mov x9, #12 // =0xc
-; CHECK-i64-NEXT: st1d { z4.d }, p0, [x8, x9, lsl #3]
+; CHECK-i64-NEXT: st1d { z6.d }, p0, [x8, x9, lsl #3]
; CHECK-i64-NEXT: mov x9, #8 // =0x8
-; CHECK-i64-NEXT: st1d { z2.d }, p0, [x8, x9, lsl #3]
-; CHECK-i64-NEXT: mov x9, #4 // =0x4
; CHECK-i64-NEXT: st1d { z1.d }, p0, [x8, x9, lsl #3]
+; CHECK-i64-NEXT: mov x9, #4 // =0x4
+; CHECK-i64-NEXT: st1d { z7.d }, p0, [x8, x9, lsl #3]
; CHECK-i64-NEXT: st1d { z0.d }, p0, [x8]
-; CHECK-i64-NEXT: mov sp, x29
-; CHECK-i64-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-i64-NEXT: ret
%a = call <32 x iXLen> @llvm.lrint.v32iXLen.v32f16(<32 x half> %x)
ret <32 x iXLen> %a
@@ -534,17 +327,13 @@ define <4 x iXLen> @lrint_v4f32(<4 x float> %x) nounwind {
; CHECK-i64-LABEL: lrint_v4f32:
; CHECK-i64: // %bb.0:
; CHECK-i64-NEXT: frintx v0.4s, v0.4s
-; CHECK-i64-NEXT: mov s1, v0.s[2]
-; CHECK-i64-NEXT: mov s2, v0.s[3]
-; CHECK-i64-NEXT: mov s3, v0.s[1]
-; CHECK-i64-NEXT: fcvtzs x9, s0
-; CHECK-i64-NEXT: fcvtzs x8, s1
-; CHECK-i64-NEXT: fcvtzs x10, s2
-; CHECK-i64-NEXT: fcvtzs x11, s3
-; CHECK-i64-NEXT: fmov d0, x9
-; CHECK-i64-NEXT: fmov d1, x8
-; CHECK-i64-NEXT: mov v0.d[1], x11
-; CHECK-i64-NEXT: mov v1.d[1], x10
+; CHECK-i64-NEXT: ptrue p0.d, vl4
+; CHECK-i64-NEXT: uunpklo z0.d, z0.s
+; CHECK-i64-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-i64-NEXT: movprfx z1, z0
+; CHECK-i64-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-i64-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-i64-NEXT: // kill: def $q1 killed $q1 killed $z1
; CHECK-i64-NEXT: ret
%a = call <4 x iXLen> @llvm.lrint.v4iXLen.v4f32(<4 x float> %x)
ret <4 x iXLen> %a
@@ -559,57 +348,32 @@ define <8 x iXLen> @lrint_v8f32(<8 x float> %x) nounwind {
; CHECK-i32-NEXT: // kill: def $q1 killed $q1 def $z1
; CHECK-i32-NEXT: splice z0.d, p0, z0.d, z1.d
; CHECK-i32-NEXT: ptrue p0.s, vl8
-; CHECK-i32-NEXT: movprfx z2, z0
-; CHECK-i32-NEXT: frintx z2.s, p0/m, z0.s
-; CHECK-i32-NEXT: mov z0.s, z2.s[5]
-; CHECK-i32-NEXT: mov z1.s, z2.s[4]
-; CHECK-i32-NEXT: mov z3.s, z2.s[1]
-; CHECK-i32-NEXT: mov z4.s, z2.s[6]
-; CHECK-i32-NEXT: mov z5.s, z2.s[2]
-; CHECK-i32-NEXT: fcvtzs w8, s0
-; CHECK-i32-NEXT: fcvtzs s1, s1
-; CHECK-i32-NEXT: fcvtzs w9, s3
-; CHECK-i32-NEXT: fcvtzs s0, s2
-; CHECK-i32-NEXT: fcvtzs w10, s4
-; CHECK-i32-NEXT: fcvtzs w11, s5
-; CHECK-i32-NEXT: mov z3.s, z2.s[7]
-; CHECK-i32-NEXT: mov z2.s, z2.s[3]
-; CHECK-i32-NEXT: mov v1.s[1], w8
-; CHECK-i32-NEXT: mov v0.s[1], w9
-; CHECK-i32-NEXT: fcvtzs w8, s3
-; CHECK-i32-NEXT: fcvtzs w9, s2
-; CHECK-i32-NEXT: mov v1.s[2], w10
-; CHECK-i32-NEXT: mov v0.s[2], w11
-; CHECK-i32-NEXT: mov v1.s[3], w8
-; CHECK-i32-NEXT: mov v0.s[3], w9
+; CHECK-i32-NEXT: frintx z0.s, p0/m, z0.s
+; CHECK-i32-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-i32-NEXT: movprfx z1, z0
+; CHECK-i32-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-i32-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-i32-NEXT: // kill: def $q1 killed $q1 killed $z1
; CHECK-i32-NEXT: ret
;
; CHECK-i64-LABEL: lrint_v8f32:
; CHECK-i64: // %bb.0:
; CHECK-i64-NEXT: frintx v1.4s, v1.4s
; CHECK-i64-NEXT: frintx v0.4s, v0.4s
-; CHECK-i64-NEXT: mov s2, v1.s[2]
-; CHECK-i64-NEXT: mov s3, v0.s[2]
-; CHECK-i64-NEXT: mov s4, v0.s[1]
-; CHECK-i64-NEXT: mov s5, v1.s[3]
-; CHECK-i64-NEXT: mov s6, v1.s[1]
-; CHECK-i64-NEXT: mov s7, v0.s[3]
-; CHECK-i64-NEXT: fcvtzs x8, s0
-; CHECK-i64-NEXT: fcvtzs x10, s1
-; CHECK-i64-NEXT: fcvtzs x9, s2
-; CHECK-i64-NEXT: fcvtzs x11, s3
-; CHECK-i64-NEXT: fcvtzs x12, s4
-; CHECK-i64-NEXT: fcvtzs x13, s5
-; CHECK-i64-NEXT: fcvtzs x14, s6
-; CHECK-i64-NEXT: fcvtzs x15, s7
-; CHECK-i64-NEXT: fmov d0, x8
-; CHECK-i64-NEXT: fmov d2, x10
-; CHECK-i64-NEXT: fmov d3, x9
-; CHECK-i64-NEXT: fmov d1, x11
-; CHECK-i64-NEXT: mov v0.d[1], x12
-; CHECK-i64-NEXT: mov v2.d[1], x14
-; CHECK-i64-NEXT: mov v1.d[1], x15
-; CHECK-i64-NEXT: mov v3.d[1], x13
+; CHECK-i64-NEXT: ptrue p0.d, vl4
+; CHECK-i64-NEXT: uunpklo z1.d, z1.s
+; CHECK-i64-NEXT: uunpklo z0.d, z0.s
+; CHECK-i64-NEXT: movprfx z2, z1
+; CHECK-i64-NEXT: fcvtzs z2.d, p0/m, z1.s
+; CHECK-i64-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-i64-NEXT: movprfx z1, z0
+; CHECK-i64-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-i64-NEXT: movprfx z3, z2
+; CHECK-i64-NEXT: ext z3.b, z3.b, z2.b, #16
+; CHECK-i64-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-i64-NEXT: // kill: def $q2 killed $q2 killed $z2
+; CHECK-i64-NEXT: // kill: def $q1 killed $q1 killed $z1
+; CHECK-i64-NEXT: // kill: def $q3 killed $q3 killed $z3
; CHECK-i64-NEXT: ret
%a = call <8 x iXLen> @llvm.lrint.v8iXLen.v8f32(<8 x float> %x)
ret <8 x iXLen> %a
@@ -624,107 +388,56 @@ define <16 x iXLen> @lrint_v16f32(<16 x float> %x) nounwind {
; CHECK-i32-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-i32-NEXT: // kill: def $q3 killed $q3 def $z3
; CHECK-i32-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-i32-NEXT: splice z2.d, p0, z2.d, z3.d
; CHECK-i32-NEXT: splice z0.d, p0, z0.d, z1.d
+; CHECK-i32-NEXT: splice z2.d, p0, z2.d, z3.d
; CHECK-i32-NEXT: ptrue p0.s, vl8
-; CHECK-i32-NEXT: movprfx z4, z2
-; CHECK-i32-NEXT: frintx z4.s, p0/m, z2.s
-; CHECK-i32-NEXT: movprfx z5, z0
-; CHECK-i32-NEXT: frintx z5.s, p0/m, z0.s
-; CHECK-i32-NEXT: mov z0.s, z4.s[5]
-; CHECK-i32-NEXT: mov z1.s, z5.s[5]
-; CHECK-i32-NEXT: mov z3.s, z4.s[4]
-; CHECK-i32-NEXT: mov z2.s, z4.s[1]
-; CHECK-i32-NEXT: mov z7.s, z5.s[1]
-; CHECK-i32-NEXT: mov z17.s, z5.s[4]
-; CHECK-i32-NEXT: mov z6.s, z4.s[6]
-; CHECK-i32-NEXT: mov z16.s, z5.s[6]
-; CHECK-i32-NEXT: mov z18.s, z4.s[2]
-; CHECK-i32-NEXT: fcvtzs w8, s0
-; CHECK-i32-NEXT: fcvtzs w9, s1
-; CHECK-i32-NEXT: fcvtzs s0, s5
-; CHECK-i32-NEXT: fcvtzs w10, s2
-; CHECK-i32-NEXT: fcvtzs w11, s7
-; CHECK-i32-NEXT: fcvtzs s2, s4
-; CHECK-i32-NEXT: fcvtzs s3, s3
-; CHECK-i32-NEXT: fcvtzs s1, s17
-; CHECK-i32-NEXT: mov z19.s, z5.s[2]
-; CHECK-i32-NEXT: fcvtzs w12, s6
-; CHECK-i32-NEXT: fcvtzs w13, s16
-; CHECK-i32-NEXT: fcvtzs w14, s18
-; CHECK-i32-NEXT: mov z6.s, z4.s[7]
-; CHECK-i32-NEXT: mov z7.s, z5.s[7]
-; CHECK-i32-NEXT: mov z4.s, z4.s[3]
-; CHECK-i32-NEXT: fcvtzs w15, s19
-; CHECK-i32-NEXT: mov v0.s[1], w11
-; CHECK-i32-NEXT: mov v2.s[1], w10
-; CHECK-i32-NEXT: mov v1.s[1], w9
-; CHECK-i32-NEXT: mov v3.s[1], w8
-; CHECK-i32-NEXT: mov z5.s, z5.s[3]
-; CHECK-i32-NEXT: fcvtzs w8, s6
-; CHECK-i32-NEXT: fcvtzs w9, s7
-; CHECK-i32-NEXT: fcvtzs w10, s4
-; CHECK-i32-NEXT: fcvtzs w11, s5
-; CHECK-i32-NEXT: mov v0.s[2], w15
-; CHECK-i32-NEXT: mov v2.s[2], w14
-; CHECK-i32-NEXT: mov v1.s[2], w13
-; CHECK-i32-NEXT: mov v3.s[2], w12
-; CHECK-i32-NEXT: mov v0.s[3], w11
-; CHECK-i32-NEXT: mov v2.s[3], w10
-; CHECK-i32-NEXT: mov v1.s[3], w9
-; CHECK-i32-NEXT: mov v3.s[3], w8
+; CHECK-i32-NEXT: frintx z2.s, p0/m, z2.s
+; CHECK-i32-NEXT: frintx z0.s, p0/m, z0.s
+; CHECK-i32-NEXT: fcvtzs z2.s, p0/m, z2.s
+; CHECK-i32-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-i32-NEXT: movprfx z1, z0
+; CHECK-i32-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-i32-NEXT: movprfx z3, z2
+; CHECK-i32-NEXT: ext z3.b, z3.b, z2.b, #16
+; CHECK-i32-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-i32-NEXT: // kill: def $q2 killed $q2 killed $z2
+; CHECK-i32-NEXT: // kill: def $q1 killed $q1 killed $z1
+; CHECK-i32-NEXT: // kill: def $q3 killed $q3 killed $z3
; CHECK-i32-NEXT: ret
;
; CHECK-i64-LABEL: lrint_v16f32:
; CHECK-i64: // %bb.0:
-; CHECK-i64-NEXT: frintx v3.4s, v3.4s
-; CHECK-i64-NEXT: frintx v2.4s, v2.4s
; CHECK-i64-NEXT: frintx v1.4s, v1.4s
; CHECK-i64-NEXT: frintx v0.4s, v0.4s
-; CHECK-i64-NEXT: mov s4, v3.s[2]
-; CHECK-i64-NEXT: mov s5, v2.s[2]
-; CHECK-i64-NEXT: mov s6, v2.s[1]
-; CHECK-i64-NEXT: mov s7, v1.s[2]
-; CHECK-i64-NEXT: fcvtzs x8, s3
-; CHECK-i64-NEXT: mov s16, v0.s[2]
-; CHECK-i64-NEXT: fcvtzs x9, s2
-; CHECK-i64-NEXT: mov s17, v1.s[3]
-; CHECK-i64-NEXT: mov s18, v0.s[1]
-; CHECK-i64-NEXT: mov s19, v3.s[3]
-; CHECK-i64-NEXT: fcvtzs x14, s1
-; CHECK-i64-NEXT: mov s1, v1.s[1]
-; CHECK-i64-NEXT: fcvtzs x10, s4
-; CHECK-i64-NEXT: fcvtzs x11, s5
-; CHECK-i64-NEXT: mov s5, v0.s[3]
-; CHECK-i64-NEXT: mov s3, v3.s[1]
-; CHECK-i64-NEXT: mov s2, v2.s[3]
-; CHECK-i64-NEXT: fcvtzs x12, s6
-; CHECK-i64-NEXT: fcvtzs x13, s7
-; CHECK-i64-NEXT: fcvtzs x15, s16
-; CHECK-i64-NEXT: fmov d6, x8
-; CHECK-i64-NEXT: fcvtzs x8, s0
-; CHECK-i64-NEXT: fmov d4, x9
-; CHECK-i64-NEXT: fcvtzs x9, s17
-; CHECK-i64-NEXT: fcvtzs x16, s5
-; CHECK-i64-NEXT: fcvtzs x17, s18
-; CHECK-i64-NEXT: fmov d7, x10
-; CHECK-i64-NEXT: fmov d5, x11
-; CHECK-i64-NEXT: fcvtzs x10, s1
-; CHECK-i64-NEXT: fcvtzs x11, s19
-; CHECK-i64-NEXT: fcvtzs x18, s3
-; CHECK-i64-NEXT: fcvtzs x0, s2
-; CHECK-i64-NEXT: fmov d3, x13
-; CHECK-i64-NEXT: fmov d1, x15
-; CHECK-i64-NEXT: fmov d0, x8
-; CHECK-i64-NEXT: fmov d2, x14
-; CHECK-i64-NEXT: mov v4.d[1], x12
-; CHECK-i64-NEXT: mov v3.d[1], x9
-; CHECK-i64-NEXT: mov v7.d[1], x11
-; CHECK-i64-NEXT: mov v0.d[1], x17
-; CHECK-i64-NEXT: mov v1.d[1], x16
-; CHECK-i64-NEXT: mov v2.d[1], x10
-; CHECK-i64-NEXT: mov v5.d[1], x0
-; CHECK-i64-NEXT: mov v6.d[1], x18
+; CHECK-i64-NEXT: frintx v3.4s, v3.4s
+; CHECK-i64-NEXT: frintx v2.4s, v2.4s
+; CHECK-i64-NEXT: ptrue p0.d, vl4
+; CHECK-i64-NEXT: uunpklo z1.d, z1.s
+; CHECK-i64-NEXT: uunpklo z0.d, z0.s
+; CHECK-i64-NEXT: uunpklo z3.d, z3.s
+; CHECK-i64-NEXT: uunpklo z4.d, z2.s
+; CHECK-i64-NEXT: movprfx z2, z1
+; CHECK-i64-NEXT: fcvtzs z2.d, p0/m, z1.s
+; CHECK-i64-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-i64-NEXT: movprfx z6, z3
+; CHECK-i64-NEXT: fcvtzs z6.d, p0/m, z3.s
+; CHECK-i64-NEXT: fcvtzs z4.d, p0/m, z4.s
+; CHECK-i64-NEXT: movprfx z1, z0
+; CHECK-i64-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-i64-NEXT: movprfx z3, z2
+; CHECK-i64-NEXT: ext z3.b, z3.b, z2.b, #16
+; CHECK-i64-NEXT: movprfx z7, z6
+; CHECK-i64-NEXT: ext z7.b, z7.b, z6.b, #16
+; CHECK-i64-NEXT: movprfx z5, z4
+; CHECK-i64-NEXT: ext z5.b, z5.b, z4.b, #16
+; CHECK-i64-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-i64-NEXT: // kill: def $q2 killed $q2 killed $z2
+; CHECK-i64-NEXT: // kill: def $q4 killed $q4 killed $z4
+; CHECK-i64-NEXT: // kill: def $q6 killed $q6 killed $z6
+; CHECK-i64-NEXT: // kill: def $q1 killed $q1 killed $z1
+; CHECK-i64-NEXT: // kill: def $q3 killed $q3 killed $z3
+; CHECK-i64-NEXT: // kill: def $q7 killed $q7 killed $z7
+; CHECK-i64-NEXT: // kill: def $q5 killed $q5 killed $z5
; CHECK-i64-NEXT: ret
%a = call <16 x iXLen> @llvm.lrint.v16iXLen.v16f32(<16 x float> %x)
ret <16 x iXLen> %a
@@ -734,236 +447,88 @@ declare <16 x iXLen> @llvm.lrint.v16iXLen.v16f32(<16 x float>)
define <32 x iXLen> @lrint_v32f32(<32 x float> %x) nounwind {
; CHECK-i32-LABEL: lrint_v32f32:
; CHECK-i32: // %bb.0:
-; CHECK-i32-NEXT: str x19, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-i32-NEXT: ptrue p1.d, vl2
+; CHECK-i32-NEXT: ptrue p0.d, vl2
; CHECK-i32-NEXT: // kill: def $q6 killed $q6 def $z6
-; CHECK-i32-NEXT: // kill: def $q7 killed $q7 def $z7
; CHECK-i32-NEXT: // kill: def $q4 killed $q4 def $z4
; CHECK-i32-NEXT: // kill: def $q2 killed $q2 def $z2
; CHECK-i32-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-i32-NEXT: // kill: def $q7 killed $q7 def $z7
; CHECK-i32-NEXT: // kill: def $q5 killed $q5 def $z5
; CHECK-i32-NEXT: // kill: def $q3 killed $q3 def $z3
; CHECK-i32-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-i32-NEXT: splice z0.d, p0, z0.d, z1.d
+; CHECK-i32-NEXT: splice z2.d, p0, z2.d, z3.d
+; CHECK-i32-NEXT: splice z4.d, p0, z4.d, z5.d
+; CHECK-i32-NEXT: splice z6.d, p0, z6.d, z7.d
; CHECK-i32-NEXT: ptrue p0.s, vl8
-; CHECK-i32-NEXT: splice z6.d, p1, z6.d, z7.d
-; CHECK-i32-NEXT: splice z4.d, p1, z4.d, z5.d
-; CHECK-i32-NEXT: splice z2.d, p1, z2.d, z3.d
-; CHECK-i32-NEXT: splice z0.d, p1, z0.d, z1.d
-; CHECK-i32-NEXT: movprfx z16, z6
-; CHECK-i32-NEXT: frintx z16.s, p0/m, z6.s
-; CHECK-i32-NEXT: movprfx z17, z4
-; CHECK-i32-NEXT: frintx z17.s, p0/m, z4.s
-; CHECK-i32-NEXT: movprfx z18, z2
-; CHECK-i32-NEXT: frintx z18.s, p0/m, z2.s
-; CHECK-i32-NEXT: movprfx z19, z0
-; CHECK-i32-NEXT: frintx z19.s, p0/m, z0.s
-; CHECK-i32-NEXT: mov z0.s, z16.s[7]
-; CHECK-i32-NEXT: mov z2.s, z16.s[5]
-; CHECK-i32-NEXT: mov z3.s, z16.s[4]
-; CHECK-i32-NEXT: mov z1.s, z16.s[6]
-; CHECK-i32-NEXT: mov z4.s, z17.s[7]
-; CHECK-i32-NEXT: mov z6.s, z17.s[6]
-; CHECK-i32-NEXT: mov z20.s, z17.s[5]
-; CHECK-i32-NEXT: mov z5.s, z17.s[4]
-; CHECK-i32-NEXT: mov z21.s, z19.s[1]
-; CHECK-i32-NEXT: fcvtzs w8, s0
-; CHECK-i32-NEXT: mov z0.s, z18.s[7]
-; CHECK-i32-NEXT: fcvtzs w13, s2
-; CHECK-i32-NEXT: mov z2.s, z18.s[5]
-; CHECK-i32-NEXT: fcvtzs s7, s3
-; CHECK-i32-NEXT: mov z3.s, z19.s[7]
-; CHECK-i32-NEXT: fcvtzs w10, s1
-; CHECK-i32-NEXT: mov z1.s, z18.s[6]
-; CHECK-i32-NEXT: fcvtzs w9, s4
-; CHECK-i32-NEXT: fcvtzs w12, s6
-; CHECK-i32-NEXT: fcvtzs w11, s0
-; CHECK-i32-NEXT: mov z0.s, z19.s[6]
-; CHECK-i32-NEXT: mov z4.s, z19.s[5]
-; CHECK-i32-NEXT: fcvtzs w18, s2
-; CHECK-i32-NEXT: mov z2.s, z18.s[4]
-; CHECK-i32-NEXT: fcvtzs w15, s3
-; CHECK-i32-NEXT: mov z3.s, z16.s[1]
-; CHECK-i32-NEXT: mov z6.s, z17.s[1]
-; CHECK-i32-NEXT: fcvtzs w14, s1
-; CHECK-i32-NEXT: mov z1.s, z16.s[2]
-; CHECK-i32-NEXT: fcvtzs w17, s0
-; CHECK-i32-NEXT: fcvtzs w1, s4
-; CHECK-i32-NEXT: mov z0.s, z17.s[2]
-; CHECK-i32-NEXT: mov z4.s, z19.s[4]
-; CHECK-i32-NEXT: fcvtzs w2, s3
-; CHECK-i32-NEXT: fcvtzs s3, s2
-; CHECK-i32-NEXT: mov z2.s, z18.s[1]
-; CHECK-i32-NEXT: fcvtzs w6, s6
-; CHECK-i32-NEXT: mov z6.s, z19.s[2]
-; CHECK-i32-NEXT: fcvtzs w16, s20
-; CHECK-i32-NEXT: fcvtzs w0, s1
-; CHECK-i32-NEXT: fcvtzs w3, s0
-; CHECK-i32-NEXT: fcvtzs s1, s4
-; CHECK-i32-NEXT: fcvtzs w7, s21
-; CHECK-i32-NEXT: fcvtzs s0, s19
-; CHECK-i32-NEXT: fcvtzs s4, s17
-; CHECK-i32-NEXT: fcvtzs w19, s2
-; CHECK-i32-NEXT: fcvtzs s2, s18
-; CHECK-i32-NEXT: fcvtzs s5, s5
-; CHECK-i32-NEXT: fcvtzs w5, s6
-; CHECK-i32-NEXT: fcvtzs s6, s16
-; CHECK-i32-NEXT: mov z20.s, z18.s[2]
-; CHECK-i32-NEXT: mov v1.s[1], w1
-; CHECK-i32-NEXT: mov v3.s[1], w18
-; CHECK-i32-NEXT: mov v7.s[1], w13
-; CHECK-i32-NEXT: mov v0.s[1], w7
-; CHECK-i32-NEXT: mov v4.s[1], w6
-; CHECK-i32-NEXT: mov z16.s, z16.s[3]
-; CHECK-i32-NEXT: fcvtzs w4, s20
-; CHECK-i32-NEXT: mov v2.s[1], w19
-; CHECK-i32-NEXT: mov v5.s[1], w16
-; CHECK-i32-NEXT: mov v6.s[1], w2
-; CHECK-i32-NEXT: mov z17.s, z17.s[3]
-; CHECK-i32-NEXT: mov z18.s, z18.s[3]
-; CHECK-i32-NEXT: mov z19.s, z19.s[3]
-; CHECK-i32-NEXT: fcvtzs w13, s16
-; CHECK-i32-NEXT: mov v1.s[2], w17
-; CHECK-i32-NEXT: mov v0.s[2], w5
-; CHECK-i32-NEXT: mov v4.s[2], w3
-; CHECK-i32-NEXT: mov v3.s[2], w14
-; CHECK-i32-NEXT: fcvtzs w16, s17
-; CHECK-i32-NEXT: fcvtzs w18, s18
-; CHECK-i32-NEXT: mov v2.s[2], w4
-; CHECK-i32-NEXT: fcvtzs w1, s19
-; CHECK-i32-NEXT: mov v6.s[2], w0
-; CHECK-i32-NEXT: mov v5.s[2], w12
-; CHECK-i32-NEXT: mov v7.s[2], w10
-; CHECK-i32-NEXT: mov v1.s[3], w15
-; CHECK-i32-NEXT: mov v3.s[3], w11
-; CHECK-i32-NEXT: mov v2.s[3], w18
-; CHECK-i32-NEXT: mov v4.s[3], w16
-; CHECK-i32-NEXT: mov v0.s[3], w1
-; CHECK-i32-NEXT: mov v6.s[3], w13
-; CHECK-i32-NEXT: mov v5.s[3], w9
-; CHECK-i32-NEXT: mov v7.s[3], w8
-; CHECK-i32-NEXT: ldr x19, [sp], #16 // 8-byte Folded Reload
+; CHECK-i32-NEXT: frintx z2.s, p0/m, z2.s
+; CHECK-i32-NEXT: frintx z0.s, p0/m, z0.s
+; CHECK-i32-NEXT: frintx z4.s, p0/m, z4.s
+; CHECK-i32-NEXT: frintx z6.s, p0/m, z6.s
+; CHECK-i32-NEXT: fcvtzs z2.s, p0/m, z2.s
+; CHECK-i32-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-i32-NEXT: fcvtzs z4.s, p0/m, z4.s
+; CHECK-i32-NEXT: fcvtzs z6.s, p0/m, z6.s
+; CHECK-i32-NEXT: movprfx z1, z0
+; CHECK-i32-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-i32-NEXT: movprfx z3, z2
+; CHECK-i32-NEXT: ext z3.b, z3.b, z2.b, #16
+; CHECK-i32-NEXT: movprfx z5, z4
+; CHECK-i32-NEXT: ext z5.b, z5.b, z4.b, #16
+; CHECK-i32-NEXT: movprfx z7, z6
+; CHECK-i32-NEXT: ext z7.b, z7.b, z6.b, #16
+; CHECK-i32-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-i32-NEXT: // kill: def $q2 killed $q2 killed $z2
+; CHECK-i32-NEXT: // kill: def $q4 killed $q4 killed $z4
+; CHECK-i32-NEXT: // kill: def $q6 killed $q6 killed $z6
+; CHECK-i32-NEXT: // kill: def $q1 killed $q1 killed $z1
+; CHECK-i32-NEXT: // kill: def $q3 killed $q3 killed $z3
+; CHECK-i32-NEXT: // kill: def $q5 killed $q5 killed $z5
+; CHECK-i32-NEXT: // kill: def $q7 killed $q7 killed $z7
; CHECK-i32-NEXT: ret
;
; CHECK-i64-LABEL: lrint_v32f32:
; CHECK-i64: // %bb.0:
-; CHECK-i64-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-i64-NEXT: sub x9, sp, #272
-; CHECK-i64-NEXT: mov x29, sp
-; CHECK-i64-NEXT: and sp, x9, #0xffffffffffffffe0
-; CHECK-i64-NEXT: frintx v0.4s, v0.4s
-; CHECK-i64-NEXT: frintx v1.4s, v1.4s
+; CHECK-i64-NEXT: frintx v7.4s, v7.4s
+; CHECK-i64-NEXT: frintx v6.4s, v6.4s
+; CHECK-i64-NEXT: mov x9, #28 // =0x1c
+; CHECK-i64-NEXT: frintx v5.4s, v5.4s
+; CHECK-i64-NEXT: frintx v4.4s, v4.4s
+; CHECK-i64-NEXT: frintx v3.4s, v3.4s
; CHECK-i64-NEXT: frintx v2.4s, v2.4s
; CHECK-i64-NEXT: ptrue p0.d, vl4
-; CHECK-i64-NEXT: mov s16, v0.s[3]
-; CHECK-i64-NEXT: mov s17, v0.s[2]
-; CHECK-i64-NEXT: mov s18, v0.s[1]
-; CHECK-i64-NEXT: fcvtzs x12, s0
-; CHECK-i64-NEXT: frintx v0.4s, v3.4s
-; CHECK-i64-NEXT: mov s3, v2.s[3]
-; CHECK-i64-NEXT: fcvtzs x9, s16
-; CHECK-i64-NEXT: mov s16, v1.s[3]
-; CHECK-i64-NEXT: fcvtzs x10, s17
-; CHECK-i64-NEXT: mov s17, v1.s[2]
-; CHECK-i64-NEXT: fcvtzs x11, s18
-; CHECK-i64-NEXT: mov s18, v1.s[1]
-; CHECK-i64-NEXT: fcvtzs x13, s16
-; CHECK-i64-NEXT: stp x10, x9, [sp, #16]
-; CHECK-i64-NEXT: mov s16, v2.s[2]
-; CHECK-i64-NEXT: fcvtzs x9, s17
-; CHECK-i64-NEXT: fcvtzs x10, s18
-; CHECK-i64-NEXT: mov s17, v2.s[1]
-; CHECK-i64-NEXT: stp x12, x11, [sp]
-; CHECK-i64-NEXT: fcvtzs x11, s1
-; CHECK-i64-NEXT: frintx v1.4s, v4.4s
-; CHECK-i64-NEXT: fcvtzs x12, s3
-; CHECK-i64-NEXT: mov s3, v0.s[3]
-; CHECK-i64-NEXT: mov s4, v0.s[2]
-; CHECK-i64-NEXT: stp x9, x13, [sp, #48]
-; CHECK-i64-NEXT: fcvtzs x13, s16
-; CHECK-i64-NEXT: fcvtzs x9, s17
-; CHECK-i64-NEXT: mov s16, v0.s[1]
-; CHECK-i64-NEXT: stp x11, x10, [sp, #32]
-; CHECK-i64-NEXT: fcvtzs x10, s2
-; CHECK-i64-NEXT: frintx v2.4s, v5.4s
-; CHECK-i64-NEXT: fcvtzs x11, s3
-; CHECK-i64-NEXT: mov s3, v1.s[3]
-; CHECK-i64-NEXT: mov s5, v1.s[1]
-; CHECK-i64-NEXT: stp x13, x12, [sp, #80]
-; CHECK-i64-NEXT: fcvtzs x12, s4
-; CHECK-i64-NEXT: mov s4, v1.s[2]
-; CHECK-i64-NEXT: fcvtzs x13, s16
-; CHECK-i64-NEXT: stp x10, x9, [sp, #64]
-; CHECK-i64-NEXT: fcvtzs x9, s0
-; CHECK-i64-NEXT: mov s0, v2.s[3]
-; CHECK-i64-NEXT: fcvtzs x10, s3
-; CHECK-i64-NEXT: frintx v3.4s, v6.4s
-; CHECK-i64-NEXT: stp x12, x11, [sp, #112]
-; CHECK-i64-NEXT: fcvtzs x11, s4
-; CHECK-i64-NEXT: mov s4, v2.s[2]
-; CHECK-i64-NEXT: fcvtzs x12, s5
-; CHECK-i64-NEXT: mov s5, v2.s[1]
-; CHECK-i64-NEXT: stp x9, x13, [sp, #96]
-; CHECK-i64-NEXT: fcvtzs x9, s1
-; CHECK-i64-NEXT: fcvtzs x13, s0
-; CHECK-i64-NEXT: mov s0, v3.s[3]
-; CHECK-i64-NEXT: frintx v1.4s, v7.4s
-; CHECK-i64-NEXT: stp x11, x10, [sp, #144]
-; CHECK-i64-NEXT: fcvtzs x10, s4
-; CHECK-i64-NEXT: mov s4, v3.s[2]
-; CHECK-i64-NEXT: fcvtzs x11, s5
-; CHECK-i64-NEXT: mov s5, v3.s[1]
-; CHECK-i64-NEXT: stp x9, x12, [sp, #128]
-; CHECK-i64-NEXT: fcvtzs x9, s2
-; CHECK-i64-NEXT: fcvtzs x12, s0
-; CHECK-i64-NEXT: mov s0, v1.s[3]
-; CHECK-i64-NEXT: mov s2, v1.s[2]
-; CHECK-i64-NEXT: stp x10, x13, [sp, #176]
-; CHECK-i64-NEXT: fcvtzs x10, s4
-; CHECK-i64-NEXT: mov s4, v1.s[1]
-; CHECK-i64-NEXT: fcvtzs x13, s5
-; CHECK-i64-NEXT: stp x9, x11, [sp, #160]
-; CHECK-i64-NEXT: fcvtzs x9, s3
-; CHECK-i64-NEXT: fcvtzs x11, s0
-; CHECK-i64-NEXT: stp x10, x12, [sp, #208]
-; CHECK-i64-NEXT: fcvtzs x10, s2
-; CHECK-i64-NEXT: fcvtzs x12, s4
-; CHECK-i64-NEXT: stp x9, x13, [sp, #192]
-; CHECK-i64-NEXT: fcvtzs x9, s1
-; CHECK-i64-NEXT: stp x10, x11, [sp, #240]
-; CHECK-i64-NEXT: add x10, sp, #64
-; CHECK-i64-NEXT: stp x9, x12, [sp, #224]
-; CHECK-i64-NEXT: mov x9, sp
-; CHECK-i64-NEXT: ld1d { z0.d }, p0/z, [x9]
-; CHECK-i64-NEXT: add x9, sp, #32
-; CHECK-i64-NEXT: ld1d { z2.d }, p0/z, [x10]
-; CHECK-i64-NEXT: ld1d { z1.d }, p0/z, [x9]
-; CHECK-i64-NEXT: add x9, sp, #224
-; CHECK-i64-NEXT: add x10, sp, #96
-; CHECK-i64-NEXT: ld1d { z3.d }, p0/z, [x9]
-; CHECK-i64-NEXT: add x9, sp, #192
-; CHECK-i64-NEXT: ld1d { z4.d }, p0/z, [x10]
-; CHECK-i64-NEXT: add x10, sp, #160
-; CHECK-i64-NEXT: ld1d { z5.d }, p0/z, [x9]
-; CHECK-i64-NEXT: add x9, sp, #128
-; CHECK-i64-NEXT: ld1d { z6.d }, p0/z, [x10]
-; CHECK-i64-NEXT: mov x10, #28 // =0x1c
-; CHECK-i64-NEXT: ld1d { z7.d }, p0/z, [x9]
+; CHECK-i64-NEXT: frintx v1.4s, v1.4s
+; CHECK-i64-NEXT: frintx v0.4s, v0.4s
+; CHECK-i64-NEXT: uunpklo z7.d, z7.s
+; CHECK-i64-NEXT: uunpklo z6.d, z6.s
+; CHECK-i64-NEXT: uunpklo z5.d, z5.s
+; CHECK-i64-NEXT: uunpklo z4.d, z4.s
+; CHECK-i64-NEXT: uunpklo z3.d, z3.s
+; CHECK-i64-NEXT: uunpklo z2.d, z2.s
+; CHECK-i64-NEXT: uunpklo z1.d, z1.s
+; CHECK-i64-NEXT: uunpklo z0.d, z0.s
+; CHECK-i64-NEXT: fcvtzs z7.d, p0/m, z7.s
+; CHECK-i64-NEXT: fcvtzs z6.d, p0/m, z6.s
+; CHECK-i64-NEXT: fcvtzs z5.d, p0/m, z5.s
+; CHECK-i64-NEXT: fcvtzs z4.d, p0/m, z4.s
+; CHECK-i64-NEXT: fcvtzs z3.d, p0/m, z3.s
+; CHECK-i64-NEXT: fcvtzs z2.d, p0/m, z2.s
+; CHECK-i64-NEXT: fcvtzs z1.d, p0/m, z1.s
+; CHECK-i64-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-i64-NEXT: st1d { z7.d }, p0, [x8, x9, lsl #3]
; CHECK-i64-NEXT: mov x9, #24 // =0x18
-; CHECK-i64-NEXT: st1d { z3.d }, p0, [x8, x10, lsl #3]
-; CHECK-i64-NEXT: st1d { z5.d }, p0, [x8, x9, lsl #3]
-; CHECK-i64-NEXT: mov x9, #20 // =0x14
; CHECK-i64-NEXT: st1d { z6.d }, p0, [x8, x9, lsl #3]
+; CHECK-i64-NEXT: mov x9, #20 // =0x14
+; CHECK-i64-NEXT: st1d { z5.d }, p0, [x8, x9, lsl #3]
; CHECK-i64-NEXT: mov x9, #16 // =0x10
-; CHECK-i64-NEXT: st1d { z7.d }, p0, [x8, x9, lsl #3]
-; CHECK-i64-NEXT: mov x9, #12 // =0xc
; CHECK-i64-NEXT: st1d { z4.d }, p0, [x8, x9, lsl #3]
+; CHECK-i64-NEXT: mov x9, #12 // =0xc
+; CHECK-i64-NEXT: st1d { z3.d }, p0, [x8, x9, lsl #3]
; CHECK-i64-NEXT: mov x9, #8 // =0x8
; CHECK-i64-NEXT: st1d { z2.d }, p0, [x8, x9, lsl #3]
; CHECK-i64-NEXT: mov x9, #4 // =0x4
; CHECK-i64-NEXT: st1d { z1.d }, p0, [x8, x9, lsl #3]
; CHECK-i64-NEXT: st1d { z0.d }, p0, [x8]
-; CHECK-i64-NEXT: mov sp, x29
-; CHECK-i64-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-i64-NEXT: ret
%a = call <32 x iXLen> @llvm.lrint.v32iXLen.v32f32(<32 x float> %x)
ret <32 x iXLen> %a
@@ -1016,21 +581,16 @@ define <4 x iXLen> @lrint_v4f64(<4 x double> %x) nounwind {
; CHECK-i32-NEXT: ptrue p0.d, vl2
; CHECK-i32-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-i32-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-i32-NEXT: mov z2.d, #0xffffffff80000000
; CHECK-i32-NEXT: splice z0.d, p0, z0.d, z1.d
; CHECK-i32-NEXT: ptrue p0.d, vl4
-; CHECK-i32-NEXT: movprfx z1, z0
-; CHECK-i32-NEXT: frintx z1.d, p0/m, z0.d
-; CHECK-i32-NEXT: mov z0.d, z1.d[1]
-; CHECK-i32-NEXT: fcvtzs w8, d1
-; CHECK-i32-NEXT: mov z2.d, z1.d[2]
-; CHECK-i32-NEXT: mov z1.d, z1.d[3]
-; CHECK-i32-NEXT: fcvtzs w9, d0
-; CHECK-i32-NEXT: fmov s0, w8
-; CHECK-i32-NEXT: fcvtzs w8, d2
-; CHECK-i32-NEXT: mov v0.s[1], w9
-; CHECK-i32-NEXT: mov v0.s[2], w8
-; CHECK-i32-NEXT: fcvtzs w8, d1
-; CHECK-i32-NEXT: mov v0.s[3], w8
+; CHECK-i32-NEXT: mov z1.d, #0x7fffffff
+; CHECK-i32-NEXT: frintx z0.d, p0/m, z0.d
+; CHECK-i32-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-i32-NEXT: smin z0.d, p0/m, z0.d, z1.d
+; CHECK-i32-NEXT: smax z0.d, p0/m, z0.d, z2.d
+; CHECK-i32-NEXT: uzp1 z0.s, z0.s, z0.s
+; CHECK-i32-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-i32-NEXT: ret
;
; CHECK-i64-LABEL: lrint_v4f64:
@@ -1041,15 +601,11 @@ define <4 x iXLen> @lrint_v4f64(<4 x double> %x) nounwind {
; CHECK-i64-NEXT: splice z0.d, p0, z0.d, z1.d
; CHECK-i64-NEXT: ptrue p0.d, vl4
; CHECK-i64-NEXT: frintx z0.d, p0/m, z0.d
-; CHECK-i64-NEXT: mov z1.d, z0.d[3]
-; CHECK-i64-NEXT: mov z2.d, z0.d[2]
-; CHECK-i64-NEXT: mov z3.d, z0.d[1]
-; CHECK-i64-NEXT: fcvtzs d0, d0
-; CHECK-i64-NEXT: fcvtzs x8, d1
-; CHECK-i64-NEXT: fcvtzs d1, d2
-; CHECK-i64-NEXT: fcvtzs x9, d3
-; CHECK-i64-NEXT: mov v0.d[1], x9
-; CHECK-i64-NEXT: mov v1.d[1], x8
+; CHECK-i64-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-i64-NEXT: movprfx z1, z0
+; CHECK-i64-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-i64-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-i64-NEXT: // kill: def $q1 killed $q1 killed $z1
; CHECK-i64-NEXT: ret
%a = call <4 x iXLen> @llvm.lrint.v4iXLen.v4f64(<4 x double> %x)
ret <4 x iXLen> %a
@@ -1064,34 +620,23 @@ define <8 x iXLen> @lrint_v8f64(<8 x double> %x) nounwind {
; CHECK-i32-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-i32-NEXT: // kill: def $q3 killed $q3 def $z3
; CHECK-i32-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-i32-NEXT: splice z0.d, p0, z0.d, z1.d
; CHECK-i32-NEXT: splice z2.d, p0, z2.d, z3.d
+; CHECK-i32-NEXT: splice z0.d, p0, z0.d, z1.d
; CHECK-i32-NEXT: ptrue p0.d, vl4
-; CHECK-i32-NEXT: movprfx z3, z0
-; CHECK-i32-NEXT: frintx z3.d, p0/m, z0.d
+; CHECK-i32-NEXT: mov z1.d, #0x7fffffff
+; CHECK-i32-NEXT: mov z3.d, #0xffffffff80000000
+; CHECK-i32-NEXT: frintx z0.d, p0/m, z0.d
; CHECK-i32-NEXT: frintx z2.d, p0/m, z2.d
-; CHECK-i32-NEXT: mov z0.d, z3.d[1]
-; CHECK-i32-NEXT: mov z1.d, z2.d[1]
-; CHECK-i32-NEXT: fcvtzs w8, d3
-; CHECK-i32-NEXT: fcvtzs w9, d2
-; CHECK-i32-NEXT: mov z4.d, z3.d[2]
-; CHECK-i32-NEXT: mov z5.d, z2.d[2]
-; CHECK-i32-NEXT: mov z3.d, z3.d[3]
-; CHECK-i32-NEXT: mov z2.d, z2.d[3]
-; CHECK-i32-NEXT: fcvtzs w10, d0
-; CHECK-i32-NEXT: fcvtzs w11, d1
-; CHECK-i32-NEXT: fmov s0, w8
-; CHECK-i32-NEXT: fcvtzs w8, d4
-; CHECK-i32-NEXT: fmov s1, w9
-; CHECK-i32-NEXT: fcvtzs w9, d5
-; CHECK-i32-NEXT: mov v0.s[1], w10
-; CHECK-i32-NEXT: mov v1.s[1], w11
-; CHECK-i32-NEXT: mov v0.s[2], w8
-; CHECK-i32-NEXT: fcvtzs w8, d3
-; CHECK-i32-NEXT: mov v1.s[2], w9
-; CHECK-i32-NEXT: fcvtzs w9, d2
-; CHECK-i32-NEXT: mov v0.s[3], w8
-; CHECK-i32-NEXT: mov v1.s[3], w9
+; CHECK-i32-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-i32-NEXT: fcvtzs z2.d, p0/m, z2.d
+; CHECK-i32-NEXT: smin z0.d, p0/m, z0.d, z1.d
+; CHECK-i32-NEXT: smin z1.d, p0/m, z1.d, z2.d
+; CHECK-i32-NEXT: smax z0.d, p0/m, z0.d, z3.d
+; CHECK-i32-NEXT: smax z1.d, p0/m, z1.d, z3.d
+; CHECK-i32-NEXT: uzp1 z0.s, z0.s, z0.s
+; CHECK-i32-NEXT: uzp1 z1.s, z1.s, z1.s
+; CHECK-i32-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-i32-NEXT: // kill: def $q1 killed $q1 killed $z1
; CHECK-i32-NEXT: ret
;
; CHECK-i64-LABEL: lrint_v8f64:
@@ -1106,24 +651,16 @@ define <8 x iXLen> @lrint_v8f64(<8 x double> %x) nounwind {
; CHECK-i64-NEXT: ptrue p0.d, vl4
; CHECK-i64-NEXT: frintx z2.d, p0/m, z2.d
; CHECK-i64-NEXT: frintx z0.d, p0/m, z0.d
-; CHECK-i64-NEXT: mov z1.d, z2.d[3]
-; CHECK-i64-NEXT: mov z3.d, z0.d[3]
-; CHECK-i64-NEXT: mov z4.d, z0.d[1]
-; CHECK-i64-NEXT: mov z5.d, z2.d[2]
-; CHECK-i64-NEXT: mov z6.d, z0.d[2]
-; CHECK-i64-NEXT: mov z7.d, z2.d[1]
-; CHECK-i64-NEXT: fcvtzs d2, d2
-; CHECK-i64-NEXT: fcvtzs d0, d0
-; CHECK-i64-NEXT: fcvtzs x8, d1
-; CHECK-i64-NEXT: fcvtzs x9, d3
-; CHECK-i64-NEXT: fcvtzs x10, d4
-; CHECK-i64-NEXT: fcvtzs d3, d5
-; CHECK-i64-NEXT: fcvtzs d1, d6
-; CHECK-i64-NEXT: fcvtzs x11, d7
-; CHECK-i64-NEXT: mov v0.d[1], x10
-; CHECK-i64-NEXT: mov v2.d[1], x11
-; CHECK-i64-NEXT: mov v1.d[1], x9
-; CHECK-i64-NEXT: mov v3.d[1], x8
+; CHECK-i64-NEXT: fcvtzs z2.d, p0/m, z2.d
+; CHECK-i64-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-i64-NEXT: movprfx z1, z0
+; CHECK-i64-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-i64-NEXT: movprfx z3, z2
+; CHECK-i64-NEXT: ext z3.b, z3.b, z2.b, #16
+; CHECK-i64-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-i64-NEXT: // kill: def $q2 killed $q2 killed $z2
+; CHECK-i64-NEXT: // kill: def $q1 killed $q1 killed $z1
+; CHECK-i64-NEXT: // kill: def $q3 killed $q3 killed $z3
; CHECK-i64-NEXT: ret
%a = call <8 x iXLen> @llvm.lrint.v8iXLen.v8f64(<8 x double> %x)
ret <8 x iXLen> %a
@@ -1133,70 +670,46 @@ declare <8 x iXLen> @llvm.lrint.v8iXLen.v8f64(<8 x double>)
define <16 x iXLen> @lrint_v16f64(<16 x double> %x) nounwind {
; CHECK-i32-LABEL: lrint_v16f64:
; CHECK-i32: // %bb.0:
-; CHECK-i32-NEXT: ptrue p1.d, vl2
-; CHECK-i32-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-i32-NEXT: ptrue p0.d, vl2
; CHECK-i32-NEXT: // kill: def $q6 killed $q6 def $z6
; CHECK-i32-NEXT: // kill: def $q4 killed $q4 def $z4
; CHECK-i32-NEXT: // kill: def $q2 killed $q2 def $z2
-; CHECK-i32-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-i32-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-i32-NEXT: // kill: def $q7 killed $q7 def $z7
; CHECK-i32-NEXT: // kill: def $q5 killed $q5 def $z5
; CHECK-i32-NEXT: // kill: def $q3 killed $q3 def $z3
+; CHECK-i32-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-i32-NEXT: splice z0.d, p0, z0.d, z1.d
+; CHECK-i32-NEXT: splice z6.d, p0, z6.d, z7.d
+; CHECK-i32-NEXT: splice z4.d, p0, z4.d, z5.d
+; CHECK-i32-NEXT: splice z2.d, p0, z2.d, z3.d
; CHECK-i32-NEXT: ptrue p0.d, vl4
-; CHECK-i32-NEXT: splice z0.d, p1, z0.d, z1.d
-; CHECK-i32-NEXT: splice z2.d, p1, z2.d, z3.d
-; CHECK-i32-NEXT: splice z4.d, p1, z4.d, z5.d
-; CHECK-i32-NEXT: splice z6.d, p1, z6.d, z7.d
-; CHECK-i32-NEXT: movprfx z5, z0
-; CHECK-i32-NEXT: frintx z5.d, p0/m, z0.d
-; CHECK-i32-NEXT: movprfx z7, z2
-; CHECK-i32-NEXT: frintx z7.d, p0/m, z2.d
+; CHECK-i32-NEXT: mov z1.d, #0x7fffffff
+; CHECK-i32-NEXT: mov z3.d, #0xffffffff80000000
+; CHECK-i32-NEXT: frintx z0.d, p0/m, z0.d
; CHECK-i32-NEXT: frintx z4.d, p0/m, z4.d
; CHECK-i32-NEXT: frintx z6.d, p0/m, z6.d
-; CHECK-i32-NEXT: fcvtzs w8, d5
-; CHECK-i32-NEXT: mov z0.d, z5.d[1]
-; CHECK-i32-NEXT: mov z1.d, z7.d[1]
-; CHECK-i32-NEXT: fcvtzs w9, d7
-; CHECK-i32-NEXT: mov z3.d, z4.d[1]
-; CHECK-i32-NEXT: fcvtzs w10, d4
-; CHECK-i32-NEXT: mov z16.d, z6.d[1]
-; CHECK-i32-NEXT: fcvtzs w12, d6
-; CHECK-i32-NEXT: mov z2.d, z5.d[2]
-; CHECK-i32-NEXT: fcvtzs w11, d0
-; CHECK-i32-NEXT: fcvtzs w13, d1
-; CHECK-i32-NEXT: mov z17.d, z7.d[2]
-; CHECK-i32-NEXT: fcvtzs w14, d3
-; CHECK-i32-NEXT: fmov s0, w8
-; CHECK-i32-NEXT: mov z18.d, z4.d[2]
-; CHECK-i32-NEXT: fcvtzs w8, d16
-; CHECK-i32-NEXT: mov z19.d, z6.d[2]
-; CHECK-i32-NEXT: fcvtzs w15, d2
-; CHECK-i32-NEXT: fmov s1, w9
-; CHECK-i32-NEXT: fmov s2, w10
-; CHECK-i32-NEXT: fmov s3, w12
-; CHECK-i32-NEXT: fcvtzs w9, d17
-; CHECK-i32-NEXT: fcvtzs w10, d18
-; CHECK-i32-NEXT: mov v0.s[1], w11
-; CHECK-i32-NEXT: fcvtzs w11, d19
-; CHECK-i32-NEXT: mov z5.d, z5.d[3]
-; CHECK-i32-NEXT: mov z7.d, z7.d[3]
-; CHECK-i32-NEXT: mov v1.s[1], w13
-; CHECK-i32-NEXT: mov v2.s[1], w14
-; CHECK-i32-NEXT: mov v3.s[1], w8
-; CHECK-i32-NEXT: mov z4.d, z4.d[3]
-; CHECK-i32-NEXT: mov z6.d, z6.d[3]
-; CHECK-i32-NEXT: mov v0.s[2], w15
-; CHECK-i32-NEXT: fcvtzs w8, d5
-; CHECK-i32-NEXT: mov v1.s[2], w9
-; CHECK-i32-NEXT: fcvtzs w9, d7
-; CHECK-i32-NEXT: mov v2.s[2], w10
-; CHECK-i32-NEXT: fcvtzs w10, d4
-; CHECK-i32-NEXT: mov v3.s[2], w11
-; CHECK-i32-NEXT: fcvtzs w11, d6
-; CHECK-i32-NEXT: mov v0.s[3], w8
-; CHECK-i32-NEXT: mov v1.s[3], w9
-; CHECK-i32-NEXT: mov v2.s[3], w10
-; CHECK-i32-NEXT: mov v3.s[3], w11
+; CHECK-i32-NEXT: frintx z2.d, p0/m, z2.d
+; CHECK-i32-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-i32-NEXT: fcvtzs z4.d, p0/m, z4.d
+; CHECK-i32-NEXT: fcvtzs z6.d, p0/m, z6.d
+; CHECK-i32-NEXT: fcvtzs z2.d, p0/m, z2.d
+; CHECK-i32-NEXT: smin z0.d, p0/m, z0.d, z1.d
+; CHECK-i32-NEXT: smin z4.d, p0/m, z4.d, z1.d
+; CHECK-i32-NEXT: smin z2.d, p0/m, z2.d, z1.d
+; CHECK-i32-NEXT: smin z1.d, p0/m, z1.d, z6.d
+; CHECK-i32-NEXT: smax z0.d, p0/m, z0.d, z3.d
+; CHECK-i32-NEXT: smax z4.d, p0/m, z4.d, z3.d
+; CHECK-i32-NEXT: smax z2.d, p0/m, z2.d, z3.d
+; CHECK-i32-NEXT: smax z3.d, p0/m, z3.d, z1.d
+; CHECK-i32-NEXT: uzp1 z0.s, z0.s, z0.s
+; CHECK-i32-NEXT: uzp1 z1.s, z2.s, z2.s
+; CHECK-i32-NEXT: uzp1 z2.s, z4.s, z4.s
+; CHECK-i32-NEXT: uzp1 z3.s, z3.s, z3.s
+; CHECK-i32-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-i32-NEXT: // kill: def $q1 killed $q1 killed $z1
+; CHECK-i32-NEXT: // kill: def $q2 killed $q2 killed $z2
+; CHECK-i32-NEXT: // kill: def $q3 killed $q3 killed $z3
; CHECK-i32-NEXT: ret
;
; CHECK-i64-LABEL: lrint_v16f64:
@@ -1205,56 +718,40 @@ define <16 x iXLen> @lrint_v16f64(<16 x double> %x) nounwind {
; CHECK-i64-NEXT: // kill: def $q6 killed $q6 def $z6
; CHECK-i64-NEXT: // kill: def $q4 killed $q4 def $z4
; CHECK-i64-NEXT: // kill: def $q2 killed $q2 def $z2
+; CHECK-i64-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-i64-NEXT: // kill: def $q7 killed $q7 def $z7
; CHECK-i64-NEXT: // kill: def $q5 killed $q5 def $z5
; CHECK-i64-NEXT: // kill: def $q3 killed $q3 def $z3
-; CHECK-i64-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-i64-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-i64-NEXT: splice z6.d, p0, z6.d, z7.d
+; CHECK-i64-NEXT: splice z0.d, p0, z0.d, z1.d
; CHECK-i64-NEXT: splice z2.d, p0, z2.d, z3.d
; CHECK-i64-NEXT: splice z4.d, p0, z4.d, z5.d
-; CHECK-i64-NEXT: splice z0.d, p0, z0.d, z1.d
+; CHECK-i64-NEXT: splice z6.d, p0, z6.d, z7.d
; CHECK-i64-NEXT: ptrue p0.d, vl4
-; CHECK-i64-NEXT: frintx z6.d, p0/m, z6.d
-; CHECK-i64-NEXT: frintx z4.d, p0/m, z4.d
; CHECK-i64-NEXT: frintx z2.d, p0/m, z2.d
; CHECK-i64-NEXT: frintx z0.d, p0/m, z0.d
-; CHECK-i64-NEXT: mov z1.d, z6.d[3]
-; CHECK-i64-NEXT: mov z3.d, z4.d[3]
-; CHECK-i64-NEXT: mov z5.d, z2.d[3]
-; CHECK-i64-NEXT: mov z16.d, z4.d[1]
-; CHECK-i64-NEXT: mov z7.d, z0.d[3]
-; CHECK-i64-NEXT: mov z17.d, z0.d[2]
-; CHECK-i64-NEXT: mov z18.d, z4.d[2]
-; CHECK-i64-NEXT: mov z19.d, z6.d[1]
-; CHECK-i64-NEXT: fcvtzs d4, d4
-; CHECK-i64-NEXT: fcvtzs x8, d1
-; CHECK-i64-NEXT: mov z1.d, z2.d[1]
-; CHECK-i64-NEXT: fcvtzs x9, d3
-; CHECK-i64-NEXT: mov z3.d, z0.d[1]
-; CHECK-i64-NEXT: fcvtzs x10, d5
-; CHECK-i64-NEXT: mov z5.d, z6.d[2]
-; CHECK-i64-NEXT: fcvtzs x12, d16
-; CHECK-i64-NEXT: mov z16.d, z2.d[2]
-; CHECK-i64-NEXT: fcvtzs x11, d7
-; CHECK-i64-NEXT: fcvtzs x13, d1
-; CHECK-i64-NEXT: fcvtzs d1, d17
-; CHECK-i64-NEXT: fcvtzs d0, d0
-; CHECK-i64-NEXT: fcvtzs x14, d3
-; CHECK-i64-NEXT: fcvtzs d7, d5
-; CHECK-i64-NEXT: fcvtzs d2, d2
-; CHECK-i64-NEXT: fcvtzs d3, d16
-; CHECK-i64-NEXT: fcvtzs d5, d18
-; CHECK-i64-NEXT: fcvtzs x15, d19
-; CHECK-i64-NEXT: fcvtzs d6, d6
-; CHECK-i64-NEXT: mov v4.d[1], x12
-; CHECK-i64-NEXT: mov v1.d[1], x11
-; CHECK-i64-NEXT: mov v0.d[1], x14
-; CHECK-i64-NEXT: mov v2.d[1], x13
-; CHECK-i64-NEXT: mov v7.d[1], x8
-; CHECK-i64-NEXT: mov v3.d[1], x10
-; CHECK-i64-NEXT: mov v5.d[1], x9
-; CHECK-i64-NEXT: mov v6.d[1], x15
+; CHECK-i64-NEXT: frintx z4.d, p0/m, z4.d
+; CHECK-i64-NEXT: frintx z6.d, p0/m, z6.d
+; CHECK-i64-NEXT: fcvtzs z2.d, p0/m, z2.d
+; CHECK-i64-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-i64-NEXT: fcvtzs z4.d, p0/m, z4.d
+; CHECK-i64-NEXT: fcvtzs z6.d, p0/m, z6.d
+; CHECK-i64-NEXT: movprfx z1, z0
+; CHECK-i64-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-i64-NEXT: movprfx z3, z2
+; CHECK-i64-NEXT: ext z3.b, z3.b, z2.b, #16
+; CHECK-i64-NEXT: movprfx z5, z4
+; CHECK-i64-NEXT: ext z5.b, z5.b, z4.b, #16
+; CHECK-i64-NEXT: movprfx z7, z6
+; CHECK-i64-NEXT: ext z7.b, z7.b, z6.b, #16
+; CHECK-i64-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-i64-NEXT: // kill: def $q2 killed $q2 killed $z2
+; CHECK-i64-NEXT: // kill: def $q4 killed $q4 killed $z4
+; CHECK-i64-NEXT: // kill: def $q6 killed $q6 killed $z6
+; CHECK-i64-NEXT: // kill: def $q1 killed $q1 killed $z1
+; CHECK-i64-NEXT: // kill: def $q3 killed $q3 killed $z3
+; CHECK-i64-NEXT: // kill: def $q5 killed $q5 killed $z5
+; CHECK-i64-NEXT: // kill: def $q7 killed $q7 killed $z7
; CHECK-i64-NEXT: ret
%a = call <16 x iXLen> @llvm.lrint.v16iXLen.v16f64(<16 x double> %x)
ret <16 x iXLen> %a
@@ -1264,276 +761,137 @@ declare <16 x iXLen> @llvm.lrint.v16iXLen.v16f64(<16 x double>)
define <32 x iXLen> @lrint_v32f64(<32 x double> %x) nounwind {
; CHECK-i32-LABEL: lrint_v32f64:
; CHECK-i32: // %bb.0:
-; CHECK-i32-NEXT: ptrue p1.d, vl2
-; CHECK-i32-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-i32-NEXT: ldp q16, q17, [sp, #96]
+; CHECK-i32-NEXT: ptrue p0.d, vl2
+; CHECK-i32-NEXT: // kill: def $q3 killed $q3 def $z3
; CHECK-i32-NEXT: // kill: def $q2 killed $q2 def $z2
; CHECK-i32-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-i32-NEXT: // kill: def $q3 killed $q3 def $z3
+; CHECK-i32-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-i32-NEXT: ldp q20, q19, [sp]
+; CHECK-i32-NEXT: // kill: def $q6 killed $q6 def $z6
; CHECK-i32-NEXT: // kill: def $q4 killed $q4 def $z4
; CHECK-i32-NEXT: // kill: def $q7 killed $q7 def $z7
-; CHECK-i32-NEXT: // kill: def $q6 killed $q6 def $z6
; CHECK-i32-NEXT: // kill: def $q5 killed $q5 def $z5
+; CHECK-i32-NEXT: splice z2.d, p0, z2.d, z3.d
+; CHECK-i32-NEXT: splice z0.d, p0, z0.d, z1.d
+; CHECK-i32-NEXT: splice z6.d, p0, z6.d, z7.d
+; CHECK-i32-NEXT: splice z16.d, p0, z16.d, z17.d
+; CHECK-i32-NEXT: ldp q17, q18, [sp, #64]
+; CHECK-i32-NEXT: ldp q3, q1, [sp, #32]
+; CHECK-i32-NEXT: splice z20.d, p0, z20.d, z19.d
+; CHECK-i32-NEXT: splice z4.d, p0, z4.d, z5.d
+; CHECK-i32-NEXT: mov z5.d, #0xffffffff80000000
+; CHECK-i32-NEXT: splice z17.d, p0, z17.d, z18.d
+; CHECK-i32-NEXT: splice z3.d, p0, z3.d, z1.d
; CHECK-i32-NEXT: ptrue p0.d, vl4
-; CHECK-i32-NEXT: splice z0.d, p1, z0.d, z1.d
-; CHECK-i32-NEXT: splice z2.d, p1, z2.d, z3.d
-; CHECK-i32-NEXT: splice z4.d, p1, z4.d, z5.d
-; CHECK-i32-NEXT: ldp q1, q3, [sp]
-; CHECK-i32-NEXT: splice z6.d, p1, z6.d, z7.d
+; CHECK-i32-NEXT: mov z1.d, #0x7fffffff
; CHECK-i32-NEXT: frintx z0.d, p0/m, z0.d
-; CHECK-i32-NEXT: movprfx z18, z2
-; CHECK-i32-NEXT: frintx z18.d, p0/m, z2.d
-; CHECK-i32-NEXT: splice z1.d, p1, z1.d, z3.d
-; CHECK-i32-NEXT: ldp q5, q3, [sp, #96]
+; CHECK-i32-NEXT: frintx z2.d, p0/m, z2.d
; CHECK-i32-NEXT: frintx z4.d, p0/m, z4.d
-; CHECK-i32-NEXT: ldp q2, q7, [sp, #64]
-; CHECK-i32-NEXT: movprfx z16, z6
-; CHECK-i32-NEXT: frintx z16.d, p0/m, z6.d
-; CHECK-i32-NEXT: mov z19.d, z0.d[1]
-; CHECK-i32-NEXT: fcvtzs w8, d0
-; CHECK-i32-NEXT: splice z5.d, p1, z5.d, z3.d
-; CHECK-i32-NEXT: splice z2.d, p1, z2.d, z7.d
-; CHECK-i32-NEXT: ldp q3, q7, [sp, #32]
-; CHECK-i32-NEXT: mov z20.d, z18.d[1]
-; CHECK-i32-NEXT: fcvtzs w9, d18
-; CHECK-i32-NEXT: movprfx z17, z1
-; CHECK-i32-NEXT: frintx z17.d, p0/m, z1.d
-; CHECK-i32-NEXT: mov z1.d, z0.d[2]
-; CHECK-i32-NEXT: fcvtzs w10, d19
-; CHECK-i32-NEXT: mov z6.d, z18.d[2]
-; CHECK-i32-NEXT: splice z3.d, p1, z3.d, z7.d
-; CHECK-i32-NEXT: mov z7.d, z0.d[3]
-; CHECK-i32-NEXT: fmov s0, w8
-; CHECK-i32-NEXT: fcvtzs w11, d20
-; CHECK-i32-NEXT: mov z20.d, z18.d[3]
-; CHECK-i32-NEXT: mov z18.d, z4.d[1]
-; CHECK-i32-NEXT: fcvtzs w12, d4
-; CHECK-i32-NEXT: mov z21.d, z4.d[2]
-; CHECK-i32-NEXT: fcvtzs w13, d1
-; CHECK-i32-NEXT: fmov s1, w9
-; CHECK-i32-NEXT: mov v0.s[1], w10
-; CHECK-i32-NEXT: movprfx z19, z2
-; CHECK-i32-NEXT: frintx z19.d, p0/m, z2.d
-; CHECK-i32-NEXT: fcvtzs w15, d18
-; CHECK-i32-NEXT: movprfx z18, z3
-; CHECK-i32-NEXT: frintx z18.d, p0/m, z3.d
-; CHECK-i32-NEXT: mov z3.d, z4.d[3]
-; CHECK-i32-NEXT: fcvtzs w16, d16
-; CHECK-i32-NEXT: mov z4.d, z16.d[1]
-; CHECK-i32-NEXT: fcvtzs w14, d6
-; CHECK-i32-NEXT: mov v1.s[1], w11
-; CHECK-i32-NEXT: fcvtzs w11, d21
-; CHECK-i32-NEXT: movprfx z21, z5
-; CHECK-i32-NEXT: frintx z21.d, p0/m, z5.d
-; CHECK-i32-NEXT: fcvtzs w8, d7
-; CHECK-i32-NEXT: fmov s2, w12
-; CHECK-i32-NEXT: mov z7.d, z17.d[1]
-; CHECK-i32-NEXT: mov z6.d, z16.d[2]
-; CHECK-i32-NEXT: mov v0.s[2], w13
-; CHECK-i32-NEXT: fcvtzs w12, d4
-; CHECK-i32-NEXT: fcvtzs w13, d17
-; CHECK-i32-NEXT: fcvtzs w10, d3
-; CHECK-i32-NEXT: fmov s3, w16
-; CHECK-i32-NEXT: mov v2.s[1], w15
-; CHECK-i32-NEXT: mov z4.d, z18.d[1]
-; CHECK-i32-NEXT: fcvtzs w15, d7
-; CHECK-i32-NEXT: mov z5.d, z19.d[1]
-; CHECK-i32-NEXT: fcvtzs w17, d18
-; CHECK-i32-NEXT: fcvtzs w0, d19
-; CHECK-i32-NEXT: mov z7.d, z21.d[1]
-; CHECK-i32-NEXT: fcvtzs w2, d21
-; CHECK-i32-NEXT: fcvtzs w9, d20
-; CHECK-i32-NEXT: mov v1.s[2], w14
-; CHECK-i32-NEXT: mov z20.d, z17.d[2]
-; CHECK-i32-NEXT: fcvtzs w14, d6
-; CHECK-i32-NEXT: mov z6.d, z18.d[2]
-; CHECK-i32-NEXT: fcvtzs w18, d4
-; CHECK-i32-NEXT: fmov s4, w13
-; CHECK-i32-NEXT: fcvtzs w13, d5
-; CHECK-i32-NEXT: mov v3.s[1], w12
-; CHECK-i32-NEXT: fcvtzs w12, d7
-; CHECK-i32-NEXT: fcvtzs w16, d20
-; CHECK-i32-NEXT: mov z20.d, z19.d[2]
-; CHECK-i32-NEXT: mov z22.d, z21.d[2]
-; CHECK-i32-NEXT: fcvtzs w1, d6
-; CHECK-i32-NEXT: fmov s5, w17
-; CHECK-i32-NEXT: fmov s6, w0
-; CHECK-i32-NEXT: fmov s7, w2
-; CHECK-i32-NEXT: mov v4.s[1], w15
-; CHECK-i32-NEXT: mov z16.d, z16.d[3]
-; CHECK-i32-NEXT: fcvtzs w15, d20
-; CHECK-i32-NEXT: mov z17.d, z17.d[3]
-; CHECK-i32-NEXT: mov z18.d, z18.d[3]
-; CHECK-i32-NEXT: mov v5.s[1], w18
-; CHECK-i32-NEXT: mov v6.s[1], w13
-; CHECK-i32-NEXT: fcvtzs w13, d22
-; CHECK-i32-NEXT: mov v7.s[1], w12
-; CHECK-i32-NEXT: mov z19.d, z19.d[3]
-; CHECK-i32-NEXT: mov z20.d, z21.d[3]
-; CHECK-i32-NEXT: mov v2.s[2], w11
-; CHECK-i32-NEXT: mov v3.s[2], w14
-; CHECK-i32-NEXT: fcvtzs w11, d16
-; CHECK-i32-NEXT: mov v4.s[2], w16
-; CHECK-i32-NEXT: fcvtzs w12, d17
-; CHECK-i32-NEXT: fcvtzs w14, d18
-; CHECK-i32-NEXT: mov v5.s[2], w1
-; CHECK-i32-NEXT: mov v6.s[2], w15
-; CHECK-i32-NEXT: fcvtzs w15, d19
-; CHECK-i32-NEXT: mov v7.s[2], w13
-; CHECK-i32-NEXT: fcvtzs w13, d20
-; CHECK-i32-NEXT: mov v0.s[3], w8
-; CHECK-i32-NEXT: mov v1.s[3], w9
-; CHECK-i32-NEXT: mov v2.s[3], w10
-; CHECK-i32-NEXT: mov v3.s[3], w11
-; CHECK-i32-NEXT: mov v4.s[3], w12
-; CHECK-i32-NEXT: mov v5.s[3], w14
-; CHECK-i32-NEXT: mov v6.s[3], w15
-; CHECK-i32-NEXT: mov v7.s[3], w13
+; CHECK-i32-NEXT: frintx z6.d, p0/m, z6.d
+; CHECK-i32-NEXT: frintx z20.d, p0/m, z20.d
+; CHECK-i32-NEXT: frintx z17.d, p0/m, z17.d
+; CHECK-i32-NEXT: frintx z3.d, p0/m, z3.d
+; CHECK-i32-NEXT: frintx z16.d, p0/m, z16.d
+; CHECK-i32-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-i32-NEXT: fcvtzs z2.d, p0/m, z2.d
+; CHECK-i32-NEXT: fcvtzs z4.d, p0/m, z4.d
+; CHECK-i32-NEXT: fcvtzs z6.d, p0/m, z6.d
+; CHECK-i32-NEXT: fcvtzs z20.d, p0/m, z20.d
+; CHECK-i32-NEXT: fcvtzs z17.d, p0/m, z17.d
+; CHECK-i32-NEXT: fcvtzs z3.d, p0/m, z3.d
+; CHECK-i32-NEXT: fcvtzs z16.d, p0/m, z16.d
+; CHECK-i32-NEXT: smin z0.d, p0/m, z0.d, z1.d
+; CHECK-i32-NEXT: smin z2.d, p0/m, z2.d, z1.d
+; CHECK-i32-NEXT: smin z4.d, p0/m, z4.d, z1.d
+; CHECK-i32-NEXT: smin z6.d, p0/m, z6.d, z1.d
+; CHECK-i32-NEXT: smin z20.d, p0/m, z20.d, z1.d
+; CHECK-i32-NEXT: smin z17.d, p0/m, z17.d, z1.d
+; CHECK-i32-NEXT: smin z3.d, p0/m, z3.d, z1.d
+; CHECK-i32-NEXT: smin z1.d, p0/m, z1.d, z16.d
+; CHECK-i32-NEXT: smax z0.d, p0/m, z0.d, z5.d
+; CHECK-i32-NEXT: smax z2.d, p0/m, z2.d, z5.d
+; CHECK-i32-NEXT: smax z4.d, p0/m, z4.d, z5.d
+; CHECK-i32-NEXT: smax z6.d, p0/m, z6.d, z5.d
+; CHECK-i32-NEXT: smax z20.d, p0/m, z20.d, z5.d
+; CHECK-i32-NEXT: smax z17.d, p0/m, z17.d, z5.d
+; CHECK-i32-NEXT: movprfx z7, z3
+; CHECK-i32-NEXT: smax z7.d, p0/m, z7.d, z5.d
+; CHECK-i32-NEXT: movprfx z16, z1
+; CHECK-i32-NEXT: smax z16.d, p0/m, z16.d, z5.d
+; CHECK-i32-NEXT: uzp1 z0.s, z0.s, z0.s
+; CHECK-i32-NEXT: uzp1 z1.s, z2.s, z2.s
+; CHECK-i32-NEXT: uzp1 z2.s, z4.s, z4.s
+; CHECK-i32-NEXT: uzp1 z3.s, z6.s, z6.s
+; CHECK-i32-NEXT: uzp1 z4.s, z20.s, z20.s
+; CHECK-i32-NEXT: uzp1 z6.s, z17.s, z17.s
+; CHECK-i32-NEXT: uzp1 z5.s, z7.s, z7.s
+; CHECK-i32-NEXT: uzp1 z7.s, z16.s, z16.s
+; CHECK-i32-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-i32-NEXT: // kill: def $q1 killed $q1 killed $z1
+; CHECK-i32-NEXT: // kill: def $q2 killed $q2 killed $z2
+; CHECK-i32-NEXT: // kill: def $q3 killed $q3 killed $z3
+; CHECK-i32-NEXT: // kill: def $q4 killed $q4 killed $z4
+; CHECK-i32-NEXT: // kill: def $q6 killed $q6 killed $z6
+; CHECK-i32-NEXT: // kill: def $q5 killed $q5 killed $z5
+; CHECK-i32-NEXT: // kill: def $q7 killed $q7 killed $z7
; CHECK-i32-NEXT: ret
;
; CHECK-i64-LABEL: lrint_v32f64:
; CHECK-i64: // %bb.0:
-; CHECK-i64-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
-; CHECK-i64-NEXT: sub x9, sp, #272
-; CHECK-i64-NEXT: mov x29, sp
-; CHECK-i64-NEXT: and sp, x9, #0xffffffffffffffe0
-; CHECK-i64-NEXT: ptrue p1.d, vl2
-; CHECK-i64-NEXT: // kill: def $q0 killed $q0 def $z0
-; CHECK-i64-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-i64-NEXT: // kill: def $q3 killed $q3 def $z3
-; CHECK-i64-NEXT: // kill: def $q2 killed $q2 def $z2
-; CHECK-i64-NEXT: // kill: def $q7 killed $q7 def $z7
+; CHECK-i64-NEXT: ldp q17, q16, [sp, #96]
+; CHECK-i64-NEXT: ptrue p0.d, vl2
+; CHECK-i64-NEXT: ldp q19, q18, [sp, #64]
+; CHECK-i64-NEXT: ptrue p1.d, vl4
; CHECK-i64-NEXT: // kill: def $q6 killed $q6 def $z6
+; CHECK-i64-NEXT: // kill: def $q7 killed $q7 def $z7
; CHECK-i64-NEXT: // kill: def $q4 killed $q4 def $z4
; CHECK-i64-NEXT: // kill: def $q5 killed $q5 def $z5
-; CHECK-i64-NEXT: ptrue p0.d, vl4
-; CHECK-i64-NEXT: splice z0.d, p1, z0.d, z1.d
-; CHECK-i64-NEXT: splice z2.d, p1, z2.d, z3.d
-; CHECK-i64-NEXT: splice z4.d, p1, z4.d, z5.d
-; CHECK-i64-NEXT: splice z6.d, p1, z6.d, z7.d
-; CHECK-i64-NEXT: ldp q5, q19, [x29, #16]
-; CHECK-i64-NEXT: movprfx z3, z0
-; CHECK-i64-NEXT: frintx z3.d, p0/m, z0.d
-; CHECK-i64-NEXT: movprfx z16, z2
-; CHECK-i64-NEXT: frintx z16.d, p0/m, z2.d
-; CHECK-i64-NEXT: frintx z4.d, p0/m, z4.d
-; CHECK-i64-NEXT: splice z5.d, p1, z5.d, z19.d
-; CHECK-i64-NEXT: frintx z6.d, p0/m, z6.d
-; CHECK-i64-NEXT: ldp q2, q17, [x29, #48]
-; CHECK-i64-NEXT: ldp q0, q1, [x29, #112]
-; CHECK-i64-NEXT: mov z18.d, z3.d[3]
-; CHECK-i64-NEXT: mov z7.d, z3.d[2]
-; CHECK-i64-NEXT: fcvtzs x9, d3
-; CHECK-i64-NEXT: mov z3.d, z3.d[1]
-; CHECK-i64-NEXT: mov z20.d, z16.d[3]
-; CHECK-i64-NEXT: fcvtzs x12, d16
-; CHECK-i64-NEXT: splice z2.d, p1, z2.d, z17.d
-; CHECK-i64-NEXT: frintx z5.d, p0/m, z5.d
-; CHECK-i64-NEXT: splice z0.d, p1, z0.d, z1.d
-; CHECK-i64-NEXT: fcvtzs x10, d18
-; CHECK-i64-NEXT: fcvtzs x11, d7
-; CHECK-i64-NEXT: mov z18.d, z16.d[2]
-; CHECK-i64-NEXT: mov z7.d, z16.d[1]
-; CHECK-i64-NEXT: fcvtzs x13, d3
-; CHECK-i64-NEXT: str x9, [sp, #128]
-; CHECK-i64-NEXT: fcvtzs x9, d20
-; CHECK-i64-NEXT: mov z16.d, z4.d[3]
-; CHECK-i64-NEXT: ldp q3, q19, [x29, #80]
-; CHECK-i64-NEXT: frintx z2.d, p0/m, z2.d
-; CHECK-i64-NEXT: stp x11, x10, [sp, #144]
-; CHECK-i64-NEXT: fcvtzs x10, d18
-; CHECK-i64-NEXT: fcvtzs x11, d7
-; CHECK-i64-NEXT: mov z18.d, z4.d[2]
-; CHECK-i64-NEXT: mov z7.d, z4.d[1]
-; CHECK-i64-NEXT: str x13, [sp, #136]
-; CHECK-i64-NEXT: fcvtzs x13, d16
-; CHECK-i64-NEXT: mov z16.d, z6.d[3]
-; CHECK-i64-NEXT: splice z3.d, p1, z3.d, z19.d
-; CHECK-i64-NEXT: mov z1.d, z5.d[1]
-; CHECK-i64-NEXT: frintx z0.d, p0/m, z0.d
-; CHECK-i64-NEXT: stp x10, x9, [sp, #176]
-; CHECK-i64-NEXT: fcvtzs x9, d18
-; CHECK-i64-NEXT: fcvtzs x10, d4
-; CHECK-i64-NEXT: stp x12, x11, [sp, #160]
-; CHECK-i64-NEXT: fcvtzs x11, d7
-; CHECK-i64-NEXT: mov z4.d, z6.d[2]
-; CHECK-i64-NEXT: mov z7.d, z6.d[1]
-; CHECK-i64-NEXT: fcvtzs x12, d6
-; CHECK-i64-NEXT: mov z6.d, z5.d[2]
-; CHECK-i64-NEXT: frintx z3.d, p0/m, z3.d
-; CHECK-i64-NEXT: stp x9, x13, [sp, #208]
-; CHECK-i64-NEXT: fcvtzs x9, d16
-; CHECK-i64-NEXT: fcvtzs x13, d4
-; CHECK-i64-NEXT: stp x10, x11, [sp, #192]
-; CHECK-i64-NEXT: fcvtzs x10, d7
-; CHECK-i64-NEXT: mov z4.d, z5.d[3]
-; CHECK-i64-NEXT: fcvtzs x11, d4
-; CHECK-i64-NEXT: stp x13, x9, [sp, #240]
-; CHECK-i64-NEXT: fcvtzs x9, d6
-; CHECK-i64-NEXT: stp x12, x10, [sp, #224]
-; CHECK-i64-NEXT: fcvtzs x10, d5
-; CHECK-i64-NEXT: fcvtzs x12, d1
-; CHECK-i64-NEXT: mov z4.d, z2.d[3]
-; CHECK-i64-NEXT: mov z5.d, z2.d[2]
-; CHECK-i64-NEXT: mov z1.d, z2.d[1]
-; CHECK-i64-NEXT: fcvtzs x13, d2
-; CHECK-i64-NEXT: mov z2.d, z3.d[2]
-; CHECK-i64-NEXT: stp x9, x11, [sp, #16]
-; CHECK-i64-NEXT: fcvtzs x9, d4
-; CHECK-i64-NEXT: fcvtzs x11, d5
-; CHECK-i64-NEXT: stp x10, x12, [sp]
-; CHECK-i64-NEXT: fcvtzs x10, d1
-; CHECK-i64-NEXT: mov z4.d, z3.d[3]
-; CHECK-i64-NEXT: mov z1.d, z3.d[1]
-; CHECK-i64-NEXT: fcvtzs x12, d4
-; CHECK-i64-NEXT: stp x11, x9, [sp, #48]
-; CHECK-i64-NEXT: fcvtzs x9, d2
-; CHECK-i64-NEXT: fcvtzs x11, d3
-; CHECK-i64-NEXT: stp x13, x10, [sp, #32]
-; CHECK-i64-NEXT: fcvtzs x10, d1
-; CHECK-i64-NEXT: mov z2.d, z0.d[3]
-; CHECK-i64-NEXT: mov z3.d, z0.d[2]
-; CHECK-i64-NEXT: mov z1.d, z0.d[1]
-; CHECK-i64-NEXT: stp x9, x12, [sp, #80]
-; CHECK-i64-NEXT: fcvtzs x12, d0
-; CHECK-i64-NEXT: fcvtzs x13, d2
-; CHECK-i64-NEXT: fcvtzs x9, d3
-; CHECK-i64-NEXT: stp x11, x10, [sp, #64]
-; CHECK-i64-NEXT: fcvtzs x10, d1
-; CHECK-i64-NEXT: stp x9, x13, [sp, #112]
-; CHECK-i64-NEXT: add x9, sp, #128
-; CHECK-i64-NEXT: stp x12, x10, [sp, #96]
-; CHECK-i64-NEXT: add x10, sp, #192
-; CHECK-i64-NEXT: ld1d { z0.d }, p0/z, [x9]
-; CHECK-i64-NEXT: add x9, sp, #160
-; CHECK-i64-NEXT: ld1d { z2.d }, p0/z, [x10]
-; CHECK-i64-NEXT: ld1d { z1.d }, p0/z, [x9]
-; CHECK-i64-NEXT: add x9, sp, #96
-; CHECK-i64-NEXT: add x10, sp, #224
-; CHECK-i64-NEXT: ld1d { z3.d }, p0/z, [x9]
-; CHECK-i64-NEXT: add x9, sp, #64
-; CHECK-i64-NEXT: ld1d { z4.d }, p0/z, [x10]
-; CHECK-i64-NEXT: add x10, sp, #32
-; CHECK-i64-NEXT: ld1d { z5.d }, p0/z, [x9]
-; CHECK-i64-NEXT: mov x9, sp
-; CHECK-i64-NEXT: ld1d { z6.d }, p0/z, [x10]
-; CHECK-i64-NEXT: mov x10, #28 // =0x1c
-; CHECK-i64-NEXT: ld1d { z7.d }, p0/z, [x9]
+; CHECK-i64-NEXT: // kill: def $q2 killed $q2 def $z2
+; CHECK-i64-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-i64-NEXT: // kill: def $q3 killed $q3 def $z3
+; CHECK-i64-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-i64-NEXT: mov x9, #28 // =0x1c
+; CHECK-i64-NEXT: splice z17.d, p0, z17.d, z16.d
+; CHECK-i64-NEXT: ldp q20, q16, [sp, #32]
+; CHECK-i64-NEXT: splice z19.d, p0, z19.d, z18.d
+; CHECK-i64-NEXT: ldp q21, q18, [sp]
+; CHECK-i64-NEXT: splice z6.d, p0, z6.d, z7.d
+; CHECK-i64-NEXT: splice z4.d, p0, z4.d, z5.d
+; CHECK-i64-NEXT: splice z2.d, p0, z2.d, z3.d
+; CHECK-i64-NEXT: splice z20.d, p0, z20.d, z16.d
+; CHECK-i64-NEXT: splice z0.d, p0, z0.d, z1.d
+; CHECK-i64-NEXT: splice z21.d, p0, z21.d, z18.d
+; CHECK-i64-NEXT: frintx z17.d, p1/m, z17.d
+; CHECK-i64-NEXT: frintx z19.d, p1/m, z19.d
+; CHECK-i64-NEXT: frintx z6.d, p1/m, z6.d
+; CHECK-i64-NEXT: frintx z4.d, p1/m, z4.d
+; CHECK-i64-NEXT: frintx z2.d, p1/m, z2.d
+; CHECK-i64-NEXT: frintx z20.d, p1/m, z20.d
+; CHECK-i64-NEXT: frintx z0.d, p1/m, z0.d
+; CHECK-i64-NEXT: frintx z21.d, p1/m, z21.d
+; CHECK-i64-NEXT: fcvtzs z17.d, p1/m, z17.d
+; CHECK-i64-NEXT: fcvtzs z19.d, p1/m, z19.d
+; CHECK-i64-NEXT: fcvtzs z6.d, p1/m, z6.d
+; CHECK-i64-NEXT: fcvtzs z4.d, p1/m, z4.d
+; CHECK-i64-NEXT: fcvtzs z2.d, p1/m, z2.d
+; CHECK-i64-NEXT: fcvtzs z20.d, p1/m, z20.d
+; CHECK-i64-NEXT: fcvtzs z0.d, p1/m, z0.d
+; CHECK-i64-NEXT: fcvtzs z21.d, p1/m, z21.d
+; CHECK-i64-NEXT: st1d { z17.d }, p1, [x8, x9, lsl #3]
; CHECK-i64-NEXT: mov x9, #24 // =0x18
-; CHECK-i64-NEXT: st1d { z3.d }, p0, [x8, x10, lsl #3]
-; CHECK-i64-NEXT: st1d { z5.d }, p0, [x8, x9, lsl #3]
+; CHECK-i64-NEXT: st1d { z19.d }, p1, [x8, x9, lsl #3]
; CHECK-i64-NEXT: mov x9, #20 // =0x14
-; CHECK-i64-NEXT: st1d { z6.d }, p0, [x8, x9, lsl #3]
+; CHECK-i64-NEXT: st1d { z20.d }, p1, [x8, x9, lsl #3]
; CHECK-i64-NEXT: mov x9, #16 // =0x10
-; CHECK-i64-NEXT: st1d { z7.d }, p0, [x8, x9, lsl #3]
+; CHECK-i64-NEXT: st1d { z21.d }, p1, [x8, x9, lsl #3]
; CHECK-i64-NEXT: mov x9, #12 // =0xc
-; CHECK-i64-NEXT: st1d { z4.d }, p0, [x8, x9, lsl #3]
+; CHECK-i64-NEXT: st1d { z6.d }, p1, [x8, x9, lsl #3]
; CHECK-i64-NEXT: mov x9, #8 // =0x8
-; CHECK-i64-NEXT: st1d { z2.d }, p0, [x8, x9, lsl #3]
+; CHECK-i64-NEXT: st1d { z4.d }, p1, [x8, x9, lsl #3]
; CHECK-i64-NEXT: mov x9, #4 // =0x4
-; CHECK-i64-NEXT: st1d { z1.d }, p0, [x8, x9, lsl #3]
-; CHECK-i64-NEXT: st1d { z0.d }, p0, [x8]
-; CHECK-i64-NEXT: mov sp, x29
-; CHECK-i64-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
+; CHECK-i64-NEXT: st1d { z2.d }, p1, [x8, x9, lsl #3]
+; CHECK-i64-NEXT: st1d { z0.d }, p1, [x8]
; CHECK-i64-NEXT: ret
%a = call <32 x iXLen> @llvm.lrint.v32iXLen.v16f64(<32 x double> %x)
ret <32 x iXLen> %a
diff --git a/llvm/test/CodeGen/AArch64/sve-fptosi-sat.ll b/llvm/test/CodeGen/AArch64/sve-fptosi-sat.ll
index e9db8434869bb..1091407030693 100644
--- a/llvm/test/CodeGen/AArch64/sve-fptosi-sat.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fptosi-sat.ll
@@ -14,19 +14,13 @@ declare <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f32.nxv4i64(<vscale x 4 x float>
define <vscale x 2 x i32> @test_signed_v2f32_v2i32(<vscale x 2 x float> %f) {
; CHECK-LABEL: test_signed_v2f32_v2i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-822083584 // =0xcf000000
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z1.s, w8
-; CHECK-NEXT: mov w8, #1325400063 // =0x4effffff
-; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z1.s
-; CHECK-NEXT: mov z1.d, #0xffffffff80000000
-; CHECK-NEXT: fcmgt p2.s, p0/z, z0.s, z2.s
-; CHECK-NEXT: mov z2.d, #0x7fffffff
-; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: fcvtzs z1.d, p1/m, z0.s
-; CHECK-NEXT: sel z0.d, p2, z2.d, z1.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: mov z1.d, #0x7fffffff
+; CHECK-NEXT: mov z2.d, #0xffffffff80000000
+; CHECK-NEXT: fcvt z0.d, p0/m, z0.s
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: smax z0.d, p0/m, z0.d, z2.d
; CHECK-NEXT: ret
%x = call <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f32.nxv2i32(<vscale x 2 x float> %f)
ret <vscale x 2 x i32> %x
@@ -35,19 +29,8 @@ define <vscale x 2 x i32> @test_signed_v2f32_v2i32(<vscale x 2 x float> %f) {
define <vscale x 4 x i32> @test_signed_v4f32_v4i32(<vscale x 4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-822083584 // =0xcf000000
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: mov z1.s, w8
-; CHECK-NEXT: mov w8, #1325400063 // =0x4effffff
-; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z1.s
-; CHECK-NEXT: mov z1.s, #0x80000000
-; CHECK-NEXT: fcmgt p2.s, p0/z, z0.s, z2.s
-; CHECK-NEXT: mov z2.s, #0x7fffffff
-; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: fcvtzs z1.s, p1/m, z0.s
-; CHECK-NEXT: sel z0.s, p2, z2.s, z1.s
-; CHECK-NEXT: mov z0.s, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
; CHECK-NEXT: ret
%x = call <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f32.nxv4i32(<vscale x 4 x float> %f)
ret <vscale x 4 x i32> %x
@@ -56,26 +39,9 @@ define <vscale x 4 x i32> @test_signed_v4f32_v4i32(<vscale x 4 x float> %f) {
define <vscale x 8 x i32> @test_signed_v8f32_v8i32(<vscale x 8 x float> %f) {
; CHECK-LABEL: test_signed_v8f32_v8i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-822083584 // =0xcf000000
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: mov z3.s, #0x80000000
-; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: mov w8, #1325400063 // =0x4effffff
-; CHECK-NEXT: mov z4.s, #0x80000000
-; CHECK-NEXT: mov z5.s, w8
-; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z2.s
-; CHECK-NEXT: fcmge p2.s, p0/z, z1.s, z2.s
-; CHECK-NEXT: mov z2.s, #0x7fffffff
-; CHECK-NEXT: fcmgt p3.s, p0/z, z1.s, z5.s
-; CHECK-NEXT: fcvtzs z3.s, p1/m, z0.s
-; CHECK-NEXT: fcmgt p1.s, p0/z, z0.s, z5.s
-; CHECK-NEXT: fcvtzs z4.s, p2/m, z1.s
-; CHECK-NEXT: fcmuo p2.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: fcmuo p0.s, p0/z, z1.s, z1.s
-; CHECK-NEXT: sel z0.s, p1, z2.s, z3.s
-; CHECK-NEXT: sel z1.s, p3, z2.s, z4.s
-; CHECK-NEXT: mov z0.s, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z1.s, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-NEXT: fcvtzs z1.s, p0/m, z1.s
; CHECK-NEXT: ret
%x = call <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f32.nxv8i32(<vscale x 8 x float> %f)
ret <vscale x 8 x i32> %x
@@ -84,18 +50,12 @@ define <vscale x 8 x i32> @test_signed_v8f32_v8i32(<vscale x 8 x float> %f) {
define <vscale x 4 x i16> @test_signed_v4f32_v4i16(<vscale x 4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-956301312 // =0xc7000000
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: mov z1.s, w8
-; CHECK-NEXT: mov w8, #65024 // =0xfe00
-; CHECK-NEXT: movk w8, #18175, lsl #16
-; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: fmaxnm z1.s, p0/m, z1.s, z0.s
-; CHECK-NEXT: fminnm z1.s, p0/m, z1.s, z2.s
-; CHECK-NEXT: fcvtzs z1.s, p0/m, z1.s
-; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: mov z1.s, p0/m, #0 // =0x0
-; CHECK-NEXT: mov z0.d, z1.d
+; CHECK-NEXT: mov z1.s, #32767 // =0x7fff
+; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT: mov z1.s, #-32768 // =0xffffffffffff8000
+; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT: ret
%x = call <vscale x 4 x i16> @llvm.fptosi.sat.nxv4f32.nxv4i16(<vscale x 4 x float> %f)
ret <vscale x 4 x i16> %x
@@ -104,24 +64,16 @@ define <vscale x 4 x i16> @test_signed_v4f32_v4i16(<vscale x 4 x float> %f) {
define <vscale x 8 x i16> @test_signed_v8f32_v8i16(<vscale x 8 x float> %f) {
; CHECK-LABEL: test_signed_v8f32_v8i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-956301312 // =0xc7000000
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: mov w8, #65024 // =0xfe00
-; CHECK-NEXT: movk w8, #18175, lsl #16
-; CHECK-NEXT: mov z4.s, w8
-; CHECK-NEXT: movprfx z3, z1
-; CHECK-NEXT: fmaxnm z3.s, p0/m, z3.s, z2.s
-; CHECK-NEXT: fmaxnm z2.s, p0/m, z2.s, z0.s
-; CHECK-NEXT: fcmuo p1.s, p0/z, z1.s, z1.s
-; CHECK-NEXT: fminnm z3.s, p0/m, z3.s, z4.s
-; CHECK-NEXT: fminnm z2.s, p0/m, z2.s, z4.s
-; CHECK-NEXT: fcvtzs z3.s, p0/m, z3.s
-; CHECK-NEXT: fcvtzs z2.s, p0/m, z2.s
-; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: mov z3.s, p1/m, #0 // =0x0
-; CHECK-NEXT: mov z2.s, p0/m, #0 // =0x0
-; CHECK-NEXT: uzp1 z0.h, z2.h, z3.h
+; CHECK-NEXT: mov z2.s, #32767 // =0x7fff
+; CHECK-NEXT: mov z3.s, #-32768 // =0xffffffffffff8000
+; CHECK-NEXT: fcvtzs z1.s, p0/m, z1.s
+; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-NEXT: smin z1.s, p0/m, z1.s, z2.s
+; CHECK-NEXT: smin z0.s, p0/m, z0.s, z2.s
+; CHECK-NEXT: smax z1.s, p0/m, z1.s, z3.s
+; CHECK-NEXT: smax z0.s, p0/m, z0.s, z3.s
+; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h
; CHECK-NEXT: ret
%x = call <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f32.nxv8i16(<vscale x 8 x float> %f)
ret <vscale x 8 x i16> %x
@@ -130,19 +82,8 @@ define <vscale x 8 x i16> @test_signed_v8f32_v8i16(<vscale x 8 x float> %f) {
define <vscale x 2 x i64> @test_signed_v2f32_v2i64(<vscale x 2 x float> %f) {
; CHECK-LABEL: test_signed_v2f32_v2i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-553648128 // =0xdf000000
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z1.s, w8
-; CHECK-NEXT: mov w8, #1593835519 // =0x5effffff
-; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z1.s
-; CHECK-NEXT: mov z1.d, #0x8000000000000000
-; CHECK-NEXT: fcmgt p2.s, p0/z, z0.s, z2.s
-; CHECK-NEXT: mov z2.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: fcvtzs z1.d, p1/m, z0.s
-; CHECK-NEXT: sel z0.d, p2, z2.d, z1.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
; CHECK-NEXT: ret
%x = call <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f32.nxv2i64(<vscale x 2 x float> %f)
ret <vscale x 2 x i64> %x
@@ -151,28 +92,13 @@ define <vscale x 2 x i64> @test_signed_v2f32_v2i64(<vscale x 2 x float> %f) {
define <vscale x 4 x i64> @test_signed_v4f32_v4i64(<vscale x 4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-553648128 // =0xdf000000
; CHECK-NEXT: uunpklo z1.d, z0.s
-; CHECK-NEXT: uunpkhi z0.d, z0.s
-; CHECK-NEXT: mov z2.s, w8
+; CHECK-NEXT: uunpkhi z2.d, z0.s
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov w8, #1593835519 // =0x5effffff
-; CHECK-NEXT: mov z3.d, #0x8000000000000000
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov z5.s, w8
-; CHECK-NEXT: fcmge p1.s, p0/z, z1.s, z2.s
-; CHECK-NEXT: fcmge p2.s, p0/z, z0.s, z2.s
-; CHECK-NEXT: mov z2.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmgt p3.s, p0/z, z0.s, z5.s
-; CHECK-NEXT: fcvtzs z3.d, p1/m, z1.s
-; CHECK-NEXT: fcmgt p1.s, p0/z, z1.s, z5.s
-; CHECK-NEXT: fcvtzs z4.d, p2/m, z0.s
-; CHECK-NEXT: fcmuo p2.s, p0/z, z1.s, z1.s
-; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: sel z0.d, p1, z2.d, z3.d
-; CHECK-NEXT: sel z1.d, p3, z2.d, z4.d
-; CHECK-NEXT: mov z0.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
+; CHECK-NEXT: movprfx z0, z1
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.s
+; CHECK-NEXT: movprfx z1, z2
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z2.s
; CHECK-NEXT: ret
%x = call <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f32.nxv4i64(<vscale x 4 x float> %f)
ret <vscale x 4 x i64> %x
@@ -191,18 +117,12 @@ declare <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f64.nxv4i64(<vscale x 4 x double
define <vscale x 2 x i32> @test_signed_v2f64_v2i32(<vscale x 2 x double> %f) {
; CHECK-LABEL: test_signed_v2f64_v2i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-4476578029606273024 // =0xc1e0000000000000
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z1.d, x8
-; CHECK-NEXT: mov x8, #281474972516352 // =0xffffffc00000
-; CHECK-NEXT: movk x8, #16863, lsl #48
-; CHECK-NEXT: mov z2.d, x8
-; CHECK-NEXT: fmaxnm z1.d, p0/m, z1.d, z0.d
-; CHECK-NEXT: fminnm z1.d, p0/m, z1.d, z2.d
-; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
-; CHECK-NEXT: mov z0.d, z1.d
+; CHECK-NEXT: mov z1.d, #0x7fffffff
+; CHECK-NEXT: mov z2.d, #0xffffffff80000000
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: smax z0.d, p0/m, z0.d, z2.d
; CHECK-NEXT: ret
%x = call <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f64.nxv2i32(<vscale x 2 x double> %f)
ret <vscale x 2 x i32> %x
@@ -211,24 +131,16 @@ define <vscale x 2 x i32> @test_signed_v2f64_v2i32(<vscale x 2 x double> %f) {
define <vscale x 4 x i32> @test_signed_v4f64_v4i32(<vscale x 4 x double> %f) {
; CHECK-LABEL: test_signed_v4f64_v4i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-4476578029606273024 // =0xc1e0000000000000
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z2.d, x8
-; CHECK-NEXT: mov x8, #281474972516352 // =0xffffffc00000
-; CHECK-NEXT: movk x8, #16863, lsl #48
-; CHECK-NEXT: mov z4.d, x8
-; CHECK-NEXT: movprfx z3, z1
-; CHECK-NEXT: fmaxnm z3.d, p0/m, z3.d, z2.d
-; CHECK-NEXT: fmaxnm z2.d, p0/m, z2.d, z0.d
-; CHECK-NEXT: fcmuo p1.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: fminnm z3.d, p0/m, z3.d, z4.d
-; CHECK-NEXT: fminnm z2.d, p0/m, z2.d, z4.d
-; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
-; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: mov z3.d, p1/m, #0 // =0x0
-; CHECK-NEXT: mov z2.d, p0/m, #0 // =0x0
-; CHECK-NEXT: uzp1 z0.s, z2.s, z3.s
+; CHECK-NEXT: mov z2.d, #0x7fffffff
+; CHECK-NEXT: mov z3.d, #0xffffffff80000000
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: smin z1.d, p0/m, z1.d, z2.d
+; CHECK-NEXT: smin z0.d, p0/m, z0.d, z2.d
+; CHECK-NEXT: smax z1.d, p0/m, z1.d, z3.d
+; CHECK-NEXT: smax z0.d, p0/m, z0.d, z3.d
+; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
; CHECK-NEXT: ret
%x = call <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f64.nxv4i32(<vscale x 4 x double> %f)
ret <vscale x 4 x i32> %x
@@ -237,37 +149,23 @@ define <vscale x 4 x i32> @test_signed_v4f64_v4i32(<vscale x 4 x double> %f) {
define <vscale x 8 x i32> @test_signed_v8f64_v8i32(<vscale x 8 x double> %f) {
; CHECK-LABEL: test_signed_v8f64_v8i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-4476578029606273024 // =0xc1e0000000000000
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z4.d, x8
-; CHECK-NEXT: mov x8, #281474972516352 // =0xffffffc00000
-; CHECK-NEXT: movk x8, #16863, lsl #48
-; CHECK-NEXT: mov z5.d, x8
-; CHECK-NEXT: movprfx z6, z1
-; CHECK-NEXT: fmaxnm z6.d, p0/m, z6.d, z4.d
-; CHECK-NEXT: movprfx z7, z0
-; CHECK-NEXT: fmaxnm z7.d, p0/m, z7.d, z4.d
-; CHECK-NEXT: movprfx z24, z3
-; CHECK-NEXT: fmaxnm z24.d, p0/m, z24.d, z4.d
-; CHECK-NEXT: fmaxnm z4.d, p0/m, z4.d, z2.d
-; CHECK-NEXT: fcmuo p1.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: fcmuo p2.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: fminnm z6.d, p0/m, z6.d, z5.d
-; CHECK-NEXT: fminnm z7.d, p0/m, z7.d, z5.d
-; CHECK-NEXT: fminnm z24.d, p0/m, z24.d, z5.d
-; CHECK-NEXT: fminnm z4.d, p0/m, z4.d, z5.d
-; CHECK-NEXT: fcmuo p3.d, p0/z, z3.d, z3.d
-; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.d
-; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.d
-; CHECK-NEXT: fcvtzs z24.d, p0/m, z24.d
-; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.d
-; CHECK-NEXT: fcmuo p0.d, p0/z, z2.d, z2.d
-; CHECK-NEXT: mov z6.d, p1/m, #0 // =0x0
-; CHECK-NEXT: mov z7.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z24.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z4.d, p0/m, #0 // =0x0
-; CHECK-NEXT: uzp1 z0.s, z7.s, z6.s
-; CHECK-NEXT: uzp1 z1.s, z4.s, z24.s
+; CHECK-NEXT: mov z4.d, #0x7fffffff
+; CHECK-NEXT: mov z5.d, #0xffffffff80000000
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
+; CHECK-NEXT: smin z1.d, p0/m, z1.d, z4.d
+; CHECK-NEXT: smin z0.d, p0/m, z0.d, z4.d
+; CHECK-NEXT: smin z3.d, p0/m, z3.d, z4.d
+; CHECK-NEXT: smin z2.d, p0/m, z2.d, z4.d
+; CHECK-NEXT: smax z1.d, p0/m, z1.d, z5.d
+; CHECK-NEXT: smax z0.d, p0/m, z0.d, z5.d
+; CHECK-NEXT: smax z3.d, p0/m, z3.d, z5.d
+; CHECK-NEXT: smax z2.d, p0/m, z2.d, z5.d
+; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
+; CHECK-NEXT: uzp1 z1.s, z2.s, z3.s
; CHECK-NEXT: ret
%x = call <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f64.nxv8i32(<vscale x 8 x double> %f)
ret <vscale x 8 x i32> %x
@@ -276,24 +174,16 @@ define <vscale x 8 x i32> @test_signed_v8f64_v8i32(<vscale x 8 x double> %f) {
define <vscale x 4 x i16> @test_signed_v4f64_v4i16(<vscale x 4 x double> %f) {
; CHECK-LABEL: test_signed_v4f64_v4i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-4548635623644200960 // =0xc0e0000000000000
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z2.d, x8
-; CHECK-NEXT: mov x8, #281200098803712 // =0xffc000000000
-; CHECK-NEXT: movk x8, #16607, lsl #48
-; CHECK-NEXT: mov z4.d, x8
-; CHECK-NEXT: movprfx z3, z1
-; CHECK-NEXT: fmaxnm z3.d, p0/m, z3.d, z2.d
-; CHECK-NEXT: fmaxnm z2.d, p0/m, z2.d, z0.d
-; CHECK-NEXT: fcmuo p1.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: fminnm z3.d, p0/m, z3.d, z4.d
-; CHECK-NEXT: fminnm z2.d, p0/m, z2.d, z4.d
-; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
-; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: mov z3.d, p1/m, #0 // =0x0
-; CHECK-NEXT: mov z2.d, p0/m, #0 // =0x0
-; CHECK-NEXT: uzp1 z0.s, z2.s, z3.s
+; CHECK-NEXT: mov z2.d, #32767 // =0x7fff
+; CHECK-NEXT: mov z3.d, #-32768 // =0xffffffffffff8000
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: smin z1.d, p0/m, z1.d, z2.d
+; CHECK-NEXT: smin z0.d, p0/m, z0.d, z2.d
+; CHECK-NEXT: smax z1.d, p0/m, z1.d, z3.d
+; CHECK-NEXT: smax z0.d, p0/m, z0.d, z3.d
+; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
; CHECK-NEXT: ret
%x = call <vscale x 4 x i16> @llvm.fptosi.sat.nxv4f64.nxv4i16(<vscale x 4 x double> %f)
ret <vscale x 4 x i16> %x
@@ -302,38 +192,24 @@ define <vscale x 4 x i16> @test_signed_v4f64_v4i16(<vscale x 4 x double> %f) {
define <vscale x 8 x i16> @test_signed_v8f64_v8i16(<vscale x 8 x double> %f) {
; CHECK-LABEL: test_signed_v8f64_v8i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-4548635623644200960 // =0xc0e0000000000000
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z4.d, x8
-; CHECK-NEXT: mov x8, #281200098803712 // =0xffc000000000
-; CHECK-NEXT: movk x8, #16607, lsl #48
-; CHECK-NEXT: mov z5.d, x8
-; CHECK-NEXT: movprfx z6, z3
-; CHECK-NEXT: fmaxnm z6.d, p0/m, z6.d, z4.d
-; CHECK-NEXT: movprfx z7, z2
-; CHECK-NEXT: fmaxnm z7.d, p0/m, z7.d, z4.d
-; CHECK-NEXT: movprfx z24, z1
-; CHECK-NEXT: fmaxnm z24.d, p0/m, z24.d, z4.d
-; CHECK-NEXT: fmaxnm z4.d, p0/m, z4.d, z0.d
-; CHECK-NEXT: fcmuo p1.d, p0/z, z3.d, z3.d
-; CHECK-NEXT: fcmuo p2.d, p0/z, z2.d, z2.d
-; CHECK-NEXT: fminnm z6.d, p0/m, z6.d, z5.d
-; CHECK-NEXT: fminnm z7.d, p0/m, z7.d, z5.d
-; CHECK-NEXT: fminnm z24.d, p0/m, z24.d, z5.d
-; CHECK-NEXT: fminnm z4.d, p0/m, z4.d, z5.d
-; CHECK-NEXT: fcmuo p3.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.d
-; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.d
-; CHECK-NEXT: fcvtzs z24.d, p0/m, z24.d
-; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.d
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: mov z6.d, p1/m, #0 // =0x0
-; CHECK-NEXT: mov z7.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z24.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z4.d, p0/m, #0 // =0x0
-; CHECK-NEXT: uzp1 z0.s, z7.s, z6.s
-; CHECK-NEXT: uzp1 z1.s, z4.s, z24.s
-; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h
+; CHECK-NEXT: mov z4.d, #32767 // =0x7fff
+; CHECK-NEXT: mov z5.d, #-32768 // =0xffffffffffff8000
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: smin z3.d, p0/m, z3.d, z4.d
+; CHECK-NEXT: smin z2.d, p0/m, z2.d, z4.d
+; CHECK-NEXT: smin z1.d, p0/m, z1.d, z4.d
+; CHECK-NEXT: smin z0.d, p0/m, z0.d, z4.d
+; CHECK-NEXT: smax z3.d, p0/m, z3.d, z5.d
+; CHECK-NEXT: smax z2.d, p0/m, z2.d, z5.d
+; CHECK-NEXT: smax z1.d, p0/m, z1.d, z5.d
+; CHECK-NEXT: smax z0.d, p0/m, z0.d, z5.d
+; CHECK-NEXT: uzp1 z2.s, z2.s, z3.s
+; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
+; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h
; CHECK-NEXT: ret
%x = call <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f64.nxv8i16(<vscale x 8 x double> %f)
ret <vscale x 8 x i16> %x
@@ -342,19 +218,8 @@ define <vscale x 8 x i16> @test_signed_v8f64_v8i16(<vscale x 8 x double> %f) {
define <vscale x 2 x i64> @test_signed_v2f64_v2i64(<vscale x 2 x double> %f) {
; CHECK-LABEL: test_signed_v2f64_v2i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z1.d, x8
-; CHECK-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff
-; CHECK-NEXT: mov z2.d, x8
-; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z1.d
-; CHECK-NEXT: mov z1.d, #0x8000000000000000
-; CHECK-NEXT: fcmgt p2.d, p0/z, z0.d, z2.d
-; CHECK-NEXT: mov z2.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: fcvtzs z1.d, p1/m, z0.d
-; CHECK-NEXT: sel z0.d, p2, z2.d, z1.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
; CHECK-NEXT: ret
%x = call <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f64.nxv2i64(<vscale x 2 x double> %f)
ret <vscale x 2 x i64> %x
@@ -363,26 +228,9 @@ define <vscale x 2 x i64> @test_signed_v2f64_v2i64(<vscale x 2 x double> %f) {
define <vscale x 4 x i64> @test_signed_v4f64_v4i64(<vscale x 4 x double> %f) {
; CHECK-LABEL: test_signed_v4f64_v4i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z3.d, #0x8000000000000000
-; CHECK-NEXT: mov z2.d, x8
-; CHECK-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov z5.d, x8
-; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z2.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z1.d, z2.d
-; CHECK-NEXT: mov z2.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmgt p3.d, p0/z, z1.d, z5.d
-; CHECK-NEXT: fcvtzs z3.d, p1/m, z0.d
-; CHECK-NEXT: fcmgt p1.d, p0/z, z0.d, z5.d
-; CHECK-NEXT: fcvtzs z4.d, p2/m, z1.d
-; CHECK-NEXT: fcmuo p2.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: fcmuo p0.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: sel z0.d, p1, z2.d, z3.d
-; CHECK-NEXT: sel z1.d, p3, z2.d, z4.d
-; CHECK-NEXT: mov z0.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
; CHECK-NEXT: ret
%x = call <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f64.nxv4i64(<vscale x 4 x double> %f)
ret <vscale x 4 x i64> %x
@@ -402,18 +250,13 @@ declare <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f16.nxv4i64(<vscale x 4 x half>)
define <vscale x 2 x i32> @test_signed_v2f16_v2i32(<vscale x 2 x half> %f) {
; CHECK-LABEL: test_signed_v2f16_v2i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov z1.h, #-1025 // =0xfffffffffffffbff
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
-; CHECK-NEXT: mov z2.d, #0xffffffff80000000
-; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.h, w8
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z1.h
; CHECK-NEXT: mov z1.d, #0x7fffffff
-; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
-; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: mov z2.d, #0xffffffff80000000
+; CHECK-NEXT: fcvt z0.d, p0/m, z0.h
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: smax z0.d, p0/m, z0.d, z2.d
; CHECK-NEXT: ret
%x = call <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f16.nxv2i32(<vscale x 2 x half> %f)
ret <vscale x 2 x i32> %x
@@ -422,18 +265,8 @@ define <vscale x 2 x i32> @test_signed_v2f16_v2i32(<vscale x 2 x half> %f) {
define <vscale x 4 x i32> @test_signed_v4f16_v4i32(<vscale x 4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov z1.h, #-1025 // =0xfffffffffffffbff
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
-; CHECK-NEXT: mov z2.s, #0x80000000
-; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.h, w8
-; CHECK-NEXT: fcvtzs z2.s, p1/m, z0.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.s, #0x7fffffff
-; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
-; CHECK-NEXT: sel z0.s, p1, z1.s, z2.s
-; CHECK-NEXT: mov z0.s, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h
; CHECK-NEXT: ret
%x = call <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f16.nxv4i32(<vscale x 4 x half> %f)
ret <vscale x 4 x i32> %x
@@ -442,27 +275,13 @@ define <vscale x 4 x i32> @test_signed_v4f16_v4i32(<vscale x 4 x half> %f) {
define <vscale x 8 x i32> @test_signed_v8f16_v8i32(<vscale x 8 x half> %f) {
; CHECK-LABEL: test_signed_v8f16_v8i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov z1.h, #-1025 // =0xfffffffffffffbff
-; CHECK-NEXT: uunpklo z2.s, z0.h
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
-; CHECK-NEXT: uunpkhi z0.s, z0.h
+; CHECK-NEXT: uunpklo z1.s, z0.h
+; CHECK-NEXT: uunpkhi z2.s, z0.h
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: mov z3.s, #0x80000000
-; CHECK-NEXT: mov z4.s, #0x80000000
-; CHECK-NEXT: mov z5.h, w8
-; CHECK-NEXT: fcmge p1.h, p0/z, z2.h, z1.h
-; CHECK-NEXT: fcmge p2.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.s, #0x7fffffff
-; CHECK-NEXT: fcmgt p3.h, p0/z, z0.h, z5.h
-; CHECK-NEXT: fcvtzs z3.s, p1/m, z2.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z2.h, z5.h
-; CHECK-NEXT: fcvtzs z4.s, p2/m, z0.h
-; CHECK-NEXT: fcmuo p2.h, p0/z, z2.h, z2.h
-; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
-; CHECK-NEXT: sel z0.s, p1, z1.s, z3.s
-; CHECK-NEXT: sel z1.s, p3, z1.s, z4.s
-; CHECK-NEXT: mov z0.s, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z1.s, p0/m, #0 // =0x0
+; CHECK-NEXT: movprfx z0, z1
+; CHECK-NEXT: fcvtzs z0.s, p0/m, z1.h
+; CHECK-NEXT: movprfx z1, z2
+; CHECK-NEXT: fcvtzs z1.s, p0/m, z2.h
; CHECK-NEXT: ret
%x = call <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f16.nxv8i32(<vscale x 8 x half> %f)
ret <vscale x 8 x i32> %x
@@ -471,18 +290,13 @@ define <vscale x 8 x i32> @test_signed_v8f16_v8i32(<vscale x 8 x half> %f) {
define <vscale x 4 x i16> @test_signed_v4f16_v4i16(<vscale x 4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: dupm z1.h, #0xf800
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: mov w8, #30719 // =0x77ff
-; CHECK-NEXT: mov z2.h, w8
-; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
+; CHECK-NEXT: mov z1.s, #32767 // =0x7fff
+; CHECK-NEXT: fcvt z0.s, p0/m, z0.h
+; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT: mov z1.s, #-32768 // =0xffffffffffff8000
-; CHECK-NEXT: fcvtzs z1.s, p1/m, z0.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z2.h
-; CHECK-NEXT: mov z2.s, #32767 // =0x7fff
-; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
-; CHECK-NEXT: sel z0.s, p1, z2.s, z1.s
-; CHECK-NEXT: mov z0.s, p0/m, #0 // =0x0
+; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT: ret
%x = call <vscale x 4 x i16> @llvm.fptosi.sat.nxv4f16.nxv4i16(<vscale x 4 x half> %f)
ret <vscale x 4 x i16> %x
@@ -491,18 +305,8 @@ define <vscale x 4 x i16> @test_signed_v4f16_v4i16(<vscale x 4 x half> %f) {
define <vscale x 8 x i16> @test_signed_v8f16_v8i16(<vscale x 8 x half> %f) {
; CHECK-LABEL: test_signed_v8f16_v8i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: dupm z1.h, #0xf800
; CHECK-NEXT: ptrue p0.h
-; CHECK-NEXT: mov w8, #30719 // =0x77ff
-; CHECK-NEXT: mov z2.h, w8
-; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.h, #-32768 // =0xffffffffffff8000
-; CHECK-NEXT: fcvtzs z1.h, p1/m, z0.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z2.h
-; CHECK-NEXT: mov z2.h, #32767 // =0x7fff
-; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
-; CHECK-NEXT: sel z0.h, p1, z2.h, z1.h
-; CHECK-NEXT: mov z0.h, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.h, p0/m, z0.h
; CHECK-NEXT: ret
%x = call <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f16.nxv8i16(<vscale x 8 x half> %f)
ret <vscale x 8 x i16> %x
@@ -511,18 +315,8 @@ define <vscale x 8 x i16> @test_signed_v8f16_v8i16(<vscale x 8 x half> %f) {
define <vscale x 2 x i64> @test_signed_v2f16_v2i64(<vscale x 2 x half> %f) {
; CHECK-LABEL: test_signed_v2f16_v2i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov z1.h, #-1025 // =0xfffffffffffffbff
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.h, w8
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
-; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
; CHECK-NEXT: ret
%x = call <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f16.nxv2i64(<vscale x 2 x half> %f)
ret <vscale x 2 x i64> %x
@@ -531,27 +325,13 @@ define <vscale x 2 x i64> @test_signed_v2f16_v2i64(<vscale x 2 x half> %f) {
define <vscale x 4 x i64> @test_signed_v4f16_v4i64(<vscale x 4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov z1.h, #-1025 // =0xfffffffffffffbff
-; CHECK-NEXT: uunpklo z2.d, z0.s
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
-; CHECK-NEXT: uunpkhi z0.d, z0.s
+; CHECK-NEXT: uunpklo z1.d, z0.s
+; CHECK-NEXT: uunpkhi z2.d, z0.s
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z3.d, #0x8000000000000000
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov z5.h, w8
-; CHECK-NEXT: fcmge p1.h, p0/z, z2.h, z1.h
-; CHECK-NEXT: fcmge p2.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmgt p3.h, p0/z, z0.h, z5.h
-; CHECK-NEXT: fcvtzs z3.d, p1/m, z2.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z2.h, z5.h
-; CHECK-NEXT: fcvtzs z4.d, p2/m, z0.h
-; CHECK-NEXT: fcmuo p2.h, p0/z, z2.h, z2.h
-; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
-; CHECK-NEXT: sel z0.d, p1, z1.d, z3.d
-; CHECK-NEXT: sel z1.d, p3, z1.d, z4.d
-; CHECK-NEXT: mov z0.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
+; CHECK-NEXT: movprfx z0, z1
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.h
+; CHECK-NEXT: movprfx z1, z2
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z2.h
; CHECK-NEXT: ret
%x = call <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f16.nxv4i64(<vscale x 4 x half> %f)
ret <vscale x 4 x i64> %x
diff --git a/llvm/test/CodeGen/AArch64/sve-fptoui-sat.ll b/llvm/test/CodeGen/AArch64/sve-fptoui-sat.ll
index 61620fbdf0826..be3a0c21e8611 100644
--- a/llvm/test/CodeGen/AArch64/sve-fptoui-sat.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fptoui-sat.ll
@@ -15,14 +15,10 @@ define <vscale x 2 x i32> @test_signed_v2f32_v2i32(<vscale x 2 x float> %f) {
; CHECK-LABEL: test_signed_v2f32_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov w8, #1333788671 // =0x4f7fffff
-; CHECK-NEXT: movi v1.2d, #0000000000000000
-; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, #0.0
-; CHECK-NEXT: fcmgt p0.s, p0/z, z0.s, z2.s
-; CHECK-NEXT: fcvtzu z1.d, p1/m, z0.s
-; CHECK-NEXT: mov z0.d, #0xffffffff
-; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: mov z1.d, #0xffffffff
+; CHECK-NEXT: fcvt z0.d, p0/m, z0.s
+; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
+; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d
; CHECK-NEXT: ret
%x = call <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f32.nxv2i32(<vscale x 2 x float> %f)
ret <vscale x 2 x i32> %x
@@ -32,14 +28,7 @@ define <vscale x 4 x i32> @test_signed_v4f32_v4i32(<vscale x 4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: mov w8, #1333788671 // =0x4f7fffff
-; CHECK-NEXT: movi v1.2d, #0000000000000000
-; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, #0.0
-; CHECK-NEXT: fcmgt p0.s, p0/z, z0.s, z2.s
-; CHECK-NEXT: fcvtzu z1.s, p1/m, z0.s
-; CHECK-NEXT: mov z1.s, p0/m, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: mov z0.d, z1.d
+; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s
; CHECK-NEXT: ret
%x = call <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f32.nxv4i32(<vscale x 4 x float> %f)
ret <vscale x 4 x i32> %x
@@ -49,20 +38,8 @@ define <vscale x 8 x i32> @test_signed_v8f32_v8i32(<vscale x 8 x float> %f) {
; CHECK-LABEL: test_signed_v8f32_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: mov w8, #1333788671 // =0x4f7fffff
-; CHECK-NEXT: movi v2.2d, #0000000000000000
-; CHECK-NEXT: movi v3.2d, #0000000000000000
-; CHECK-NEXT: mov z4.s, w8
-; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, #0.0
-; CHECK-NEXT: fcmge p2.s, p0/z, z1.s, #0.0
-; CHECK-NEXT: fcvtzu z2.s, p1/m, z0.s
-; CHECK-NEXT: fcmgt p1.s, p0/z, z0.s, z4.s
-; CHECK-NEXT: fcvtzu z3.s, p2/m, z1.s
-; CHECK-NEXT: fcmgt p0.s, p0/z, z1.s, z4.s
-; CHECK-NEXT: mov z2.s, p1/m, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: mov z3.s, p0/m, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: mov z0.d, z2.d
-; CHECK-NEXT: mov z1.d, z3.d
+; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s
+; CHECK-NEXT: fcvtzu z1.s, p0/m, z1.s
; CHECK-NEXT: ret
%x = call <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f32.nxv8i32(<vscale x 8 x float> %f)
ret <vscale x 8 x i32> %x
@@ -72,16 +49,9 @@ define <vscale x 4 x i16> @test_signed_v4f32_v4i16(<vscale x 4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: mov w8, #65280 // =0xff00
-; CHECK-NEXT: movk w8, #18303, lsl #16
-; CHECK-NEXT: movprfx z1, z0
-; CHECK-NEXT: fmaxnm z1.s, p0/m, z1.s, #0.0
-; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: fminnm z1.s, p0/m, z1.s, z2.s
-; CHECK-NEXT: fcvtzu z1.s, p0/m, z1.s
-; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: mov z1.s, p0/m, #0 // =0x0
-; CHECK-NEXT: mov z0.d, z1.d
+; CHECK-NEXT: mov z1.s, #65535 // =0xffff
+; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s
+; CHECK-NEXT: umin z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT: ret
%x = call <vscale x 4 x i16> @llvm.fptoui.sat.nxv4f32.nxv4i16(<vscale x 4 x float> %f)
ret <vscale x 4 x i16> %x
@@ -91,22 +61,12 @@ define <vscale x 8 x i16> @test_signed_v8f32_v8i16(<vscale x 8 x float> %f) {
; CHECK-LABEL: test_signed_v8f32_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: mov w8, #65280 // =0xff00
-; CHECK-NEXT: movk w8, #18303, lsl #16
-; CHECK-NEXT: movprfx z2, z1
-; CHECK-NEXT: fmaxnm z2.s, p0/m, z2.s, #0.0
-; CHECK-NEXT: movprfx z3, z0
-; CHECK-NEXT: fmaxnm z3.s, p0/m, z3.s, #0.0
-; CHECK-NEXT: mov z4.s, w8
-; CHECK-NEXT: fcmuo p1.s, p0/z, z1.s, z1.s
-; CHECK-NEXT: fminnm z2.s, p0/m, z2.s, z4.s
-; CHECK-NEXT: fminnm z3.s, p0/m, z3.s, z4.s
-; CHECK-NEXT: fcvtzu z2.s, p0/m, z2.s
-; CHECK-NEXT: fcvtzu z3.s, p0/m, z3.s
-; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: mov z2.s, p1/m, #0 // =0x0
-; CHECK-NEXT: mov z3.s, p0/m, #0 // =0x0
-; CHECK-NEXT: uzp1 z0.h, z3.h, z2.h
+; CHECK-NEXT: mov z2.s, #65535 // =0xffff
+; CHECK-NEXT: fcvtzu z1.s, p0/m, z1.s
+; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s
+; CHECK-NEXT: umin z1.s, p0/m, z1.s, z2.s
+; CHECK-NEXT: umin z0.s, p0/m, z0.s, z2.s
+; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h
; CHECK-NEXT: ret
%x = call <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f32.nxv8i16(<vscale x 8 x float> %f)
ret <vscale x 8 x i16> %x
@@ -116,14 +76,7 @@ define <vscale x 2 x i64> @test_signed_v2f32_v2i64(<vscale x 2 x float> %f) {
; CHECK-LABEL: test_signed_v2f32_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov w8, #1602224127 // =0x5f7fffff
-; CHECK-NEXT: movi v1.2d, #0000000000000000
-; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, #0.0
-; CHECK-NEXT: fcmgt p0.s, p0/z, z0.s, z2.s
-; CHECK-NEXT: fcvtzu z1.d, p1/m, z0.s
-; CHECK-NEXT: mov z1.d, p0/m, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: mov z0.d, z1.d
+; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.s
; CHECK-NEXT: ret
%x = call <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f32.nxv2i64(<vscale x 2 x float> %f)
ret <vscale x 2 x i64> %x
@@ -132,21 +85,13 @@ define <vscale x 2 x i64> @test_signed_v2f32_v2i64(<vscale x 2 x float> %f) {
define <vscale x 4 x i64> @test_signed_v4f32_v4i64(<vscale x 4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: uunpklo z2.d, z0.s
-; CHECK-NEXT: uunpkhi z3.d, z0.s
-; CHECK-NEXT: mov w8, #1602224127 // =0x5f7fffff
+; CHECK-NEXT: uunpklo z1.d, z0.s
+; CHECK-NEXT: uunpkhi z2.d, z0.s
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: movi v0.2d, #0000000000000000
-; CHECK-NEXT: movi v1.2d, #0000000000000000
-; CHECK-NEXT: mov z4.s, w8
-; CHECK-NEXT: fcmge p1.s, p0/z, z2.s, #0.0
-; CHECK-NEXT: fcmge p2.s, p0/z, z3.s, #0.0
-; CHECK-NEXT: fcvtzu z0.d, p1/m, z2.s
-; CHECK-NEXT: fcmgt p1.s, p0/z, z2.s, z4.s
-; CHECK-NEXT: fcvtzu z1.d, p2/m, z3.s
-; CHECK-NEXT: fcmgt p0.s, p0/z, z3.s, z4.s
-; CHECK-NEXT: mov z0.d, p1/m, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: mov z1.d, p0/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: movprfx z0, z1
+; CHECK-NEXT: fcvtzu z0.d, p0/m, z1.s
+; CHECK-NEXT: movprfx z1, z2
+; CHECK-NEXT: fcvtzu z1.d, p0/m, z2.s
; CHECK-NEXT: ret
%x = call <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f32.nxv4i64(<vscale x 4 x float> %f)
ret <vscale x 4 x i64> %x
@@ -166,16 +111,9 @@ define <vscale x 2 x i32> @test_signed_v2f64_v2i32(<vscale x 2 x double> %f) {
; CHECK-LABEL: test_signed_v2f64_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #281474974613504 // =0xffffffe00000
-; CHECK-NEXT: movk x8, #16879, lsl #48
-; CHECK-NEXT: movprfx z1, z0
-; CHECK-NEXT: fmaxnm z1.d, p0/m, z1.d, #0.0
-; CHECK-NEXT: mov z2.d, x8
-; CHECK-NEXT: fminnm z1.d, p0/m, z1.d, z2.d
-; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.d
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
-; CHECK-NEXT: mov z0.d, z1.d
+; CHECK-NEXT: mov z1.d, #0xffffffff
+; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
+; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d
; CHECK-NEXT: ret
%x = call <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f64.nxv2i32(<vscale x 2 x double> %f)
ret <vscale x 2 x i32> %x
@@ -185,22 +123,12 @@ define <vscale x 4 x i32> @test_signed_v4f64_v4i32(<vscale x 4 x double> %f) {
; CHECK-LABEL: test_signed_v4f64_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #281474974613504 // =0xffffffe00000
-; CHECK-NEXT: movk x8, #16879, lsl #48
-; CHECK-NEXT: movprfx z2, z1
-; CHECK-NEXT: fmaxnm z2.d, p0/m, z2.d, #0.0
-; CHECK-NEXT: movprfx z3, z0
-; CHECK-NEXT: fmaxnm z3.d, p0/m, z3.d, #0.0
-; CHECK-NEXT: mov z4.d, x8
-; CHECK-NEXT: fcmuo p1.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: fminnm z2.d, p0/m, z2.d, z4.d
-; CHECK-NEXT: fminnm z3.d, p0/m, z3.d, z4.d
-; CHECK-NEXT: fcvtzu z2.d, p0/m, z2.d
-; CHECK-NEXT: fcvtzu z3.d, p0/m, z3.d
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: mov z2.d, p1/m, #0 // =0x0
-; CHECK-NEXT: mov z3.d, p0/m, #0 // =0x0
-; CHECK-NEXT: uzp1 z0.s, z3.s, z2.s
+; CHECK-NEXT: mov z2.d, #0xffffffff
+; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
+; CHECK-NEXT: umin z1.d, p0/m, z1.d, z2.d
+; CHECK-NEXT: umin z0.d, p0/m, z0.d, z2.d
+; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
; CHECK-NEXT: ret
%x = call <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f64.nxv4i32(<vscale x 4 x double> %f)
ret <vscale x 4 x i32> %x
@@ -210,35 +138,17 @@ define <vscale x 8 x i32> @test_signed_v8f64_v8i32(<vscale x 8 x double> %f) {
; CHECK-LABEL: test_signed_v8f64_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #281474974613504 // =0xffffffe00000
-; CHECK-NEXT: movk x8, #16879, lsl #48
-; CHECK-NEXT: movprfx z5, z1
-; CHECK-NEXT: fmaxnm z5.d, p0/m, z5.d, #0.0
-; CHECK-NEXT: movprfx z6, z0
-; CHECK-NEXT: fmaxnm z6.d, p0/m, z6.d, #0.0
-; CHECK-NEXT: movprfx z7, z3
-; CHECK-NEXT: fmaxnm z7.d, p0/m, z7.d, #0.0
-; CHECK-NEXT: movprfx z24, z2
-; CHECK-NEXT: fmaxnm z24.d, p0/m, z24.d, #0.0
-; CHECK-NEXT: mov z4.d, x8
-; CHECK-NEXT: fcmuo p1.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: fcmuo p2.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: fminnm z5.d, p0/m, z5.d, z4.d
-; CHECK-NEXT: fminnm z6.d, p0/m, z6.d, z4.d
-; CHECK-NEXT: fminnm z7.d, p0/m, z7.d, z4.d
-; CHECK-NEXT: fminnm z4.d, p0/m, z4.d, z24.d
-; CHECK-NEXT: fcmuo p3.d, p0/z, z3.d, z3.d
-; CHECK-NEXT: fcvtzu z5.d, p0/m, z5.d
-; CHECK-NEXT: fcvtzu z6.d, p0/m, z6.d
-; CHECK-NEXT: fcvtzu z7.d, p0/m, z7.d
-; CHECK-NEXT: fcvtzu z4.d, p0/m, z4.d
-; CHECK-NEXT: fcmuo p0.d, p0/z, z2.d, z2.d
-; CHECK-NEXT: mov z5.d, p1/m, #0 // =0x0
-; CHECK-NEXT: mov z6.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z7.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z4.d, p0/m, #0 // =0x0
-; CHECK-NEXT: uzp1 z0.s, z6.s, z5.s
-; CHECK-NEXT: uzp1 z1.s, z4.s, z7.s
+; CHECK-NEXT: mov z4.d, #0xffffffff
+; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzu z3.d, p0/m, z3.d
+; CHECK-NEXT: fcvtzu z2.d, p0/m, z2.d
+; CHECK-NEXT: umin z1.d, p0/m, z1.d, z4.d
+; CHECK-NEXT: umin z0.d, p0/m, z0.d, z4.d
+; CHECK-NEXT: umin z3.d, p0/m, z3.d, z4.d
+; CHECK-NEXT: umin z2.d, p0/m, z2.d, z4.d
+; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
+; CHECK-NEXT: uzp1 z1.s, z2.s, z3.s
; CHECK-NEXT: ret
%x = call <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f64.nxv8i32(<vscale x 8 x double> %f)
ret <vscale x 8 x i32> %x
@@ -248,22 +158,12 @@ define <vscale x 4 x i16> @test_signed_v4f64_v4i16(<vscale x 4 x double> %f) {
; CHECK-LABEL: test_signed_v4f64_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #281337537757184 // =0xffe000000000
-; CHECK-NEXT: movk x8, #16623, lsl #48
-; CHECK-NEXT: movprfx z2, z1
-; CHECK-NEXT: fmaxnm z2.d, p0/m, z2.d, #0.0
-; CHECK-NEXT: movprfx z3, z0
-; CHECK-NEXT: fmaxnm z3.d, p0/m, z3.d, #0.0
-; CHECK-NEXT: mov z4.d, x8
-; CHECK-NEXT: fcmuo p1.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: fminnm z2.d, p0/m, z2.d, z4.d
-; CHECK-NEXT: fminnm z3.d, p0/m, z3.d, z4.d
-; CHECK-NEXT: fcvtzu z2.d, p0/m, z2.d
-; CHECK-NEXT: fcvtzu z3.d, p0/m, z3.d
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: mov z2.d, p1/m, #0 // =0x0
-; CHECK-NEXT: mov z3.d, p0/m, #0 // =0x0
-; CHECK-NEXT: uzp1 z0.s, z3.s, z2.s
+; CHECK-NEXT: mov z2.d, #65535 // =0xffff
+; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
+; CHECK-NEXT: umin z1.d, p0/m, z1.d, z2.d
+; CHECK-NEXT: umin z0.d, p0/m, z0.d, z2.d
+; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
; CHECK-NEXT: ret
%x = call <vscale x 4 x i16> @llvm.fptoui.sat.nxv4f64.nxv4i16(<vscale x 4 x double> %f)
ret <vscale x 4 x i16> %x
@@ -273,36 +173,18 @@ define <vscale x 8 x i16> @test_signed_v8f64_v8i16(<vscale x 8 x double> %f) {
; CHECK-LABEL: test_signed_v8f64_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #281337537757184 // =0xffe000000000
-; CHECK-NEXT: movk x8, #16623, lsl #48
-; CHECK-NEXT: movprfx z5, z3
-; CHECK-NEXT: fmaxnm z5.d, p0/m, z5.d, #0.0
-; CHECK-NEXT: movprfx z6, z2
-; CHECK-NEXT: fmaxnm z6.d, p0/m, z6.d, #0.0
-; CHECK-NEXT: movprfx z7, z1
-; CHECK-NEXT: fmaxnm z7.d, p0/m, z7.d, #0.0
-; CHECK-NEXT: movprfx z24, z0
-; CHECK-NEXT: fmaxnm z24.d, p0/m, z24.d, #0.0
-; CHECK-NEXT: mov z4.d, x8
-; CHECK-NEXT: fcmuo p1.d, p0/z, z3.d, z3.d
-; CHECK-NEXT: fcmuo p2.d, p0/z, z2.d, z2.d
-; CHECK-NEXT: fminnm z5.d, p0/m, z5.d, z4.d
-; CHECK-NEXT: fminnm z6.d, p0/m, z6.d, z4.d
-; CHECK-NEXT: fminnm z7.d, p0/m, z7.d, z4.d
-; CHECK-NEXT: fminnm z4.d, p0/m, z4.d, z24.d
-; CHECK-NEXT: fcmuo p3.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: fcvtzu z5.d, p0/m, z5.d
-; CHECK-NEXT: fcvtzu z6.d, p0/m, z6.d
-; CHECK-NEXT: fcvtzu z7.d, p0/m, z7.d
-; CHECK-NEXT: fcvtzu z4.d, p0/m, z4.d
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: mov z5.d, p1/m, #0 // =0x0
-; CHECK-NEXT: mov z6.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z7.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z4.d, p0/m, #0 // =0x0
-; CHECK-NEXT: uzp1 z0.s, z6.s, z5.s
-; CHECK-NEXT: uzp1 z1.s, z4.s, z7.s
-; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h
+; CHECK-NEXT: mov z4.d, #65535 // =0xffff
+; CHECK-NEXT: fcvtzu z3.d, p0/m, z3.d
+; CHECK-NEXT: fcvtzu z2.d, p0/m, z2.d
+; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
+; CHECK-NEXT: umin z3.d, p0/m, z3.d, z4.d
+; CHECK-NEXT: umin z2.d, p0/m, z2.d, z4.d
+; CHECK-NEXT: umin z1.d, p0/m, z1.d, z4.d
+; CHECK-NEXT: umin z0.d, p0/m, z0.d, z4.d
+; CHECK-NEXT: uzp1 z2.s, z2.s, z3.s
+; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
+; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h
; CHECK-NEXT: ret
%x = call <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f64.nxv8i16(<vscale x 8 x double> %f)
ret <vscale x 8 x i16> %x
@@ -312,14 +194,7 @@ define <vscale x 2 x i64> @test_signed_v2f64_v2i64(<vscale x 2 x double> %f) {
; CHECK-LABEL: test_signed_v2f64_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #4895412794951729151 // =0x43efffffffffffff
-; CHECK-NEXT: movi v1.2d, #0000000000000000
-; CHECK-NEXT: mov z2.d, x8
-; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, #0.0
-; CHECK-NEXT: fcmgt p0.d, p0/z, z0.d, z2.d
-; CHECK-NEXT: fcvtzu z1.d, p1/m, z0.d
-; CHECK-NEXT: mov z1.d, p0/m, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: mov z0.d, z1.d
+; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
; CHECK-NEXT: ret
%x = call <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f64.nxv2i64(<vscale x 2 x double> %f)
ret <vscale x 2 x i64> %x
@@ -329,20 +204,8 @@ define <vscale x 4 x i64> @test_signed_v4f64_v4i64(<vscale x 4 x double> %f) {
; CHECK-LABEL: test_signed_v4f64_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #4895412794951729151 // =0x43efffffffffffff
-; CHECK-NEXT: movi v2.2d, #0000000000000000
-; CHECK-NEXT: movi v3.2d, #0000000000000000
-; CHECK-NEXT: mov z4.d, x8
-; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, #0.0
-; CHECK-NEXT: fcmge p2.d, p0/z, z1.d, #0.0
-; CHECK-NEXT: fcvtzu z2.d, p1/m, z0.d
-; CHECK-NEXT: fcmgt p1.d, p0/z, z0.d, z4.d
-; CHECK-NEXT: fcvtzu z3.d, p2/m, z1.d
-; CHECK-NEXT: fcmgt p0.d, p0/z, z1.d, z4.d
-; CHECK-NEXT: mov z2.d, p1/m, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: mov z3.d, p0/m, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: mov z0.d, z2.d
-; CHECK-NEXT: mov z1.d, z3.d
+; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.d
; CHECK-NEXT: ret
%x = call <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f64.nxv4i64(<vscale x 4 x double> %f)
ret <vscale x 4 x i64> %x
@@ -363,14 +226,10 @@ define <vscale x 2 x i32> @test_signed_v2f16_v2i32(<vscale x 2 x half> %f) {
; CHECK-LABEL: test_signed_v2f16_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
-; CHECK-NEXT: movi v1.2d, #0000000000000000
-; CHECK-NEXT: mov z2.h, w8
-; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, #0.0
-; CHECK-NEXT: fcmgt p0.h, p0/z, z0.h, z2.h
-; CHECK-NEXT: fcvtzu z1.d, p1/m, z0.h
-; CHECK-NEXT: mov z0.d, #0xffffffff
-; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: mov z1.d, #0xffffffff
+; CHECK-NEXT: fcvt z0.d, p0/m, z0.h
+; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
+; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d
; CHECK-NEXT: ret
%x = call <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f16.nxv2i32(<vscale x 2 x half> %f)
ret <vscale x 2 x i32> %x
@@ -380,14 +239,7 @@ define <vscale x 4 x i32> @test_signed_v4f16_v4i32(<vscale x 4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
-; CHECK-NEXT: movi v1.2d, #0000000000000000
-; CHECK-NEXT: mov z2.h, w8
-; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, #0.0
-; CHECK-NEXT: fcmgt p0.h, p0/z, z0.h, z2.h
-; CHECK-NEXT: fcvtzu z1.s, p1/m, z0.h
-; CHECK-NEXT: mov z1.s, p0/m, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: mov z0.d, z1.d
+; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.h
; CHECK-NEXT: ret
%x = call <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f16.nxv4i32(<vscale x 4 x half> %f)
ret <vscale x 4 x i32> %x
@@ -396,21 +248,13 @@ define <vscale x 4 x i32> @test_signed_v4f16_v4i32(<vscale x 4 x half> %f) {
define <vscale x 8 x i32> @test_signed_v8f16_v8i32(<vscale x 8 x half> %f) {
; CHECK-LABEL: test_signed_v8f16_v8i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: uunpklo z2.s, z0.h
-; CHECK-NEXT: uunpkhi z3.s, z0.h
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
+; CHECK-NEXT: uunpklo z1.s, z0.h
+; CHECK-NEXT: uunpkhi z2.s, z0.h
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: movi v0.2d, #0000000000000000
-; CHECK-NEXT: movi v1.2d, #0000000000000000
-; CHECK-NEXT: mov z4.h, w8
-; CHECK-NEXT: fcmge p1.h, p0/z, z2.h, #0.0
-; CHECK-NEXT: fcmge p2.h, p0/z, z3.h, #0.0
-; CHECK-NEXT: fcvtzu z0.s, p1/m, z2.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z2.h, z4.h
-; CHECK-NEXT: fcvtzu z1.s, p2/m, z3.h
-; CHECK-NEXT: fcmgt p0.h, p0/z, z3.h, z4.h
-; CHECK-NEXT: mov z0.s, p1/m, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: mov z1.s, p0/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: movprfx z0, z1
+; CHECK-NEXT: fcvtzu z0.s, p0/m, z1.h
+; CHECK-NEXT: movprfx z1, z2
+; CHECK-NEXT: fcvtzu z1.s, p0/m, z2.h
; CHECK-NEXT: ret
%x = call <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f16.nxv8i32(<vscale x 8 x half> %f)
ret <vscale x 8 x i32> %x
@@ -420,14 +264,10 @@ define <vscale x 4 x i16> @test_signed_v4f16_v4i16(<vscale x 4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
-; CHECK-NEXT: movi v1.2d, #0000000000000000
-; CHECK-NEXT: mov z2.h, w8
-; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, #0.0
-; CHECK-NEXT: fcmgt p0.h, p0/z, z0.h, z2.h
-; CHECK-NEXT: fcvtzu z1.s, p1/m, z0.h
-; CHECK-NEXT: mov z0.s, #65535 // =0xffff
-; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
+; CHECK-NEXT: mov z1.s, #65535 // =0xffff
+; CHECK-NEXT: fcvt z0.s, p0/m, z0.h
+; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s
+; CHECK-NEXT: umin z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT: ret
%x = call <vscale x 4 x i16> @llvm.fptoui.sat.nxv4f16.nxv4i16(<vscale x 4 x half> %f)
ret <vscale x 4 x i16> %x
@@ -437,14 +277,7 @@ define <vscale x 8 x i16> @test_signed_v8f16_v8i16(<vscale x 8 x half> %f) {
; CHECK-LABEL: test_signed_v8f16_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
-; CHECK-NEXT: movi v1.2d, #0000000000000000
-; CHECK-NEXT: mov z2.h, w8
-; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, #0.0
-; CHECK-NEXT: fcmgt p0.h, p0/z, z0.h, z2.h
-; CHECK-NEXT: fcvtzu z1.h, p1/m, z0.h
-; CHECK-NEXT: mov z1.h, p0/m, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: mov z0.d, z1.d
+; CHECK-NEXT: fcvtzu z0.h, p0/m, z0.h
; CHECK-NEXT: ret
%x = call <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f16.nxv8i16(<vscale x 8 x half> %f)
ret <vscale x 8 x i16> %x
@@ -454,14 +287,7 @@ define <vscale x 2 x i64> @test_signed_v2f16_v2i64(<vscale x 2 x half> %f) {
; CHECK-LABEL: test_signed_v2f16_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
-; CHECK-NEXT: movi v1.2d, #0000000000000000
-; CHECK-NEXT: mov z2.h, w8
-; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, #0.0
-; CHECK-NEXT: fcmgt p0.h, p0/z, z0.h, z2.h
-; CHECK-NEXT: fcvtzu z1.d, p1/m, z0.h
-; CHECK-NEXT: mov z1.d, p0/m, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: mov z0.d, z1.d
+; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.h
; CHECK-NEXT: ret
%x = call <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f16.nxv2i64(<vscale x 2 x half> %f)
ret <vscale x 2 x i64> %x
@@ -470,21 +296,13 @@ define <vscale x 2 x i64> @test_signed_v2f16_v2i64(<vscale x 2 x half> %f) {
define <vscale x 4 x i64> @test_signed_v4f16_v4i64(<vscale x 4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: uunpklo z2.d, z0.s
-; CHECK-NEXT: uunpkhi z3.d, z0.s
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
+; CHECK-NEXT: uunpklo z1.d, z0.s
+; CHECK-NEXT: uunpkhi z2.d, z0.s
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: movi v0.2d, #0000000000000000
-; CHECK-NEXT: movi v1.2d, #0000000000000000
-; CHECK-NEXT: mov z4.h, w8
-; CHECK-NEXT: fcmge p1.h, p0/z, z2.h, #0.0
-; CHECK-NEXT: fcmge p2.h, p0/z, z3.h, #0.0
-; CHECK-NEXT: fcvtzu z0.d, p1/m, z2.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z2.h, z4.h
-; CHECK-NEXT: fcvtzu z1.d, p2/m, z3.h
-; CHECK-NEXT: fcmgt p0.h, p0/z, z3.h, z4.h
-; CHECK-NEXT: mov z0.d, p1/m, #-1 // =0xffffffffffffffff
-; CHECK-NEXT: mov z1.d, p0/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: movprfx z0, z1
+; CHECK-NEXT: fcvtzu z0.d, p0/m, z1.h
+; CHECK-NEXT: movprfx z1, z2
+; CHECK-NEXT: fcvtzu z1.d, p0/m, z2.h
; CHECK-NEXT: ret
%x = call <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f16.nxv4i64(<vscale x 4 x half> %f)
ret <vscale x 4 x i64> %x
diff --git a/llvm/test/CodeGen/AArch64/sve-llrint.ll b/llvm/test/CodeGen/AArch64/sve-llrint.ll
index 436b09e93fa9e..8ecf378d5623d 100644
--- a/llvm/test/CodeGen/AArch64/sve-llrint.ll
+++ b/llvm/test/CodeGen/AArch64/sve-llrint.ll
@@ -5,18 +5,8 @@ define <vscale x 1 x i64> @llrint_v1i64_v1f16(<vscale x 1 x half> %x) {
; CHECK-LABEL: llrint_v1i64_v1f16:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z1.h, #-1025 // =0xfffffffffffffbff
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
; CHECK-NEXT: frintx z0.h, p0/m, z0.h
-; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.h, w8
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
-; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
; CHECK-NEXT: ret
%a = call <vscale x 1 x i64> @llvm.llrint.nxv1i64.nxv1f16(<vscale x 1 x half> %x)
ret <vscale x 1 x i64> %a
@@ -27,18 +17,8 @@ define <vscale x 2 x i64> @llrint_v1i64_v2f16(<vscale x 2 x half> %x) {
; CHECK-LABEL: llrint_v1i64_v2f16:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z1.h, #-1025 // =0xfffffffffffffbff
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
; CHECK-NEXT: frintx z0.h, p0/m, z0.h
-; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.h, w8
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
-; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
; CHECK-NEXT: ret
%a = call <vscale x 2 x i64> @llvm.llrint.nxv2i64.nxv2f16(<vscale x 2 x half> %x)
ret <vscale x 2 x i64> %a
@@ -50,27 +30,14 @@ define <vscale x 4 x i64> @llrint_v4i64_v4f16(<vscale x 4 x half> %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z1.d, z0.s
; CHECK-NEXT: uunpkhi z0.d, z0.s
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z2.h, #-1025 // =0xfffffffffffffbff
-; CHECK-NEXT: mov z3.d, #0x8000000000000000
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov z5.d, #0x7fffffffffffffff
; CHECK-NEXT: frintx z1.h, p0/m, z1.h
-; CHECK-NEXT: frintx z0.h, p0/m, z0.h
-; CHECK-NEXT: fcmge p1.h, p0/z, z1.h, z2.h
-; CHECK-NEXT: fcmge p2.h, p0/z, z0.h, z2.h
-; CHECK-NEXT: mov z2.h, w8
-; CHECK-NEXT: fcmuo p3.h, p0/z, z1.h, z1.h
-; CHECK-NEXT: fcvtzs z4.d, p1/m, z1.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z1.h, z2.h
-; CHECK-NEXT: fcvtzs z3.d, p2/m, z0.h
-; CHECK-NEXT: fcmgt p2.h, p0/z, z0.h, z2.h
-; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
-; CHECK-NEXT: sel z0.d, p1, z5.d, z4.d
-; CHECK-NEXT: sel z1.d, p2, z5.d, z3.d
-; CHECK-NEXT: mov z0.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
+; CHECK-NEXT: movprfx z2, z0
+; CHECK-NEXT: frintx z2.h, p0/m, z0.h
+; CHECK-NEXT: movprfx z0, z1
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.h
+; CHECK-NEXT: movprfx z1, z2
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z2.h
; CHECK-NEXT: ret
%a = call <vscale x 4 x i64> @llvm.llrint.nxv4i64.nxv4f16(<vscale x 4 x half> %x)
ret <vscale x 4 x i64> %a
@@ -80,62 +47,25 @@ declare <vscale x 4 x i64> @llvm.llrint.nxv4i64.nxv4f16(<vscale x 4 x half>)
define <vscale x 8 x i64> @llrint_v8i64_v8f16(<vscale x 8 x half> %x) {
; CHECK-LABEL: llrint_v8i64_v8f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: uunpklo z1.s, z0.h
; CHECK-NEXT: uunpkhi z0.s, z0.h
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z4.h, #-1025 // =0xfffffffffffffbff
-; CHECK-NEXT: mov z5.d, #0x8000000000000000
-; CHECK-NEXT: mov z6.d, #0x8000000000000000
-; CHECK-NEXT: mov z7.d, #0x8000000000000000
-; CHECK-NEXT: mov z25.d, #0x7fffffffffffffff
; CHECK-NEXT: uunpklo z2.d, z1.s
; CHECK-NEXT: uunpkhi z1.d, z1.s
; CHECK-NEXT: uunpklo z3.d, z0.s
; CHECK-NEXT: uunpkhi z0.d, z0.s
-; CHECK-NEXT: frintx z2.h, p0/m, z2.h
; CHECK-NEXT: frintx z1.h, p0/m, z1.h
+; CHECK-NEXT: frintx z2.h, p0/m, z2.h
; CHECK-NEXT: frintx z3.h, p0/m, z3.h
-; CHECK-NEXT: movprfx z24, z0
-; CHECK-NEXT: frintx z24.h, p0/m, z0.h
-; CHECK-NEXT: mov z0.h, w8
-; CHECK-NEXT: fcmge p1.h, p0/z, z2.h, z4.h
-; CHECK-NEXT: fcmge p2.h, p0/z, z1.h, z4.h
-; CHECK-NEXT: fcmge p3.h, p0/z, z3.h, z4.h
-; CHECK-NEXT: fcmgt p4.h, p0/z, z1.h, z0.h
-; CHECK-NEXT: fcvtzs z5.d, p1/m, z2.h
-; CHECK-NEXT: fcmge p1.h, p0/z, z24.h, z4.h
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z6.d, p2/m, z1.h
-; CHECK-NEXT: fcmgt p2.h, p0/z, z2.h, z0.h
-; CHECK-NEXT: fcvtzs z7.d, p3/m, z3.h
-; CHECK-NEXT: fcmgt p5.h, p0/z, z3.h, z0.h
-; CHECK-NEXT: fcmgt p6.h, p0/z, z24.h, z0.h
-; CHECK-NEXT: fcvtzs z4.d, p1/m, z24.h
-; CHECK-NEXT: fcmuo p3.h, p0/z, z2.h, z2.h
-; CHECK-NEXT: sel z0.d, p2, z25.d, z5.d
-; CHECK-NEXT: fcmuo p1.h, p0/z, z1.h, z1.h
-; CHECK-NEXT: sel z1.d, p4, z25.d, z6.d
-; CHECK-NEXT: sel z2.d, p5, z25.d, z7.d
-; CHECK-NEXT: fcmuo p2.h, p0/z, z3.h, z3.h
-; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p0.h, p0/z, z24.h, z24.h
-; CHECK-NEXT: sel z3.d, p6, z25.d, z4.d
-; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z0.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z1.d, p1/m, #0 // =0x0
-; CHECK-NEXT: mov z2.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z3.d, p0/m, #0 // =0x0
-; CHECK-NEXT: addvl sp, sp, #1
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: movprfx z4, z0
+; CHECK-NEXT: frintx z4.h, p0/m, z0.h
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.h
+; CHECK-NEXT: movprfx z0, z2
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z2.h
+; CHECK-NEXT: movprfx z2, z3
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z3.h
+; CHECK-NEXT: movprfx z3, z4
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z4.h
; CHECK-NEXT: ret
%a = call <vscale x 8 x i64> @llvm.llrint.nxv8i64.nxv8f16(<vscale x 8 x half> %x)
ret <vscale x 8 x i64> %a
@@ -145,110 +75,46 @@ declare <vscale x 8 x i64> @llvm.llrint.nxv8i64.nxv8f16(<vscale x 8 x half>)
define <vscale x 16 x i64> @llrint_v16i64_v16f16(<vscale x 16 x half> %x) {
; CHECK-LABEL: llrint_v16i64_v16f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: str p10, [sp, #1, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p9, [sp, #2, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p8, [sp, #3, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p7, [sp, #4, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: uunpkhi z3.s, z0.h
; CHECK-NEXT: uunpklo z2.s, z0.h
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
-; CHECK-NEXT: uunpklo z7.s, z1.h
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z0.h, #-1025 // =0xfffffffffffffbff
+; CHECK-NEXT: uunpkhi z0.s, z0.h
+; CHECK-NEXT: uunpklo z3.s, z1.h
; CHECK-NEXT: uunpkhi z1.s, z1.h
-; CHECK-NEXT: mov z5.d, #0x8000000000000000
-; CHECK-NEXT: mov z31.d, #0x8000000000000000
-; CHECK-NEXT: mov z29.h, w8
-; CHECK-NEXT: uunpkhi z25.d, z3.s
+; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: uunpklo z4.d, z2.s
-; CHECK-NEXT: uunpkhi z6.d, z2.s
-; CHECK-NEXT: uunpklo z24.d, z3.s
-; CHECK-NEXT: uunpklo z26.d, z7.s
-; CHECK-NEXT: uunpkhi z7.d, z7.s
-; CHECK-NEXT: uunpklo z30.d, z1.s
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z3.d, #0x8000000000000000
+; CHECK-NEXT: uunpkhi z2.d, z2.s
+; CHECK-NEXT: uunpklo z5.d, z0.s
+; CHECK-NEXT: uunpkhi z0.d, z0.s
+; CHECK-NEXT: uunpklo z6.d, z3.s
+; CHECK-NEXT: uunpkhi z3.d, z3.s
+; CHECK-NEXT: uunpklo z7.d, z1.s
; CHECK-NEXT: uunpkhi z1.d, z1.s
-; CHECK-NEXT: movprfx z27, z4
-; CHECK-NEXT: frintx z27.h, p0/m, z4.h
-; CHECK-NEXT: movprfx z28, z6
-; CHECK-NEXT: frintx z28.h, p0/m, z6.h
-; CHECK-NEXT: frintx z25.h, p0/m, z25.h
-; CHECK-NEXT: frintx z24.h, p0/m, z24.h
-; CHECK-NEXT: frintx z26.h, p0/m, z26.h
+; CHECK-NEXT: frintx z4.h, p0/m, z4.h
+; CHECK-NEXT: frintx z2.h, p0/m, z2.h
+; CHECK-NEXT: frintx z5.h, p0/m, z5.h
+; CHECK-NEXT: movprfx z24, z0
+; CHECK-NEXT: frintx z24.h, p0/m, z0.h
+; CHECK-NEXT: frintx z6.h, p0/m, z6.h
+; CHECK-NEXT: movprfx z25, z3
+; CHECK-NEXT: frintx z25.h, p0/m, z3.h
; CHECK-NEXT: frintx z7.h, p0/m, z7.h
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov z6.d, #0x8000000000000000
-; CHECK-NEXT: frintx z30.h, p0/m, z30.h
-; CHECK-NEXT: fcmge p4.h, p0/z, z25.h, z0.h
-; CHECK-NEXT: fcmge p1.h, p0/z, z27.h, z0.h
-; CHECK-NEXT: fcmge p2.h, p0/z, z28.h, z0.h
-; CHECK-NEXT: fcmge p3.h, p0/z, z24.h, z0.h
-; CHECK-NEXT: fcvtzs z5.d, p4/m, z25.h
-; CHECK-NEXT: fcmge p5.h, p0/z, z26.h, z0.h
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z27.h
-; CHECK-NEXT: fcvtzs z3.d, p2/m, z28.h
-; CHECK-NEXT: fcmge p4.h, p0/z, z7.h, z0.h
-; CHECK-NEXT: fcvtzs z4.d, p3/m, z24.h
-; CHECK-NEXT: fcmgt p3.h, p0/z, z27.h, z29.h
-; CHECK-NEXT: fcvtzs z6.d, p5/m, z26.h
-; CHECK-NEXT: fcmuo p1.h, p0/z, z27.h, z27.h
-; CHECK-NEXT: mov z27.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z31.d, p4/m, z7.h
-; CHECK-NEXT: fcmgt p5.h, p0/z, z28.h, z29.h
-; CHECK-NEXT: fcmuo p2.h, p0/z, z28.h, z28.h
-; CHECK-NEXT: movprfx z28, z1
-; CHECK-NEXT: frintx z28.h, p0/m, z1.h
-; CHECK-NEXT: fcmge p4.h, p0/z, z30.h, z0.h
-; CHECK-NEXT: fcmgt p6.h, p0/z, z24.h, z29.h
-; CHECK-NEXT: fcmuo p7.h, p0/z, z24.h, z24.h
-; CHECK-NEXT: mov z24.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmgt p8.h, p0/z, z25.h, z29.h
-; CHECK-NEXT: fcvtzs z27.d, p4/m, z30.h
-; CHECK-NEXT: fcmuo p10.h, p0/z, z25.h, z25.h
-; CHECK-NEXT: mov z25.d, #0x8000000000000000
-; CHECK-NEXT: sel z1.d, p5, z24.d, z3.d
-; CHECK-NEXT: fcmge p4.h, p0/z, z28.h, z0.h
-; CHECK-NEXT: sel z0.d, p3, z24.d, z2.d
-; CHECK-NEXT: sel z2.d, p6, z24.d, z4.d
-; CHECK-NEXT: sel z3.d, p8, z24.d, z5.d
-; CHECK-NEXT: mov z1.d, p2/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p9.h, p0/z, z26.h, z29.h
-; CHECK-NEXT: mov z2.d, p7/m, #0 // =0x0
-; CHECK-NEXT: ldr p7, [sp, #4, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcvtzs z25.d, p4/m, z28.h
-; CHECK-NEXT: mov z3.d, p10/m, #0 // =0x0
-; CHECK-NEXT: ldr p10, [sp, #1, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z0.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p5.h, p0/z, z7.h, z29.h
-; CHECK-NEXT: fcmgt p6.h, p0/z, z30.h, z29.h
-; CHECK-NEXT: sel z4.d, p9, z24.d, z6.d
-; CHECK-NEXT: fcmgt p4.h, p0/z, z28.h, z29.h
-; CHECK-NEXT: fcmuo p8.h, p0/z, z7.h, z7.h
-; CHECK-NEXT: sel z5.d, p5, z24.d, z31.d
-; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p9.h, p0/z, z30.h, z30.h
-; CHECK-NEXT: sel z6.d, p6, z24.d, z27.d
-; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload
-; CHECK-NEXT: sel z7.d, p4, z24.d, z25.d
-; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p3.h, p0/z, z26.h, z26.h
-; CHECK-NEXT: mov z5.d, p8/m, #0 // =0x0
-; CHECK-NEXT: ldr p8, [sp, #3, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p0.h, p0/z, z28.h, z28.h
-; CHECK-NEXT: mov z6.d, p9/m, #0 // =0x0
-; CHECK-NEXT: ldr p9, [sp, #2, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z4.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z7.d, p0/m, #0 // =0x0
-; CHECK-NEXT: addvl sp, sp, #1
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: movprfx z26, z1
+; CHECK-NEXT: frintx z26.h, p0/m, z1.h
+; CHECK-NEXT: movprfx z0, z4
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z4.h
+; CHECK-NEXT: movprfx z1, z2
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z2.h
+; CHECK-NEXT: movprfx z2, z5
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z5.h
+; CHECK-NEXT: movprfx z3, z24
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z24.h
+; CHECK-NEXT: movprfx z4, z6
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z6.h
+; CHECK-NEXT: movprfx z5, z25
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z25.h
+; CHECK-NEXT: movprfx z6, z7
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z7.h
+; CHECK-NEXT: movprfx z7, z26
+; CHECK-NEXT: fcvtzs z7.d, p0/m, z26.h
; CHECK-NEXT: ret
%a = call <vscale x 16 x i64> @llvm.llrint.nxv16i64.nxv16f16(<vscale x 16 x half> %x)
ret <vscale x 16 x i64> %a
@@ -258,252 +124,79 @@ declare <vscale x 16 x i64> @llvm.llrint.nxv16i64.nxv16f16(<vscale x 16 x half>)
define <vscale x 32 x i64> @llrint_v32i64_v32f16(<vscale x 32 x half> %x) {
; CHECK-LABEL: llrint_v32i64_v32f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-18
-; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p11, [sp, #8, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p10, [sp, #9, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p9, [sp, #10, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p8, [sp, #11, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p7, [sp, #12, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p6, [sp, #13, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #14, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #15, mul vl] // 2-byte Spill
-; CHECK-NEXT: str z23, [sp, #2, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z22, [sp, #3, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z21, [sp, #4, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z20, [sp, #5, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z19, [sp, #6, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z18, [sp, #7, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z17, [sp, #8, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z16, [sp, #9, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0a, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x11, 0x90, 0x01, 0x1e, 0x22 // sp + 16 + 144 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x40, 0x1c // $d9 @ cfa - 16 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x68, 0x1e, 0x22, 0x40, 0x1c // $d10 @ cfa - 24 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4b, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x60, 0x1e, 0x22, 0x40, 0x1c // $d11 @ cfa - 32 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4c, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x58, 0x1e, 0x22, 0x40, 0x1c // $d12 @ cfa - 40 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4d, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x50, 0x1e, 0x22, 0x40, 0x1c // $d13 @ cfa - 48 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4e, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x48, 0x1e, 0x22, 0x40, 0x1c // $d14 @ cfa - 56 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4f, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x40, 0x1e, 0x22, 0x40, 0x1c // $d15 @ cfa - 64 * VG - 16
-; CHECK-NEXT: uunpklo z4.s, z0.h
-; CHECK-NEXT: uunpkhi z0.s, z0.h
-; CHECK-NEXT: mov w9, #31743 // =0x7bff
-; CHECK-NEXT: uunpklo z5.s, z1.h
+; CHECK-NEXT: uunpkhi z4.s, z3.h
+; CHECK-NEXT: uunpklo z3.s, z3.h
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z28.h, #-1025 // =0xfffffffffffffbff
-; CHECK-NEXT: uunpkhi z29.s, z1.h
-; CHECK-NEXT: mov z7.d, #0x8000000000000000
-; CHECK-NEXT: uunpklo z13.s, z2.h
-; CHECK-NEXT: mov z9.d, #0x8000000000000000
-; CHECK-NEXT: uunpkhi z14.s, z2.h
-; CHECK-NEXT: uunpkhi z17.s, z3.h
-; CHECK-NEXT: uunpklo z6.d, z4.s
-; CHECK-NEXT: uunpkhi z4.d, z4.s
-; CHECK-NEXT: uunpklo z27.d, z0.s
-; CHECK-NEXT: uunpklo z31.d, z5.s
-; CHECK-NEXT: uunpkhi z8.d, z5.s
-; CHECK-NEXT: uunpkhi z30.d, z0.s
-; CHECK-NEXT: uunpkhi z11.d, z29.s
-; CHECK-NEXT: uunpklo z10.d, z29.s
-; CHECK-NEXT: uunpklo z15.s, z3.h
-; CHECK-NEXT: uunpklo z16.d, z14.s
-; CHECK-NEXT: uunpkhi z14.d, z14.s
-; CHECK-NEXT: mov z24.d, #0x8000000000000000
-; CHECK-NEXT: movprfx z5, z27
-; CHECK-NEXT: frintx z5.h, p0/m, z27.h
-; CHECK-NEXT: movprfx z1, z6
-; CHECK-NEXT: frintx z1.h, p0/m, z6.h
+; CHECK-NEXT: uunpkhi z7.s, z2.h
+; CHECK-NEXT: uunpklo z2.s, z2.h
+; CHECK-NEXT: uunpkhi z24.s, z0.h
+; CHECK-NEXT: uunpkhi z25.s, z1.h
+; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: uunpklo z1.s, z1.h
+; CHECK-NEXT: uunpkhi z5.d, z4.s
+; CHECK-NEXT: uunpklo z4.d, z4.s
+; CHECK-NEXT: uunpkhi z6.d, z3.s
+; CHECK-NEXT: uunpklo z3.d, z3.s
+; CHECK-NEXT: uunpkhi z26.d, z7.s
+; CHECK-NEXT: uunpklo z7.d, z7.s
+; CHECK-NEXT: uunpkhi z27.d, z2.s
+; CHECK-NEXT: uunpkhi z28.d, z24.s
+; CHECK-NEXT: uunpklo z2.d, z2.s
+; CHECK-NEXT: uunpkhi z29.d, z25.s
+; CHECK-NEXT: uunpklo z25.d, z25.s
+; CHECK-NEXT: frintx z5.h, p0/m, z5.h
; CHECK-NEXT: frintx z4.h, p0/m, z4.h
-; CHECK-NEXT: movprfx z12, z31
-; CHECK-NEXT: frintx z12.h, p0/m, z31.h
-; CHECK-NEXT: movprfx z27, z8
-; CHECK-NEXT: frintx z27.h, p0/m, z8.h
-; CHECK-NEXT: movprfx z6, z30
-; CHECK-NEXT: frintx z6.h, p0/m, z30.h
-; CHECK-NEXT: movprfx z31, z10
-; CHECK-NEXT: frintx z31.h, p0/m, z10.h
-; CHECK-NEXT: mov z8.d, #0x8000000000000000
-; CHECK-NEXT: frintx z11.h, p0/m, z11.h
-; CHECK-NEXT: movprfx z3, z16
-; CHECK-NEXT: frintx z3.h, p0/m, z16.h
-; CHECK-NEXT: mov z30.h, w9
-; CHECK-NEXT: uunpklo z10.d, z13.s
-; CHECK-NEXT: uunpkhi z13.d, z13.s
-; CHECK-NEXT: uunpkhi z20.d, z15.s
-; CHECK-NEXT: uunpklo z16.d, z17.s
-; CHECK-NEXT: mov z25.d, #0x8000000000000000
-; CHECK-NEXT: mov z0.d, #0x8000000000000000
-; CHECK-NEXT: mov z18.d, #0x8000000000000000
-; CHECK-NEXT: uunpklo z15.d, z15.s
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z21.d, #0x8000000000000000
-; CHECK-NEXT: frintx z10.h, p0/m, z10.h
-; CHECK-NEXT: mov z26.d, #0x8000000000000000
-; CHECK-NEXT: mov z29.d, #0x7fffffffffffffff
-; CHECK-NEXT: movprfx z19, z13
-; CHECK-NEXT: frintx z19.h, p0/m, z13.h
-; CHECK-NEXT: movprfx z13, z14
-; CHECK-NEXT: frintx z13.h, p0/m, z14.h
-; CHECK-NEXT: frintx z20.h, p0/m, z20.h
-; CHECK-NEXT: frintx z16.h, p0/m, z16.h
-; CHECK-NEXT: mov z22.d, #0x8000000000000000
-; CHECK-NEXT: mov z23.d, #0x8000000000000000
-; CHECK-NEXT: frintx z15.h, p0/m, z15.h
-; CHECK-NEXT: mov z14.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p4.h, p0/z, z4.h, z28.h
-; CHECK-NEXT: fcmge p2.h, p0/z, z12.h, z28.h
-; CHECK-NEXT: fcmgt p9.h, p0/z, z12.h, z30.h
-; CHECK-NEXT: fcmuo p8.h, p0/z, z12.h, z12.h
-; CHECK-NEXT: fcvtzs z7.d, p4/m, z4.h
-; CHECK-NEXT: fcvtzs z8.d, p2/m, z12.h
-; CHECK-NEXT: mov z12.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p4.h, p0/z, z27.h, z28.h
-; CHECK-NEXT: fcmuo p10.h, p0/z, z11.h, z11.h
-; CHECK-NEXT: fcmge p3.h, p0/z, z5.h, z28.h
-; CHECK-NEXT: mov z8.d, p9/m, z29.d
-; CHECK-NEXT: fcvtzs z9.d, p4/m, z27.h
-; CHECK-NEXT: fcmge p4.h, p0/z, z11.h, z28.h
-; CHECK-NEXT: fcvtzs z24.d, p3/m, z5.h
-; CHECK-NEXT: mov z8.d, p8/m, #0 // =0x0
-; CHECK-NEXT: fcmge p1.h, p0/z, z6.h, z28.h
-; CHECK-NEXT: fcmge p5.h, p0/z, z1.h, z28.h
-; CHECK-NEXT: str z8, [x8, #4, mul vl]
-; CHECK-NEXT: fcvtzs z12.d, p4/m, z11.h
-; CHECK-NEXT: fcmgt p4.h, p0/z, z11.h, z30.h
-; CHECK-NEXT: uunpkhi z11.d, z17.s
-; CHECK-NEXT: mov z17.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z25.d, p1/m, z6.h
-; CHECK-NEXT: fcvtzs z0.d, p5/m, z1.h
-; CHECK-NEXT: fcmge p6.h, p0/z, z10.h, z28.h
-; CHECK-NEXT: frintx z11.h, p0/m, z11.h
-; CHECK-NEXT: fcmge p3.h, p0/z, z31.h, z28.h
-; CHECK-NEXT: fcmge p1.h, p0/z, z13.h, z28.h
-; CHECK-NEXT: fcvtzs z18.d, p6/m, z10.h
-; CHECK-NEXT: fcmgt p11.h, p0/z, z10.h, z30.h
-; CHECK-NEXT: fcvtzs z2.d, p3/m, z31.h
-; CHECK-NEXT: fcmge p5.h, p0/z, z11.h, z28.h
-; CHECK-NEXT: fcvtzs z21.d, p1/m, z13.h
-; CHECK-NEXT: fcmge p2.h, p0/z, z20.h, z28.h
-; CHECK-NEXT: fcmge p3.h, p0/z, z16.h, z28.h
-; CHECK-NEXT: fcmuo p1.h, p0/z, z10.h, z10.h
-; CHECK-NEXT: sel z10.d, p4, z29.d, z12.d
-; CHECK-NEXT: sel z12.d, p11, z29.d, z18.d
-; CHECK-NEXT: fcvtzs z26.d, p5/m, z11.h
-; CHECK-NEXT: fcvtzs z22.d, p2/m, z20.h
-; CHECK-NEXT: fcvtzs z23.d, p3/m, z16.h
-; CHECK-NEXT: mov z10.d, p10/m, #0 // =0x0
-; CHECK-NEXT: mov z12.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p4.h, p0/z, z11.h, z30.h
-; CHECK-NEXT: fcmge p6.h, p0/z, z19.h, z28.h
-; CHECK-NEXT: str z10, [x8, #7, mul vl]
-; CHECK-NEXT: fcmge p7.h, p0/z, z3.h, z28.h
-; CHECK-NEXT: str z12, [x8, #8, mul vl]
-; CHECK-NEXT: fcmge p2.h, p0/z, z15.h, z28.h
-; CHECK-NEXT: mov z28.d, #0x8000000000000000
-; CHECK-NEXT: mov z26.d, p4/m, z29.d
-; CHECK-NEXT: fcmgt p5.h, p0/z, z16.h, z30.h
-; CHECK-NEXT: fcvtzs z14.d, p6/m, z19.h
-; CHECK-NEXT: fcvtzs z17.d, p7/m, z3.h
-; CHECK-NEXT: fcmgt p3.h, p0/z, z20.h, z30.h
-; CHECK-NEXT: fcvtzs z28.d, p2/m, z15.h
-; CHECK-NEXT: fcmuo p1.h, p0/z, z11.h, z11.h
-; CHECK-NEXT: sel z11.d, p5, z29.d, z23.d
-; CHECK-NEXT: fcmuo p2.h, p0/z, z16.h, z16.h
-; CHECK-NEXT: fcmgt p4.h, p0/z, z19.h, z30.h
-; CHECK-NEXT: sel z16.d, p3, z29.d, z22.d
-; CHECK-NEXT: mov z26.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p3.h, p0/z, z15.h, z30.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z13.h, z30.h
-; CHECK-NEXT: mov z11.d, p2/m, #0 // =0x0
-; CHECK-NEXT: str z26, [x8, #15, mul vl]
-; CHECK-NEXT: sel z26.d, p4, z29.d, z14.d
-; CHECK-NEXT: fcmuo p6.h, p0/z, z20.h, z20.h
-; CHECK-NEXT: fcmgt p2.h, p0/z, z3.h, z30.h
-; CHECK-NEXT: str z11, [x8, #14, mul vl]
-; CHECK-NEXT: mov z28.d, p3/m, z29.d
-; CHECK-NEXT: fcmuo p4.h, p0/z, z13.h, z13.h
-; CHECK-NEXT: fcmuo p3.h, p0/z, z3.h, z3.h
-; CHECK-NEXT: sel z3.d, p1, z29.d, z21.d
-; CHECK-NEXT: mov z16.d, p6/m, #0 // =0x0
-; CHECK-NEXT: sel z11.d, p2, z29.d, z17.d
-; CHECK-NEXT: fcmgt p12.h, p0/z, z27.h, z30.h
-; CHECK-NEXT: mov z3.d, p4/m, #0 // =0x0
-; CHECK-NEXT: str z16, [x8, #13, mul vl]
-; CHECK-NEXT: fcmuo p6.h, p0/z, z15.h, z15.h
-; CHECK-NEXT: mov z11.d, p3/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p1.h, p0/z, z4.h, z30.h
-; CHECK-NEXT: str z3, [x8, #11, mul vl]
-; CHECK-NEXT: fcmuo p5.h, p0/z, z19.h, z19.h
-; CHECK-NEXT: mov z9.d, p12/m, z29.d
-; CHECK-NEXT: str z11, [x8, #10, mul vl]
-; CHECK-NEXT: fcmgt p2.h, p0/z, z5.h, z30.h
-; CHECK-NEXT: mov z28.d, p6/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p4.h, p0/z, z6.h, z30.h
-; CHECK-NEXT: sel z3.d, p1, z29.d, z7.d
-; CHECK-NEXT: mov z26.d, p5/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p3.h, p0/z, z27.h, z27.h
-; CHECK-NEXT: str z28, [x8, #12, mul vl]
-; CHECK-NEXT: fcmgt p6.h, p0/z, z31.h, z30.h
-; CHECK-NEXT: sel z7.d, p2, z29.d, z24.d
-; CHECK-NEXT: str z26, [x8, #9, mul vl]
-; CHECK-NEXT: sel z24.d, p4, z29.d, z25.d
-; CHECK-NEXT: fcmgt p1.h, p0/z, z1.h, z30.h
-; CHECK-NEXT: fcmuo p5.h, p0/z, z31.h, z31.h
-; CHECK-NEXT: mov z9.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z2.d, p6/m, z29.d
-; CHECK-NEXT: fcmuo p2.h, p0/z, z6.h, z6.h
-; CHECK-NEXT: fcmuo p3.h, p0/z, z5.h, z5.h
-; CHECK-NEXT: str z9, [x8, #5, mul vl]
-; CHECK-NEXT: mov z0.d, p1/m, z29.d
-; CHECK-NEXT: mov z2.d, p5/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p4.h, p0/z, z4.h, z4.h
-; CHECK-NEXT: fcmuo p0.h, p0/z, z1.h, z1.h
-; CHECK-NEXT: mov z24.d, p2/m, #0 // =0x0
-; CHECK-NEXT: str z2, [x8, #6, mul vl]
-; CHECK-NEXT: mov z7.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z3.d, p4/m, #0 // =0x0
-; CHECK-NEXT: str z24, [x8, #3, mul vl]
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
-; CHECK-NEXT: str z7, [x8, #2, mul vl]
-; CHECK-NEXT: str z3, [x8, #1, mul vl]
+; CHECK-NEXT: frintx z6.h, p0/m, z6.h
+; CHECK-NEXT: frintx z3.h, p0/m, z3.h
+; CHECK-NEXT: frintx z26.h, p0/m, z26.h
+; CHECK-NEXT: frintx z7.h, p0/m, z7.h
+; CHECK-NEXT: frintx z27.h, p0/m, z27.h
+; CHECK-NEXT: frintx z2.h, p0/m, z2.h
+; CHECK-NEXT: frintx z28.h, p0/m, z28.h
+; CHECK-NEXT: frintx z29.h, p0/m, z29.h
+; CHECK-NEXT: frintx z25.h, p0/m, z25.h
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.h
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.h
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.h
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.h
+; CHECK-NEXT: fcvtzs z26.d, p0/m, z26.h
+; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.h
+; CHECK-NEXT: fcvtzs z27.d, p0/m, z27.h
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.h
+; CHECK-NEXT: fcvtzs z28.d, p0/m, z28.h
+; CHECK-NEXT: fcvtzs z29.d, p0/m, z29.h
+; CHECK-NEXT: fcvtzs z25.d, p0/m, z25.h
+; CHECK-NEXT: str z5, [x8, #15, mul vl]
+; CHECK-NEXT: uunpkhi z5.d, z1.s
+; CHECK-NEXT: uunpklo z1.d, z1.s
+; CHECK-NEXT: str z4, [x8, #14, mul vl]
+; CHECK-NEXT: uunpkhi z4.d, z0.s
+; CHECK-NEXT: uunpklo z0.d, z0.s
+; CHECK-NEXT: str z3, [x8, #12, mul vl]
+; CHECK-NEXT: uunpklo z3.d, z24.s
+; CHECK-NEXT: str z6, [x8, #13, mul vl]
+; CHECK-NEXT: str z26, [x8, #11, mul vl]
+; CHECK-NEXT: frintx z5.h, p0/m, z5.h
+; CHECK-NEXT: frintx z1.h, p0/m, z1.h
+; CHECK-NEXT: str z7, [x8, #10, mul vl]
+; CHECK-NEXT: frintx z4.h, p0/m, z4.h
+; CHECK-NEXT: frintx z0.h, p0/m, z0.h
+; CHECK-NEXT: str z27, [x8, #9, mul vl]
+; CHECK-NEXT: frintx z3.h, p0/m, z3.h
+; CHECK-NEXT: str z2, [x8, #8, mul vl]
+; CHECK-NEXT: str z29, [x8, #7, mul vl]
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.h
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.h
+; CHECK-NEXT: str z25, [x8, #6, mul vl]
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.h
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
+; CHECK-NEXT: str z28, [x8, #3, mul vl]
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.h
+; CHECK-NEXT: str z5, [x8, #5, mul vl]
+; CHECK-NEXT: str z1, [x8, #4, mul vl]
+; CHECK-NEXT: str z3, [x8, #2, mul vl]
+; CHECK-NEXT: str z4, [x8, #1, mul vl]
; CHECK-NEXT: str z0, [x8]
-; CHECK-NEXT: ldr z23, [sp, #2, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z22, [sp, #3, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z21, [sp, #4, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z20, [sp, #5, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z19, [sp, #6, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z18, [sp, #7, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z17, [sp, #8, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z16, [sp, #9, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z15, [sp, #10, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z14, [sp, #11, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p7, [sp, #12, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p6, [sp, #13, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p5, [sp, #14, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p4, [sp, #15, mul vl] // 2-byte Reload
-; CHECK-NEXT: addvl sp, sp, #18
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
%a = call <vscale x 32 x i64> @llvm.llrint.nxv32i64.nxv32f16(<vscale x 32 x half> %x)
ret <vscale x 32 x i64> %a
@@ -514,19 +207,8 @@ define <vscale x 1 x i64> @llrint_v1i64_v1f32(<vscale x 1 x float> %x) {
; CHECK-LABEL: llrint_v1i64_v1f32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov w8, #-553648128 // =0xdf000000
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z1.s, w8
-; CHECK-NEXT: mov w8, #1593835519 // =0x5effffff
; CHECK-NEXT: frintx z0.s, p0/m, z0.s
-; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z1.s
-; CHECK-NEXT: mov z1.s, w8
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.s
-; CHECK-NEXT: fcmgt p1.s, p0/z, z0.s, z1.s
-; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
; CHECK-NEXT: ret
%a = call <vscale x 1 x i64> @llvm.llrint.nxv1i64.nxv1f32(<vscale x 1 x float> %x)
ret <vscale x 1 x i64> %a
@@ -537,19 +219,8 @@ define <vscale x 2 x i64> @llrint_v2i64_v2f32(<vscale x 2 x float> %x) {
; CHECK-LABEL: llrint_v2i64_v2f32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov w8, #-553648128 // =0xdf000000
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z1.s, w8
-; CHECK-NEXT: mov w8, #1593835519 // =0x5effffff
; CHECK-NEXT: frintx z0.s, p0/m, z0.s
-; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z1.s
-; CHECK-NEXT: mov z1.s, w8
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.s
-; CHECK-NEXT: fcmgt p1.s, p0/z, z0.s, z1.s
-; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
; CHECK-NEXT: ret
%a = call <vscale x 2 x i64> @llvm.llrint.nxv2i64.nxv2f32(<vscale x 2 x float> %x)
ret <vscale x 2 x i64> %a
@@ -561,28 +232,14 @@ define <vscale x 4 x i64> @llrint_v4i64_v4f32(<vscale x 4 x float> %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z1.d, z0.s
; CHECK-NEXT: uunpkhi z0.d, z0.s
-; CHECK-NEXT: mov w8, #-553648128 // =0xdf000000
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: mov w8, #1593835519 // =0x5effffff
-; CHECK-NEXT: mov z3.d, #0x8000000000000000
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov z5.d, #0x7fffffffffffffff
; CHECK-NEXT: frintx z1.s, p0/m, z1.s
-; CHECK-NEXT: frintx z0.s, p0/m, z0.s
-; CHECK-NEXT: fcmge p1.s, p0/z, z1.s, z2.s
-; CHECK-NEXT: fcmge p2.s, p0/z, z0.s, z2.s
-; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: fcmuo p3.s, p0/z, z1.s, z1.s
-; CHECK-NEXT: fcvtzs z4.d, p1/m, z1.s
-; CHECK-NEXT: fcmgt p1.s, p0/z, z1.s, z2.s
-; CHECK-NEXT: fcvtzs z3.d, p2/m, z0.s
-; CHECK-NEXT: fcmgt p2.s, p0/z, z0.s, z2.s
-; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: sel z0.d, p1, z5.d, z4.d
-; CHECK-NEXT: sel z1.d, p2, z5.d, z3.d
-; CHECK-NEXT: mov z0.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
+; CHECK-NEXT: movprfx z2, z0
+; CHECK-NEXT: frintx z2.s, p0/m, z0.s
+; CHECK-NEXT: movprfx z0, z1
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.s
+; CHECK-NEXT: movprfx z1, z2
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z2.s
; CHECK-NEXT: ret
%a = call <vscale x 4 x i64> @llvm.llrint.nxv4i64.nxv4f32(<vscale x 4 x float> %x)
ret <vscale x 4 x i64> %a
@@ -592,61 +249,25 @@ declare <vscale x 4 x i64> @llvm.llrint.nxv4i64.nxv4f32(<vscale x 4 x float>)
define <vscale x 8 x i64> @llrint_v8i64_v8f32(<vscale x 8 x float> %x) {
; CHECK-LABEL: llrint_v8i64_v8f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: uunpklo z2.d, z0.s
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov w8, #-553648128 // =0xdf000000
; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: uunpklo z3.d, z1.s
; CHECK-NEXT: uunpkhi z1.d, z1.s
-; CHECK-NEXT: mov z4.s, w8
-; CHECK-NEXT: mov w8, #1593835519 // =0x5effffff
-; CHECK-NEXT: mov z5.d, #0x8000000000000000
-; CHECK-NEXT: mov z7.d, #0x8000000000000000
-; CHECK-NEXT: mov z24.d, #0x8000000000000000
-; CHECK-NEXT: mov z25.s, w8
+; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: frintx z2.s, p0/m, z2.s
-; CHECK-NEXT: mov z26.d, #0x8000000000000000
-; CHECK-NEXT: movprfx z6, z0
-; CHECK-NEXT: frintx z6.s, p0/m, z0.s
+; CHECK-NEXT: movprfx z4, z0
+; CHECK-NEXT: frintx z4.s, p0/m, z0.s
; CHECK-NEXT: frintx z3.s, p0/m, z3.s
-; CHECK-NEXT: frintx z1.s, p0/m, z1.s
-; CHECK-NEXT: fcmge p1.s, p0/z, z2.s, z4.s
-; CHECK-NEXT: fcmge p2.s, p0/z, z6.s, z4.s
-; CHECK-NEXT: fcmge p3.s, p0/z, z3.s, z4.s
-; CHECK-NEXT: fcmgt p4.s, p0/z, z2.s, z25.s
-; CHECK-NEXT: fcvtzs z5.d, p1/m, z2.s
-; CHECK-NEXT: fcmge p1.s, p0/z, z1.s, z4.s
-; CHECK-NEXT: mov z4.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcvtzs z7.d, p2/m, z6.s
-; CHECK-NEXT: fcvtzs z24.d, p3/m, z3.s
-; CHECK-NEXT: fcmgt p3.s, p0/z, z6.s, z25.s
-; CHECK-NEXT: fcmgt p5.s, p0/z, z3.s, z25.s
-; CHECK-NEXT: fcvtzs z26.d, p1/m, z1.s
-; CHECK-NEXT: sel z0.d, p4, z4.d, z5.d
-; CHECK-NEXT: fcmgt p1.s, p0/z, z1.s, z25.s
-; CHECK-NEXT: fcmuo p4.s, p0/z, z6.s, z6.s
-; CHECK-NEXT: fcmuo p6.s, p0/z, z3.s, z3.s
-; CHECK-NEXT: fcmuo p2.s, p0/z, z2.s, z2.s
-; CHECK-NEXT: sel z2.d, p5, z4.d, z24.d
-; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p0.s, p0/z, z1.s, z1.s
-; CHECK-NEXT: sel z1.d, p3, z4.d, z7.d
-; CHECK-NEXT: sel z3.d, p1, z4.d, z26.d
-; CHECK-NEXT: mov z2.d, p6/m, #0 // =0x0
-; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z1.d, p4/m, #0 // =0x0
-; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z0.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z3.d, p0/m, #0 // =0x0
-; CHECK-NEXT: addvl sp, sp, #1
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: movprfx z5, z1
+; CHECK-NEXT: frintx z5.s, p0/m, z1.s
+; CHECK-NEXT: movprfx z0, z2
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z2.s
+; CHECK-NEXT: movprfx z1, z4
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z4.s
+; CHECK-NEXT: movprfx z2, z3
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z3.s
+; CHECK-NEXT: movprfx z3, z5
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z5.s
; CHECK-NEXT: ret
%a = call <vscale x 8 x i64> @llvm.llrint.nxv8i64.nxv8f32(<vscale x 8 x float> %x)
ret <vscale x 8 x i64> %a
@@ -656,114 +277,43 @@ declare <vscale x 8 x i64> @llvm.llrint.nxv8i64.nxv8f32(<vscale x 8 x float>)
define <vscale x 16 x i64> @llrint_v16i64_v16f32(<vscale x 16 x float> %x) {
; CHECK-LABEL: llrint_v16i64_v16f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-3
-; CHECK-NEXT: str p10, [sp, #1, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p9, [sp, #2, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p8, [sp, #3, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p7, [sp, #4, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: str z9, [sp, #1, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z8, [sp, #2, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x48, 0x1e, 0x22 // sp + 16 + 24 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x40, 0x1c // $d9 @ cfa - 16 * VG - 16
; CHECK-NEXT: uunpklo z4.d, z0.s
-; CHECK-NEXT: uunpkhi z5.d, z0.s
-; CHECK-NEXT: mov w8, #-553648128 // =0xdf000000
-; CHECK-NEXT: uunpkhi z7.d, z1.s
-; CHECK-NEXT: uunpklo z24.d, z2.s
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: uunpklo z6.d, z1.s
+; CHECK-NEXT: uunpkhi z0.d, z0.s
+; CHECK-NEXT: uunpklo z5.d, z1.s
+; CHECK-NEXT: uunpkhi z1.d, z1.s
+; CHECK-NEXT: uunpklo z6.d, z2.s
; CHECK-NEXT: uunpkhi z2.d, z2.s
-; CHECK-NEXT: mov z0.d, #0x8000000000000000
-; CHECK-NEXT: mov z1.d, #0x8000000000000000
-; CHECK-NEXT: mov z27.d, #0x8000000000000000
-; CHECK-NEXT: mov z28.d, #0x8000000000000000
-; CHECK-NEXT: movprfx z25, z4
-; CHECK-NEXT: frintx z25.s, p0/m, z4.s
+; CHECK-NEXT: uunpklo z7.d, z3.s
+; CHECK-NEXT: uunpkhi z3.d, z3.s
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: frintx z4.s, p0/m, z4.s
+; CHECK-NEXT: movprfx z24, z0
+; CHECK-NEXT: frintx z24.s, p0/m, z0.s
; CHECK-NEXT: frintx z5.s, p0/m, z5.s
-; CHECK-NEXT: mov z4.s, w8
-; CHECK-NEXT: mov w8, #1593835519 // =0x5effffff
-; CHECK-NEXT: frintx z7.s, p0/m, z7.s
-; CHECK-NEXT: frintx z24.s, p0/m, z24.s
-; CHECK-NEXT: movprfx z30, z2
-; CHECK-NEXT: frintx z30.s, p0/m, z2.s
+; CHECK-NEXT: movprfx z25, z1
+; CHECK-NEXT: frintx z25.s, p0/m, z1.s
; CHECK-NEXT: frintx z6.s, p0/m, z6.s
-; CHECK-NEXT: uunpklo z2.d, z3.s
-; CHECK-NEXT: mov z29.s, w8
-; CHECK-NEXT: mov z26.d, #0x8000000000000000
-; CHECK-NEXT: mov z31.d, #0x8000000000000000
-; CHECK-NEXT: mov z8.d, #0x8000000000000000
-; CHECK-NEXT: mov z9.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmge p5.s, p0/z, z25.s, z4.s
-; CHECK-NEXT: fcmge p1.s, p0/z, z5.s, z4.s
-; CHECK-NEXT: fcmge p3.s, p0/z, z7.s, z4.s
-; CHECK-NEXT: fcmge p4.s, p0/z, z24.s, z4.s
-; CHECK-NEXT: fcvtzs z0.d, p5/m, z25.s
-; CHECK-NEXT: fcvtzs z1.d, p1/m, z5.s
-; CHECK-NEXT: fcvtzs z27.d, p3/m, z7.s
-; CHECK-NEXT: fcmge p2.s, p0/z, z6.s, z4.s
-; CHECK-NEXT: fcvtzs z28.d, p4/m, z24.s
-; CHECK-NEXT: fcmgt p3.s, p0/z, z25.s, z29.s
-; CHECK-NEXT: fcmge p4.s, p0/z, z30.s, z4.s
-; CHECK-NEXT: fcmuo p1.s, p0/z, z25.s, z25.s
-; CHECK-NEXT: movprfx z25, z2
-; CHECK-NEXT: frintx z25.s, p0/m, z2.s
-; CHECK-NEXT: uunpkhi z2.d, z3.s
-; CHECK-NEXT: fcvtzs z26.d, p2/m, z6.s
-; CHECK-NEXT: mov z0.d, p3/m, z9.d
-; CHECK-NEXT: fcmgt p5.s, p0/z, z5.s, z29.s
-; CHECK-NEXT: fcvtzs z31.d, p4/m, z30.s
-; CHECK-NEXT: fcmuo p2.s, p0/z, z5.s, z5.s
-; CHECK-NEXT: movprfx z5, z2
-; CHECK-NEXT: frintx z5.s, p0/m, z2.s
-; CHECK-NEXT: mov z0.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcmge p4.s, p0/z, z25.s, z4.s
-; CHECK-NEXT: fcmgt p6.s, p0/z, z6.s, z29.s
-; CHECK-NEXT: mov z1.d, p5/m, z9.d
-; CHECK-NEXT: fcmgt p8.s, p0/z, z7.s, z29.s
-; CHECK-NEXT: fcmuo p10.s, p0/z, z7.s, z7.s
-; CHECK-NEXT: mov z7.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z8.d, p4/m, z25.s
-; CHECK-NEXT: mov z1.d, p2/m, #0 // =0x0
-; CHECK-NEXT: sel z2.d, p6, z9.d, z26.d
-; CHECK-NEXT: sel z3.d, p8, z9.d, z27.d
-; CHECK-NEXT: fcmge p4.s, p0/z, z5.s, z4.s
-; CHECK-NEXT: fcmgt p9.s, p0/z, z24.s, z29.s
-; CHECK-NEXT: fcmgt p5.s, p0/z, z30.s, z29.s
-; CHECK-NEXT: mov z3.d, p10/m, #0 // =0x0
-; CHECK-NEXT: ldr p10, [sp, #1, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmgt p6.s, p0/z, z25.s, z29.s
-; CHECK-NEXT: fcvtzs z7.d, p4/m, z5.s
-; CHECK-NEXT: fcmgt p4.s, p0/z, z5.s, z29.s
-; CHECK-NEXT: sel z4.d, p9, z9.d, z28.d
-; CHECK-NEXT: fcmuo p7.s, p0/z, z6.s, z6.s
-; CHECK-NEXT: sel z6.d, p6, z9.d, z8.d
-; CHECK-NEXT: ldr z8, [sp, #2, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p8.s, p0/z, z30.s, z30.s
-; CHECK-NEXT: fcmuo p9.s, p0/z, z25.s, z25.s
-; CHECK-NEXT: mov z7.d, p4/m, z9.d
-; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z2.d, p7/m, #0 // =0x0
-; CHECK-NEXT: ldr p7, [sp, #4, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p3.s, p0/z, z24.s, z24.s
-; CHECK-NEXT: fcmuo p0.s, p0/z, z5.s, z5.s
-; CHECK-NEXT: sel z5.d, p5, z9.d, z31.d
-; CHECK-NEXT: ldr z9, [sp, #1, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z6.d, p9/m, #0 // =0x0
-; CHECK-NEXT: ldr p9, [sp, #2, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z5.d, p8/m, #0 // =0x0
-; CHECK-NEXT: ldr p8, [sp, #3, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z4.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z7.d, p0/m, #0 // =0x0
-; CHECK-NEXT: addvl sp, sp, #3
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: movprfx z26, z2
+; CHECK-NEXT: frintx z26.s, p0/m, z2.s
+; CHECK-NEXT: frintx z7.s, p0/m, z7.s
+; CHECK-NEXT: movprfx z27, z3
+; CHECK-NEXT: frintx z27.s, p0/m, z3.s
+; CHECK-NEXT: movprfx z0, z4
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z4.s
+; CHECK-NEXT: movprfx z1, z24
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z24.s
+; CHECK-NEXT: movprfx z2, z5
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z5.s
+; CHECK-NEXT: movprfx z3, z25
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z25.s
+; CHECK-NEXT: movprfx z4, z6
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z6.s
+; CHECK-NEXT: movprfx z5, z26
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z26.s
+; CHECK-NEXT: movprfx z6, z7
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z7.s
+; CHECK-NEXT: movprfx z7, z27
+; CHECK-NEXT: fcvtzs z7.d, p0/m, z27.s
; CHECK-NEXT: ret
%a = call <vscale x 16 x i64> @llvm.llrint.nxv16i64.nxv16f32(<vscale x 16 x float> %x)
ret <vscale x 16 x i64> %a
@@ -773,251 +323,71 @@ declare <vscale x 16 x i64> @llvm.llrint.nxv16i64.nxv16f32(<vscale x 16 x float>
define <vscale x 32 x i64> @llrint_v32i64_v32f32(<vscale x 32 x float> %x) {
; CHECK-LABEL: llrint_v32i64_v32f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-18
-; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p11, [sp, #8, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p10, [sp, #9, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p9, [sp, #10, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p8, [sp, #11, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p7, [sp, #12, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p6, [sp, #13, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #14, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #15, mul vl] // 2-byte Spill
-; CHECK-NEXT: str z23, [sp, #2, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z22, [sp, #3, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z21, [sp, #4, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z20, [sp, #5, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z19, [sp, #6, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z18, [sp, #7, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z17, [sp, #8, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z16, [sp, #9, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0a, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x11, 0x98, 0x01, 0x1e, 0x22 // sp + 16 + 152 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x40, 0x1c // $d9 @ cfa - 16 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x68, 0x1e, 0x22, 0x40, 0x1c // $d10 @ cfa - 24 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4b, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x60, 0x1e, 0x22, 0x40, 0x1c // $d11 @ cfa - 32 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4c, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x58, 0x1e, 0x22, 0x40, 0x1c // $d12 @ cfa - 40 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4d, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x50, 0x1e, 0x22, 0x40, 0x1c // $d13 @ cfa - 48 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4e, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x48, 0x1e, 0x22, 0x40, 0x1c // $d14 @ cfa - 56 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4f, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x40, 0x1e, 0x22, 0x40, 0x1c // $d15 @ cfa - 64 * VG - 16
-; CHECK-NEXT: uunpklo z24.d, z0.s
-; CHECK-NEXT: uunpklo z26.d, z1.s
-; CHECK-NEXT: mov w9, #-553648128 // =0xdf000000
-; CHECK-NEXT: uunpklo z28.d, z2.s
-; CHECK-NEXT: uunpkhi z30.d, z2.s
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: uunpkhi z25.d, z0.s
-; CHECK-NEXT: uunpkhi z13.d, z3.s
-; CHECK-NEXT: uunpklo z14.d, z4.s
-; CHECK-NEXT: uunpkhi z27.d, z1.s
-; CHECK-NEXT: uunpklo z9.d, z3.s
-; CHECK-NEXT: mov z29.s, w9
-; CHECK-NEXT: movprfx z0, z24
-; CHECK-NEXT: frintx z0.s, p0/m, z24.s
-; CHECK-NEXT: movprfx z24, z26
-; CHECK-NEXT: frintx z24.s, p0/m, z26.s
-; CHECK-NEXT: mov w9, #1593835519 // =0x5effffff
-; CHECK-NEXT: movprfx z10, z28
-; CHECK-NEXT: frintx z10.s, p0/m, z28.s
-; CHECK-NEXT: frintx z30.s, p0/m, z30.s
-; CHECK-NEXT: uunpklo z17.d, z5.s
-; CHECK-NEXT: movprfx z1, z25
-; CHECK-NEXT: frintx z1.s, p0/m, z25.s
-; CHECK-NEXT: movprfx z15, z13
-; CHECK-NEXT: frintx z15.s, p0/m, z13.s
-; CHECK-NEXT: movprfx z13, z14
-; CHECK-NEXT: frintx z13.s, p0/m, z14.s
-; CHECK-NEXT: uunpkhi z14.d, z4.s
-; CHECK-NEXT: uunpkhi z18.d, z5.s
-; CHECK-NEXT: uunpkhi z19.d, z6.s
-; CHECK-NEXT: movprfx z25, z27
-; CHECK-NEXT: frintx z25.s, p0/m, z27.s
-; CHECK-NEXT: mov z27.d, #0x8000000000000000
-; CHECK-NEXT: mov z11.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p3.s, p0/z, z24.s, z29.s
-; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: mov z12.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p5.s, p0/z, z10.s, z29.s
-; CHECK-NEXT: frintx z9.s, p0/m, z9.s
-; CHECK-NEXT: uunpklo z20.d, z7.s
-; CHECK-NEXT: movprfx z5, z14
-; CHECK-NEXT: frintx z5.s, p0/m, z14.s
-; CHECK-NEXT: movprfx z14, z17
-; CHECK-NEXT: frintx z14.s, p0/m, z17.s
-; CHECK-NEXT: movprfx z17, z18
-; CHECK-NEXT: frintx z17.s, p0/m, z18.s
-; CHECK-NEXT: fcmge p6.s, p0/z, z30.s, z29.s
-; CHECK-NEXT: uunpkhi z7.d, z7.s
-; CHECK-NEXT: mov z31.s, w9
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z26.d, #0x8000000000000000
-; CHECK-NEXT: frintx z19.s, p0/m, z19.s
+; CHECK-NEXT: uunpkhi z24.d, z7.s
+; CHECK-NEXT: uunpkhi z25.d, z6.s
; CHECK-NEXT: uunpklo z6.d, z6.s
-; CHECK-NEXT: mov z28.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z27.d, p3/m, z24.s
-; CHECK-NEXT: fcvtzs z11.d, p5/m, z10.s
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov z16.d, #0x8000000000000000
-; CHECK-NEXT: movprfx z22, z7
-; CHECK-NEXT: frintx z22.s, p0/m, z7.s
-; CHECK-NEXT: fcvtzs z12.d, p6/m, z30.s
-; CHECK-NEXT: frintx z20.s, p0/m, z20.s
-; CHECK-NEXT: mov z21.d, #0x8000000000000000
-; CHECK-NEXT: mov z23.d, #0x8000000000000000
-; CHECK-NEXT: mov z8.d, #0x8000000000000000
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: uunpklo z7.d, z7.s
+; CHECK-NEXT: uunpkhi z26.d, z5.s
+; CHECK-NEXT: uunpklo z5.d, z5.s
+; CHECK-NEXT: uunpkhi z27.d, z4.s
+; CHECK-NEXT: uunpkhi z28.d, z1.s
+; CHECK-NEXT: uunpklo z4.d, z4.s
+; CHECK-NEXT: uunpkhi z29.d, z3.s
+; CHECK-NEXT: uunpklo z3.d, z3.s
+; CHECK-NEXT: frintx z24.s, p0/m, z24.s
; CHECK-NEXT: frintx z6.s, p0/m, z6.s
-; CHECK-NEXT: mov z3.d, #0x7fffffffffffffff
-; CHECK-NEXT: mov z18.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z29.s
-; CHECK-NEXT: fcmge p2.s, p0/z, z1.s, z29.s
-; CHECK-NEXT: fcmge p4.s, p0/z, z25.s, z29.s
-; CHECK-NEXT: fcmgt p9.s, p0/z, z10.s, z31.s
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.s
-; CHECK-NEXT: mov z0.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z26.d, p2/m, z1.s
-; CHECK-NEXT: fcvtzs z28.d, p4/m, z25.s
-; CHECK-NEXT: mov z11.d, p9/m, z3.d
-; CHECK-NEXT: fcmuo p8.s, p0/z, z10.s, z10.s
-; CHECK-NEXT: mov z10.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p5.s, p0/z, z9.s, z29.s
-; CHECK-NEXT: fcmge p3.s, p0/z, z15.s, z29.s
-; CHECK-NEXT: fcmge p6.s, p0/z, z13.s, z29.s
-; CHECK-NEXT: mov z11.d, p8/m, #0 // =0x0
-; CHECK-NEXT: fcvtzs z10.d, p5/m, z9.s
-; CHECK-NEXT: fcvtzs z4.d, p3/m, z15.s
-; CHECK-NEXT: fcvtzs z16.d, p6/m, z13.s
-; CHECK-NEXT: fcmge p1.s, p0/z, z17.s, z29.s
-; CHECK-NEXT: fcmge p2.s, p0/z, z19.s, z29.s
-; CHECK-NEXT: fcmgt p12.s, p0/z, z30.s, z31.s
-; CHECK-NEXT: fcmgt p5.s, p0/z, z15.s, z31.s
-; CHECK-NEXT: fcvtzs z21.d, p1/m, z17.s
-; CHECK-NEXT: fcmge p3.s, p0/z, z20.s, z29.s
-; CHECK-NEXT: fcvtzs z23.d, p2/m, z19.s
-; CHECK-NEXT: sel z7.d, p12, z3.d, z12.d
-; CHECK-NEXT: fcmgt p11.s, p0/z, z13.s, z31.s
-; CHECK-NEXT: mov z4.d, p5/m, z3.d
-; CHECK-NEXT: fcmge p4.s, p0/z, z22.s, z29.s
-; CHECK-NEXT: fcvtzs z0.d, p3/m, z20.s
-; CHECK-NEXT: fcmge p6.s, p0/z, z5.s, z29.s
-; CHECK-NEXT: fcmge p7.s, p0/z, z14.s, z29.s
-; CHECK-NEXT: sel z12.d, p11, z3.d, z16.d
-; CHECK-NEXT: fcvtzs z8.d, p4/m, z22.s
-; CHECK-NEXT: fcmuo p1.s, p0/z, z13.s, z13.s
-; CHECK-NEXT: fcmge p2.s, p0/z, z6.s, z29.s
-; CHECK-NEXT: mov z29.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z18.d, p7/m, z14.s
-; CHECK-NEXT: fcmuo p10.s, p0/z, z15.s, z15.s
-; CHECK-NEXT: mov z15.d, #0x8000000000000000
-; CHECK-NEXT: mov z12.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p4.s, p0/z, z22.s, z31.s
-; CHECK-NEXT: fcvtzs z29.d, p2/m, z6.s
-; CHECK-NEXT: fcmgt p5.s, p0/z, z20.s, z31.s
-; CHECK-NEXT: str z12, [x8, #8, mul vl]
-; CHECK-NEXT: fcvtzs z15.d, p6/m, z5.s
-; CHECK-NEXT: mov z4.d, p10/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p3.s, p0/z, z19.s, z31.s
-; CHECK-NEXT: mov z8.d, p4/m, z3.d
-; CHECK-NEXT: fcmuo p1.s, p0/z, z22.s, z22.s
-; CHECK-NEXT: str z4, [x8, #7, mul vl]
-; CHECK-NEXT: mov z0.d, p5/m, z3.d
-; CHECK-NEXT: fcmuo p2.s, p0/z, z20.s, z20.s
-; CHECK-NEXT: fcmuo p6.s, p0/z, z19.s, z19.s
-; CHECK-NEXT: fcmgt p4.s, p0/z, z5.s, z31.s
-; CHECK-NEXT: mov z8.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p5.s, p0/z, z5.s, z5.s
-; CHECK-NEXT: sel z5.d, p3, z3.d, z23.d
-; CHECK-NEXT: mov z0.d, p2/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p3.s, p0/z, z6.s, z31.s
-; CHECK-NEXT: str z8, [x8, #15, mul vl]
-; CHECK-NEXT: fcmgt p1.s, p0/z, z17.s, z31.s
-; CHECK-NEXT: str z0, [x8, #14, mul vl]
-; CHECK-NEXT: mov z5.d, p6/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p2.s, p0/z, z14.s, z31.s
-; CHECK-NEXT: sel z0.d, p3, z3.d, z29.d
-; CHECK-NEXT: fcmuo p6.s, p0/z, z6.s, z6.s
-; CHECK-NEXT: str z5, [x8, #13, mul vl]
-; CHECK-NEXT: sel z6.d, p4, z3.d, z15.d
-; CHECK-NEXT: sel z5.d, p1, z3.d, z21.d
-; CHECK-NEXT: fcmuo p4.s, p0/z, z17.s, z17.s
-; CHECK-NEXT: sel z29.d, p2, z3.d, z18.d
-; CHECK-NEXT: mov z6.d, p5/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p3.s, p0/z, z14.s, z14.s
-; CHECK-NEXT: mov z0.d, p6/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p1.s, p0/z, z1.s, z31.s
-; CHECK-NEXT: str z6, [x8, #9, mul vl]
-; CHECK-NEXT: mov z5.d, p4/m, #0 // =0x0
-; CHECK-NEXT: str z0, [x8, #12, mul vl]
-; CHECK-NEXT: mov z29.d, p3/m, #0 // =0x0
-; CHECK-NEXT: str z5, [x8, #11, mul vl]
-; CHECK-NEXT: sel z5.d, p1, z3.d, z26.d
-; CHECK-NEXT: fcmgt p2.s, p0/z, z24.s, z31.s
-; CHECK-NEXT: str z29, [x8, #10, mul vl]
-; CHECK-NEXT: ldr z4, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: str z11, [x8, #4, mul vl]
-; CHECK-NEXT: fcmgt p4.s, p0/z, z25.s, z31.s
-; CHECK-NEXT: fcmuo p3.s, p0/z, z30.s, z30.s
-; CHECK-NEXT: sel z26.d, p2, z3.d, z27.d
-; CHECK-NEXT: fcmgt p6.s, p0/z, z9.s, z31.s
-; CHECK-NEXT: fcmgt p1.s, p0/z, z4.s, z31.s
-; CHECK-NEXT: fcmuo p5.s, p0/z, z9.s, z9.s
-; CHECK-NEXT: sel z6.d, p4, z3.d, z28.d
-; CHECK-NEXT: mov z7.d, p3/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p2.s, p0/z, z25.s, z25.s
-; CHECK-NEXT: sel z0.d, p6, z3.d, z10.d
-; CHECK-NEXT: fcmuo p3.s, p0/z, z24.s, z24.s
-; CHECK-NEXT: fcmuo p4.s, p0/z, z1.s, z1.s
-; CHECK-NEXT: sel z1.d, p1, z3.d, z2.d
-; CHECK-NEXT: str z7, [x8, #5, mul vl]
-; CHECK-NEXT: fcmuo p0.s, p0/z, z4.s, z4.s
-; CHECK-NEXT: mov z0.d, p5/m, #0 // =0x0
-; CHECK-NEXT: mov z6.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z26.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z5.d, p4/m, #0 // =0x0
-; CHECK-NEXT: str z0, [x8, #6, mul vl]
-; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
-; CHECK-NEXT: str z6, [x8, #3, mul vl]
-; CHECK-NEXT: str z26, [x8, #2, mul vl]
-; CHECK-NEXT: str z5, [x8, #1, mul vl]
-; CHECK-NEXT: str z1, [x8]
-; CHECK-NEXT: addvl sp, sp, #1
-; CHECK-NEXT: ldr z23, [sp, #2, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z22, [sp, #3, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z21, [sp, #4, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z20, [sp, #5, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z19, [sp, #6, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z18, [sp, #7, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z17, [sp, #8, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z16, [sp, #9, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z15, [sp, #10, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z14, [sp, #11, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p7, [sp, #12, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p6, [sp, #13, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p5, [sp, #14, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p4, [sp, #15, mul vl] // 2-byte Reload
-; CHECK-NEXT: addvl sp, sp, #18
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: uunpklo z1.d, z1.s
+; CHECK-NEXT: frintx z7.s, p0/m, z7.s
+; CHECK-NEXT: frintx z25.s, p0/m, z25.s
+; CHECK-NEXT: frintx z26.s, p0/m, z26.s
+; CHECK-NEXT: frintx z5.s, p0/m, z5.s
+; CHECK-NEXT: frintx z27.s, p0/m, z27.s
+; CHECK-NEXT: frintx z28.s, p0/m, z28.s
+; CHECK-NEXT: frintx z4.s, p0/m, z4.s
+; CHECK-NEXT: frintx z29.s, p0/m, z29.s
+; CHECK-NEXT: frintx z3.s, p0/m, z3.s
+; CHECK-NEXT: fcvtzs z24.d, p0/m, z24.s
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.s
+; CHECK-NEXT: frintx z1.s, p0/m, z1.s
+; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.s
+; CHECK-NEXT: fcvtzs z25.d, p0/m, z25.s
+; CHECK-NEXT: fcvtzs z26.d, p0/m, z26.s
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.s
+; CHECK-NEXT: fcvtzs z27.d, p0/m, z27.s
+; CHECK-NEXT: fcvtzs z28.d, p0/m, z28.s
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.s
+; CHECK-NEXT: fcvtzs z29.d, p0/m, z29.s
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.s
+; CHECK-NEXT: str z24, [x8, #15, mul vl]
+; CHECK-NEXT: uunpkhi z24.d, z2.s
+; CHECK-NEXT: uunpklo z2.d, z2.s
+; CHECK-NEXT: str z6, [x8, #12, mul vl]
+; CHECK-NEXT: uunpkhi z6.d, z0.s
+; CHECK-NEXT: uunpklo z0.d, z0.s
+; CHECK-NEXT: str z7, [x8, #14, mul vl]
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.s
+; CHECK-NEXT: str z25, [x8, #13, mul vl]
+; CHECK-NEXT: str z26, [x8, #11, mul vl]
+; CHECK-NEXT: frintx z24.s, p0/m, z24.s
+; CHECK-NEXT: frintx z2.s, p0/m, z2.s
+; CHECK-NEXT: str z5, [x8, #10, mul vl]
+; CHECK-NEXT: frintx z6.s, p0/m, z6.s
+; CHECK-NEXT: frintx z0.s, p0/m, z0.s
+; CHECK-NEXT: str z27, [x8, #9, mul vl]
+; CHECK-NEXT: str z4, [x8, #8, mul vl]
+; CHECK-NEXT: str z29, [x8, #7, mul vl]
+; CHECK-NEXT: fcvtzs z24.d, p0/m, z24.s
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.s
+; CHECK-NEXT: str z3, [x8, #6, mul vl]
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.s
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-NEXT: str z28, [x8, #3, mul vl]
+; CHECK-NEXT: str z1, [x8, #2, mul vl]
+; CHECK-NEXT: str z24, [x8, #5, mul vl]
+; CHECK-NEXT: str z2, [x8, #4, mul vl]
+; CHECK-NEXT: str z6, [x8, #1, mul vl]
+; CHECK-NEXT: str z0, [x8]
; CHECK-NEXT: ret
%a = call <vscale x 32 x i64> @llvm.llrint.nxv32i64.nxv32f32(<vscale x 32 x float> %x)
ret <vscale x 32 x i64> %a
@@ -1028,19 +398,8 @@ define <vscale x 1 x i64> @llrint_v1i64_v1f64(<vscale x 1 x double> %x) {
; CHECK-LABEL: llrint_v1i64_v1f64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z1.d, x8
-; CHECK-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff
; CHECK-NEXT: frintx z0.d, p0/m, z0.d
-; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z1.d
-; CHECK-NEXT: mov z1.d, x8
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.d
-; CHECK-NEXT: fcmgt p1.d, p0/z, z0.d, z1.d
-; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
; CHECK-NEXT: ret
%a = call <vscale x 1 x i64> @llvm.llrint.nxv1i64.nxv1f64(<vscale x 1 x double> %x)
ret <vscale x 1 x i64> %a
@@ -1051,19 +410,8 @@ define <vscale x 2 x i64> @llrint_v2i64_v2f64(<vscale x 2 x double> %x) {
; CHECK-LABEL: llrint_v2i64_v2f64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z1.d, x8
-; CHECK-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff
; CHECK-NEXT: frintx z0.d, p0/m, z0.d
-; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z1.d
-; CHECK-NEXT: mov z1.d, x8
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.d
-; CHECK-NEXT: fcmgt p1.d, p0/z, z0.d, z1.d
-; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
; CHECK-NEXT: ret
%a = call <vscale x 2 x i64> @llvm.llrint.nxv2i64.nxv2f64(<vscale x 2 x double> %x)
ret <vscale x 2 x i64> %a
@@ -1074,27 +422,10 @@ define <vscale x 4 x i64> @llrint_v4i64_v4f64(<vscale x 4 x double> %x) {
; CHECK-LABEL: llrint_v4i64_v4f64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000
-; CHECK-NEXT: mov z3.d, #0x8000000000000000
-; CHECK-NEXT: mov z2.d, x8
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff
; CHECK-NEXT: frintx z0.d, p0/m, z0.d
; CHECK-NEXT: frintx z1.d, p0/m, z1.d
-; CHECK-NEXT: mov z5.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z2.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z1.d, z2.d
-; CHECK-NEXT: mov z2.d, x8
-; CHECK-NEXT: fcmuo p3.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: fcvtzs z4.d, p1/m, z0.d
-; CHECK-NEXT: fcmgt p1.d, p0/z, z0.d, z2.d
-; CHECK-NEXT: fcvtzs z3.d, p2/m, z1.d
-; CHECK-NEXT: fcmgt p2.d, p0/z, z1.d, z2.d
-; CHECK-NEXT: fcmuo p0.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: sel z0.d, p1, z5.d, z4.d
-; CHECK-NEXT: sel z1.d, p2, z5.d, z3.d
-; CHECK-NEXT: mov z0.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
; CHECK-NEXT: ret
%a = call <vscale x 4 x i64> @llvm.llrint.nxv4i64.nxv4f64(<vscale x 4 x double> %x)
ret <vscale x 4 x i64> %a
@@ -1104,56 +435,15 @@ declare <vscale x 4 x i64> @llvm.llrint.nxv4i64.nxv4f64(<vscale x 4 x double>)
define <vscale x 8 x i64> @llrint_v8i64_v8f64(<vscale x 8 x double> %x) {
; CHECK-LABEL: llrint_v8i64_v8f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov z5.d, x8
-; CHECK-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff
-; CHECK-NEXT: mov z6.d, #0x8000000000000000
; CHECK-NEXT: frintx z0.d, p0/m, z0.d
; CHECK-NEXT: frintx z1.d, p0/m, z1.d
; CHECK-NEXT: frintx z2.d, p0/m, z2.d
-; CHECK-NEXT: mov z24.d, x8
; CHECK-NEXT: frintx z3.d, p0/m, z3.d
-; CHECK-NEXT: mov z7.d, #0x8000000000000000
-; CHECK-NEXT: mov z25.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z5.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z1.d, z5.d
-; CHECK-NEXT: fcmge p3.d, p0/z, z2.d, z5.d
-; CHECK-NEXT: fcmgt p4.d, p0/z, z0.d, z24.d
-; CHECK-NEXT: fcvtzs z4.d, p1/m, z0.d
-; CHECK-NEXT: fcmge p1.d, p0/z, z3.d, z5.d
-; CHECK-NEXT: mov z5.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z6.d, p2/m, z1.d
-; CHECK-NEXT: fcvtzs z7.d, p3/m, z2.d
-; CHECK-NEXT: fcmuo p2.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: fcmgt p3.d, p0/z, z1.d, z24.d
-; CHECK-NEXT: sel z0.d, p4, z25.d, z4.d
-; CHECK-NEXT: fcmgt p4.d, p0/z, z2.d, z24.d
-; CHECK-NEXT: fcvtzs z5.d, p1/m, z3.d
-; CHECK-NEXT: fcmgt p1.d, p0/z, z3.d, z24.d
-; CHECK-NEXT: fcmuo p5.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: mov z0.d, p2/m, #0 // =0x0
-; CHECK-NEXT: sel z1.d, p3, z25.d, z6.d
-; CHECK-NEXT: fcmuo p6.d, p0/z, z2.d, z2.d
-; CHECK-NEXT: sel z2.d, p4, z25.d, z7.d
-; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p0.d, p0/z, z3.d, z3.d
-; CHECK-NEXT: sel z3.d, p1, z25.d, z5.d
-; CHECK-NEXT: mov z1.d, p5/m, #0 // =0x0
-; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z2.d, p6/m, #0 // =0x0
-; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z3.d, p0/m, #0 // =0x0
-; CHECK-NEXT: addvl sp, sp, #1
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
; CHECK-NEXT: ret
%a = call <vscale x 8 x i64> @llvm.llrint.nxv8i64.nxv8f64(<vscale x 8 x double> %x)
ret <vscale x 8 x i64> %a
@@ -1163,103 +453,23 @@ declare <vscale x 8 x i64> @llvm.llrint.nxv8i64.nxv8f64(<vscale x 8 x double>)
define <vscale x 16 x i64> @llrint_v16f64(<vscale x 16 x double> %x) {
; CHECK-LABEL: llrint_v16f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-3
-; CHECK-NEXT: str p10, [sp, #1, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p9, [sp, #2, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p8, [sp, #3, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p7, [sp, #4, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: str z9, [sp, #1, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z8, [sp, #2, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x48, 0x1e, 0x22 // sp + 16 + 24 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x40, 0x1c // $d9 @ cfa - 16 * VG - 16
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000
-; CHECK-NEXT: mov z25.d, #0x8000000000000000
-; CHECK-NEXT: mov z28.d, #0x8000000000000000
-; CHECK-NEXT: mov z26.d, #0x8000000000000000
-; CHECK-NEXT: mov z27.d, #0x8000000000000000
-; CHECK-NEXT: movprfx z24, z0
-; CHECK-NEXT: frintx z24.d, p0/m, z0.d
-; CHECK-NEXT: frintx z3.d, p0/m, z3.d
-; CHECK-NEXT: mov z0.d, x8
+; CHECK-NEXT: frintx z0.d, p0/m, z0.d
; CHECK-NEXT: frintx z1.d, p0/m, z1.d
-; CHECK-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff
; CHECK-NEXT: frintx z2.d, p0/m, z2.d
+; CHECK-NEXT: frintx z3.d, p0/m, z3.d
; CHECK-NEXT: frintx z4.d, p0/m, z4.d
-; CHECK-NEXT: frintx z6.d, p0/m, z6.d
-; CHECK-NEXT: mov z30.d, x8
-; CHECK-NEXT: mov z29.d, #0x8000000000000000
; CHECK-NEXT: frintx z5.d, p0/m, z5.d
+; CHECK-NEXT: frintx z6.d, p0/m, z6.d
; CHECK-NEXT: frintx z7.d, p0/m, z7.d
-; CHECK-NEXT: mov z31.d, #0x8000000000000000
-; CHECK-NEXT: mov z8.d, #0x7fffffffffffffff
-; CHECK-NEXT: mov z9.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p1.d, p0/z, z24.d, z0.d
-; CHECK-NEXT: fcmge p4.d, p0/z, z3.d, z0.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z1.d, z0.d
-; CHECK-NEXT: fcmge p3.d, p0/z, z2.d, z0.d
-; CHECK-NEXT: fcvtzs z25.d, p1/m, z24.d
-; CHECK-NEXT: fcvtzs z28.d, p4/m, z3.d
-; CHECK-NEXT: fcvtzs z26.d, p2/m, z1.d
-; CHECK-NEXT: fcmge p5.d, p0/z, z4.d, z0.d
-; CHECK-NEXT: fcvtzs z27.d, p3/m, z2.d
-; CHECK-NEXT: fcmgt p4.d, p0/z, z24.d, z30.d
-; CHECK-NEXT: fcmuo p1.d, p0/z, z24.d, z24.d
-; CHECK-NEXT: mov z24.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p7.d, p0/z, z6.d, z0.d
-; CHECK-NEXT: fcvtzs z29.d, p5/m, z4.d
-; CHECK-NEXT: fcmge p3.d, p0/z, z5.d, z0.d
-; CHECK-NEXT: fcmgt p5.d, p0/z, z1.d, z30.d
-; CHECK-NEXT: fcvtzs z24.d, p7/m, z6.d
-; CHECK-NEXT: fcmgt p6.d, p0/z, z2.d, z30.d
-; CHECK-NEXT: fcmge p7.d, p0/z, z7.d, z0.d
-; CHECK-NEXT: fcvtzs z31.d, p3/m, z5.d
-; CHECK-NEXT: sel z0.d, p4, z8.d, z25.d
-; CHECK-NEXT: fcmgt p8.d, p0/z, z3.d, z30.d
-; CHECK-NEXT: fcmgt p9.d, p0/z, z4.d, z30.d
-; CHECK-NEXT: mov z0.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcvtzs z9.d, p7/m, z7.d
-; CHECK-NEXT: fcmuo p2.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: sel z1.d, p5, z8.d, z26.d
-; CHECK-NEXT: fcmuo p3.d, p0/z, z2.d, z2.d
-; CHECK-NEXT: sel z2.d, p6, z8.d, z27.d
-; CHECK-NEXT: fcmgt p5.d, p0/z, z5.d, z30.d
-; CHECK-NEXT: fcmgt p6.d, p0/z, z6.d, z30.d
-; CHECK-NEXT: mov z1.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z2.d, p3/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p7.d, p0/z, z7.d, z30.d
-; CHECK-NEXT: fcmuo p10.d, p0/z, z3.d, z3.d
-; CHECK-NEXT: sel z3.d, p8, z8.d, z28.d
-; CHECK-NEXT: fcmuo p4.d, p0/z, z4.d, z4.d
-; CHECK-NEXT: sel z4.d, p9, z8.d, z29.d
-; CHECK-NEXT: fcmuo p8.d, p0/z, z5.d, z5.d
-; CHECK-NEXT: sel z5.d, p5, z8.d, z31.d
-; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p9.d, p0/z, z6.d, z6.d
-; CHECK-NEXT: sel z6.d, p6, z8.d, z24.d
-; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z3.d, p10/m, #0 // =0x0
-; CHECK-NEXT: ldr p10, [sp, #1, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z4.d, p4/m, #0 // =0x0
-; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z5.d, p8/m, #0 // =0x0
-; CHECK-NEXT: ldr p8, [sp, #3, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z6.d, p9/m, #0 // =0x0
-; CHECK-NEXT: ldr p9, [sp, #2, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p0.d, p0/z, z7.d, z7.d
-; CHECK-NEXT: sel z7.d, p7, z8.d, z9.d
-; CHECK-NEXT: ldr z9, [sp, #1, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z8, [sp, #2, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr p7, [sp, #4, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z7.d, p0/m, #0 // =0x0
-; CHECK-NEXT: addvl sp, sp, #3
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.d
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.d
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.d
+; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.d
; CHECK-NEXT: ret
%a = call <vscale x 16 x i64> @llvm.llrint.nxv16i64.nxv16f64(<vscale x 16 x double> %x)
ret <vscale x 16 x i64> %a
@@ -1269,242 +479,71 @@ declare <vscale x 16 x i64> @llvm.llrint.nxv16i64.nxv16f64(<vscale x 16 x double
define <vscale x 32 x i64> @llrint_v32f64(<vscale x 32 x double> %x) {
; CHECK-LABEL: llrint_v32f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-18
-; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p11, [sp, #8, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p10, [sp, #9, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p9, [sp, #10, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p8, [sp, #11, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p7, [sp, #12, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p6, [sp, #13, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #14, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #15, mul vl] // 2-byte Spill
-; CHECK-NEXT: str z23, [sp, #2, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z22, [sp, #3, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z21, [sp, #4, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z20, [sp, #5, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z19, [sp, #6, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z18, [sp, #7, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z17, [sp, #8, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z16, [sp, #9, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0a, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x11, 0x90, 0x01, 0x1e, 0x22 // sp + 16 + 144 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x40, 0x1c // $d9 @ cfa - 16 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x68, 0x1e, 0x22, 0x40, 0x1c // $d10 @ cfa - 24 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4b, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x60, 0x1e, 0x22, 0x40, 0x1c // $d11 @ cfa - 32 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4c, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x58, 0x1e, 0x22, 0x40, 0x1c // $d12 @ cfa - 40 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4d, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x50, 0x1e, 0x22, 0x40, 0x1c // $d13 @ cfa - 48 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4e, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x48, 0x1e, 0x22, 0x40, 0x1c // $d14 @ cfa - 56 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4f, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x40, 0x1e, 0x22, 0x40, 0x1c // $d15 @ cfa - 64 * VG - 16
-; CHECK-NEXT: ldr z0, [x0]
-; CHECK-NEXT: ldr z7, [x0, #3, mul vl]
+; CHECK-NEXT: ldr z0, [x0, #15, mul vl]
+; CHECK-NEXT: ldr z1, [x0, #14, mul vl]
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: ldr z27, [x0, #4, mul vl]
-; CHECK-NEXT: ldr z4, [x0, #2, mul vl]
-; CHECK-NEXT: mov x9, #-4332462841530417152 // =0xc3e0000000000000
-; CHECK-NEXT: mov z25.d, x9
-; CHECK-NEXT: ldr z2, [x0, #1, mul vl]
-; CHECK-NEXT: ldr z29, [x0, #6, mul vl]
+; CHECK-NEXT: ldr z2, [x0, #13, mul vl]
+; CHECK-NEXT: ldr z3, [x0, #12, mul vl]
+; CHECK-NEXT: ldr z4, [x0, #11, mul vl]
+; CHECK-NEXT: ldr z5, [x0, #10, mul vl]
+; CHECK-NEXT: ldr z6, [x0, #9, mul vl]
+; CHECK-NEXT: ldr z7, [x0, #8, mul vl]
; CHECK-NEXT: frintx z0.d, p0/m, z0.d
-; CHECK-NEXT: frintx z7.d, p0/m, z7.d
-; CHECK-NEXT: ldr z31, [x0, #7, mul vl]
-; CHECK-NEXT: movprfx z14, z27
-; CHECK-NEXT: frintx z14.d, p0/m, z27.d
+; CHECK-NEXT: frintx z1.d, p0/m, z1.d
+; CHECK-NEXT: ldr z24, [x0, #7, mul vl]
+; CHECK-NEXT: ldr z25, [x0, #6, mul vl]
+; CHECK-NEXT: frintx z2.d, p0/m, z2.d
+; CHECK-NEXT: frintx z3.d, p0/m, z3.d
+; CHECK-NEXT: ldr z26, [x0, #5, mul vl]
+; CHECK-NEXT: ldr z27, [x0, #4, mul vl]
; CHECK-NEXT: frintx z4.d, p0/m, z4.d
-; CHECK-NEXT: ldr z27, [x0, #5, mul vl]
-; CHECK-NEXT: ldr z15, [x0, #8, mul vl]
-; CHECK-NEXT: mov x9, #4890909195324358655 // =0x43dfffffffffffff
-; CHECK-NEXT: movprfx z3, z2
-; CHECK-NEXT: frintx z3.d, p0/m, z2.d
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z24.d, #0x8000000000000000
-; CHECK-NEXT: mov z30.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z25.d
-; CHECK-NEXT: movprfx z28, z27
-; CHECK-NEXT: frintx z28.d, p0/m, z27.d
+; CHECK-NEXT: ldr z28, [x0, #3, mul vl]
+; CHECK-NEXT: ldr z29, [x0, #2, mul vl]
+; CHECK-NEXT: frintx z5.d, p0/m, z5.d
+; CHECK-NEXT: ldr z30, [x0, #1, mul vl]
+; CHECK-NEXT: ldr z31, [x0]
+; CHECK-NEXT: frintx z6.d, p0/m, z6.d
+; CHECK-NEXT: frintx z7.d, p0/m, z7.d
+; CHECK-NEXT: frintx z24.d, p0/m, z24.d
+; CHECK-NEXT: frintx z25.d, p0/m, z25.d
+; CHECK-NEXT: frintx z26.d, p0/m, z26.d
+; CHECK-NEXT: frintx z27.d, p0/m, z27.d
+; CHECK-NEXT: frintx z28.d, p0/m, z28.d
; CHECK-NEXT: frintx z29.d, p0/m, z29.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z7.d, z25.d
-; CHECK-NEXT: mov z1.d, x9
-; CHECK-NEXT: mov z6.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p3.d, p0/z, z14.d, z25.d
-; CHECK-NEXT: ldr z11, [x0, #13, mul vl]
-; CHECK-NEXT: ldr z18, [x0, #11, mul vl]
-; CHECK-NEXT: fcmge p5.d, p0/z, z4.d, z25.d
-; CHECK-NEXT: ldr z19, [x0, #9, mul vl]
-; CHECK-NEXT: movprfx z20, z31
-; CHECK-NEXT: frintx z20.d, p0/m, z31.d
-; CHECK-NEXT: frintx z15.d, p0/m, z15.d
-; CHECK-NEXT: ldr z9, [x0, #15, mul vl]
-; CHECK-NEXT: ldr z10, [x0, #14, mul vl]
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.d
-; CHECK-NEXT: fcvtzs z24.d, p2/m, z7.d
-; CHECK-NEXT: mov z12.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z30.d, p3/m, z14.d
-; CHECK-NEXT: mov z31.d, #0x8000000000000000
-; CHECK-NEXT: frintx z18.d, p0/m, z18.d
-; CHECK-NEXT: fcmge p1.d, p0/z, z28.d, z25.d
-; CHECK-NEXT: mov z5.d, #0x8000000000000000
-; CHECK-NEXT: ldr z8, [x0, #12, mul vl]
-; CHECK-NEXT: fcmgt p10.d, p0/z, z14.d, z1.d
-; CHECK-NEXT: ldr z13, [x0, #10, mul vl]
-; CHECK-NEXT: fcvtzs z6.d, p5/m, z4.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z29.d, z25.d
-; CHECK-NEXT: mov z16.d, #0x8000000000000000
-; CHECK-NEXT: mov z17.d, #0x8000000000000000
-; CHECK-NEXT: frintx z10.d, p0/m, z10.d
-; CHECK-NEXT: frintx z9.d, p0/m, z9.d
-; CHECK-NEXT: mov z21.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z12.d, p1/m, z28.d
-; CHECK-NEXT: frintx z13.d, p0/m, z13.d
-; CHECK-NEXT: mov z22.d, #0x8000000000000000
-; CHECK-NEXT: frintx z8.d, p0/m, z8.d
-; CHECK-NEXT: mov z26.d, #0x8000000000000000
-; CHECK-NEXT: mov z27.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcvtzs z31.d, p2/m, z29.d
-; CHECK-NEXT: mov z23.d, #0x8000000000000000
-; CHECK-NEXT: fcmuo p8.d, p0/z, z14.d, z14.d
-; CHECK-NEXT: movprfx z14, z19
-; CHECK-NEXT: frintx z14.d, p0/m, z19.d
-; CHECK-NEXT: movprfx z19, z11
-; CHECK-NEXT: frintx z19.d, p0/m, z11.d
-; CHECK-NEXT: mov z11.d, #0x8000000000000000
-; CHECK-NEXT: mov z30.d, p10/m, z27.d
-; CHECK-NEXT: fcmge p4.d, p0/z, z3.d, z25.d
-; CHECK-NEXT: fcmge p5.d, p0/z, z20.d, z25.d
-; CHECK-NEXT: mov z30.d, p8/m, #0 // =0x0
-; CHECK-NEXT: fcmge p6.d, p0/z, z15.d, z25.d
-; CHECK-NEXT: fcvtzs z5.d, p4/m, z3.d
-; CHECK-NEXT: fcmge p1.d, p0/z, z18.d, z25.d
-; CHECK-NEXT: str z30, [x8, #4, mul vl]
-; CHECK-NEXT: fcvtzs z16.d, p5/m, z20.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z19.d, z25.d
-; CHECK-NEXT: fcvtzs z17.d, p6/m, z15.d
-; CHECK-NEXT: fcmgt p5.d, p0/z, z20.d, z1.d
-; CHECK-NEXT: fcmge p3.d, p0/z, z10.d, z25.d
-; CHECK-NEXT: fcvtzs z21.d, p1/m, z18.d
-; CHECK-NEXT: fcvtzs z22.d, p2/m, z19.d
-; CHECK-NEXT: fcmgt p11.d, p0/z, z15.d, z1.d
-; CHECK-NEXT: fcmge p4.d, p0/z, z9.d, z25.d
-; CHECK-NEXT: fcmge p6.d, p0/z, z14.d, z25.d
-; CHECK-NEXT: fcvtzs z23.d, p3/m, z10.d
-; CHECK-NEXT: fcmge p7.d, p0/z, z13.d, z25.d
-; CHECK-NEXT: fcmuo p1.d, p0/z, z15.d, z15.d
-; CHECK-NEXT: sel z15.d, p5, z27.d, z16.d
-; CHECK-NEXT: sel z16.d, p11, z27.d, z17.d
-; CHECK-NEXT: fcvtzs z26.d, p4/m, z9.d
-; CHECK-NEXT: fcvtzs z11.d, p6/m, z14.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z8.d, z25.d
-; CHECK-NEXT: mov z25.d, #0x8000000000000000
-; CHECK-NEXT: mov z16.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p4.d, p0/z, z9.d, z1.d
-; CHECK-NEXT: fcmgt p5.d, p0/z, z10.d, z1.d
-; CHECK-NEXT: str z16, [x8, #8, mul vl]
-; CHECK-NEXT: fcvtzs z25.d, p2/m, z8.d
-; CHECK-NEXT: fcmgt p3.d, p0/z, z19.d, z1.d
-; CHECK-NEXT: fcmuo p9.d, p0/z, z20.d, z20.d
-; CHECK-NEXT: mov z20.d, #0x8000000000000000
-; CHECK-NEXT: mov z26.d, p4/m, z27.d
-; CHECK-NEXT: fcmuo p1.d, p0/z, z9.d, z9.d
-; CHECK-NEXT: sel z9.d, p5, z27.d, z23.d
-; CHECK-NEXT: fcmuo p2.d, p0/z, z10.d, z10.d
-; CHECK-NEXT: sel z10.d, p3, z27.d, z22.d
-; CHECK-NEXT: fcvtzs z20.d, p7/m, z13.d
-; CHECK-NEXT: mov z15.d, p9/m, #0 // =0x0
-; CHECK-NEXT: mov z26.d, p1/m, #0 // =0x0
-; CHECK-NEXT: mov z9.d, p2/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p4.d, p0/z, z14.d, z1.d
-; CHECK-NEXT: str z15, [x8, #7, mul vl]
-; CHECK-NEXT: fcmgt p3.d, p0/z, z8.d, z1.d
-; CHECK-NEXT: str z26, [x8, #15, mul vl]
-; CHECK-NEXT: fcmuo p6.d, p0/z, z19.d, z19.d
-; CHECK-NEXT: str z9, [x8, #14, mul vl]
-; CHECK-NEXT: fcmgt p1.d, p0/z, z18.d, z1.d
-; CHECK-NEXT: fcmgt p2.d, p0/z, z13.d, z1.d
-; CHECK-NEXT: sel z26.d, p4, z27.d, z11.d
-; CHECK-NEXT: mov z25.d, p3/m, z27.d
-; CHECK-NEXT: fcmuo p4.d, p0/z, z18.d, z18.d
-; CHECK-NEXT: mov z10.d, p6/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p3.d, p0/z, z13.d, z13.d
-; CHECK-NEXT: sel z9.d, p2, z27.d, z20.d
-; CHECK-NEXT: fcmgt p12.d, p0/z, z28.d, z1.d
-; CHECK-NEXT: str z10, [x8, #13, mul vl]
-; CHECK-NEXT: fcmuo p6.d, p0/z, z8.d, z8.d
-; CHECK-NEXT: sel z8.d, p1, z27.d, z21.d
-; CHECK-NEXT: mov z9.d, p3/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p1.d, p0/z, z3.d, z1.d
-; CHECK-NEXT: fcmuo p5.d, p0/z, z14.d, z14.d
-; CHECK-NEXT: mov z8.d, p4/m, #0 // =0x0
-; CHECK-NEXT: mov z12.d, p12/m, z27.d
-; CHECK-NEXT: str z9, [x8, #10, mul vl]
-; CHECK-NEXT: mov z25.d, p6/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p2.d, p0/z, z4.d, z1.d
-; CHECK-NEXT: str z8, [x8, #11, mul vl]
-; CHECK-NEXT: mov z5.d, p1/m, z27.d
-; CHECK-NEXT: fcmgt p4.d, p0/z, z7.d, z1.d
-; CHECK-NEXT: str z25, [x8, #12, mul vl]
-; CHECK-NEXT: mov z26.d, p5/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p3.d, p0/z, z28.d, z28.d
-; CHECK-NEXT: mov z6.d, p2/m, z27.d
-; CHECK-NEXT: fcmgt p6.d, p0/z, z29.d, z1.d
-; CHECK-NEXT: str z26, [x8, #9, mul vl]
-; CHECK-NEXT: fcmgt p1.d, p0/z, z0.d, z1.d
-; CHECK-NEXT: mov z24.d, p4/m, z27.d
-; CHECK-NEXT: mov z12.d, p3/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p5.d, p0/z, z29.d, z29.d
-; CHECK-NEXT: fcmuo p2.d, p0/z, z7.d, z7.d
-; CHECK-NEXT: sel z25.d, p6, z27.d, z31.d
-; CHECK-NEXT: str z12, [x8, #5, mul vl]
-; CHECK-NEXT: fcmuo p3.d, p0/z, z4.d, z4.d
-; CHECK-NEXT: fcmuo p4.d, p0/z, z3.d, z3.d
-; CHECK-NEXT: mov z25.d, p5/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: sel z0.d, p1, z27.d, z2.d
-; CHECK-NEXT: mov z24.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z6.d, p3/m, #0 // =0x0
+; CHECK-NEXT: frintx z30.d, p0/m, z30.d
+; CHECK-NEXT: frintx z31.d, p0/m, z31.d
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.d
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.d
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.d
+; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.d
+; CHECK-NEXT: fcvtzs z24.d, p0/m, z24.d
+; CHECK-NEXT: fcvtzs z25.d, p0/m, z25.d
+; CHECK-NEXT: fcvtzs z26.d, p0/m, z26.d
+; CHECK-NEXT: fcvtzs z27.d, p0/m, z27.d
+; CHECK-NEXT: fcvtzs z28.d, p0/m, z28.d
+; CHECK-NEXT: fcvtzs z29.d, p0/m, z29.d
+; CHECK-NEXT: fcvtzs z30.d, p0/m, z30.d
+; CHECK-NEXT: fcvtzs z31.d, p0/m, z31.d
+; CHECK-NEXT: str z0, [x8, #15, mul vl]
+; CHECK-NEXT: str z1, [x8, #14, mul vl]
+; CHECK-NEXT: str z2, [x8, #13, mul vl]
+; CHECK-NEXT: str z3, [x8, #12, mul vl]
+; CHECK-NEXT: str z4, [x8, #11, mul vl]
+; CHECK-NEXT: str z5, [x8, #10, mul vl]
+; CHECK-NEXT: str z6, [x8, #9, mul vl]
+; CHECK-NEXT: str z7, [x8, #8, mul vl]
+; CHECK-NEXT: str z24, [x8, #7, mul vl]
; CHECK-NEXT: str z25, [x8, #6, mul vl]
-; CHECK-NEXT: mov z5.d, p4/m, #0 // =0x0
-; CHECK-NEXT: str z24, [x8, #3, mul vl]
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
-; CHECK-NEXT: str z6, [x8, #2, mul vl]
-; CHECK-NEXT: str z5, [x8, #1, mul vl]
-; CHECK-NEXT: str z0, [x8]
-; CHECK-NEXT: ldr z23, [sp, #2, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z22, [sp, #3, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z21, [sp, #4, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z20, [sp, #5, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z19, [sp, #6, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z18, [sp, #7, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z17, [sp, #8, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z16, [sp, #9, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z15, [sp, #10, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z14, [sp, #11, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p7, [sp, #12, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p6, [sp, #13, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p5, [sp, #14, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p4, [sp, #15, mul vl] // 2-byte Reload
-; CHECK-NEXT: addvl sp, sp, #18
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: str z26, [x8, #5, mul vl]
+; CHECK-NEXT: str z27, [x8, #4, mul vl]
+; CHECK-NEXT: str z28, [x8, #3, mul vl]
+; CHECK-NEXT: str z29, [x8, #2, mul vl]
+; CHECK-NEXT: str z30, [x8, #1, mul vl]
+; CHECK-NEXT: str z31, [x8]
; CHECK-NEXT: ret
%a = call <vscale x 32 x i64> @llvm.llrint.nxv32i64.nxv16f64(<vscale x 32 x double> %x)
ret <vscale x 32 x i64> %a
diff --git a/llvm/test/CodeGen/AArch64/sve-lrint.ll b/llvm/test/CodeGen/AArch64/sve-lrint.ll
index c6a6a693cca02..889d4a1c8f73a 100644
--- a/llvm/test/CodeGen/AArch64/sve-lrint.ll
+++ b/llvm/test/CodeGen/AArch64/sve-lrint.ll
@@ -5,18 +5,8 @@ define <vscale x 1 x i64> @lrint_v1f16(<vscale x 1 x half> %x) {
; CHECK-LABEL: lrint_v1f16:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z1.h, #-1025 // =0xfffffffffffffbff
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
; CHECK-NEXT: frintx z0.h, p0/m, z0.h
-; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.h, w8
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
-; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
; CHECK-NEXT: ret
%a = call <vscale x 1 x i64> @llvm.lrint.nxv1i64.nxv1f16(<vscale x 1 x half> %x)
ret <vscale x 1 x i64> %a
@@ -26,18 +16,8 @@ define <vscale x 2 x i64> @lrint_v2f16(<vscale x 2 x half> %x) {
; CHECK-LABEL: lrint_v2f16:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z1.h, #-1025 // =0xfffffffffffffbff
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
; CHECK-NEXT: frintx z0.h, p0/m, z0.h
-; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.h, w8
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z1.h
-; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
-; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
; CHECK-NEXT: ret
%a = call <vscale x 2 x i64> @llvm.lrint.nxv2i64.nxv2f16(<vscale x 2 x half> %x)
ret <vscale x 2 x i64> %a
@@ -48,27 +28,14 @@ define <vscale x 4 x i64> @lrint_v4f16(<vscale x 4 x half> %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z1.d, z0.s
; CHECK-NEXT: uunpkhi z0.d, z0.s
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z2.h, #-1025 // =0xfffffffffffffbff
-; CHECK-NEXT: mov z3.d, #0x8000000000000000
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov z5.d, #0x7fffffffffffffff
; CHECK-NEXT: frintx z1.h, p0/m, z1.h
-; CHECK-NEXT: frintx z0.h, p0/m, z0.h
-; CHECK-NEXT: fcmge p1.h, p0/z, z1.h, z2.h
-; CHECK-NEXT: fcmge p2.h, p0/z, z0.h, z2.h
-; CHECK-NEXT: mov z2.h, w8
-; CHECK-NEXT: fcmuo p3.h, p0/z, z1.h, z1.h
-; CHECK-NEXT: fcvtzs z4.d, p1/m, z1.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z1.h, z2.h
-; CHECK-NEXT: fcvtzs z3.d, p2/m, z0.h
-; CHECK-NEXT: fcmgt p2.h, p0/z, z0.h, z2.h
-; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
-; CHECK-NEXT: sel z0.d, p1, z5.d, z4.d
-; CHECK-NEXT: sel z1.d, p2, z5.d, z3.d
-; CHECK-NEXT: mov z0.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
+; CHECK-NEXT: movprfx z2, z0
+; CHECK-NEXT: frintx z2.h, p0/m, z0.h
+; CHECK-NEXT: movprfx z0, z1
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.h
+; CHECK-NEXT: movprfx z1, z2
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z2.h
; CHECK-NEXT: ret
%a = call <vscale x 4 x i64> @llvm.lrint.nxv4i64.nxv4f16(<vscale x 4 x half> %x)
ret <vscale x 4 x i64> %a
@@ -77,62 +44,25 @@ define <vscale x 4 x i64> @lrint_v4f16(<vscale x 4 x half> %x) {
define <vscale x 8 x i64> @lrint_v8f16(<vscale x 8 x half> %x) {
; CHECK-LABEL: lrint_v8f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: uunpklo z1.s, z0.h
; CHECK-NEXT: uunpkhi z0.s, z0.h
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z4.h, #-1025 // =0xfffffffffffffbff
-; CHECK-NEXT: mov z5.d, #0x8000000000000000
-; CHECK-NEXT: mov z6.d, #0x8000000000000000
-; CHECK-NEXT: mov z7.d, #0x8000000000000000
-; CHECK-NEXT: mov z25.d, #0x7fffffffffffffff
; CHECK-NEXT: uunpklo z2.d, z1.s
; CHECK-NEXT: uunpkhi z1.d, z1.s
; CHECK-NEXT: uunpklo z3.d, z0.s
; CHECK-NEXT: uunpkhi z0.d, z0.s
-; CHECK-NEXT: frintx z2.h, p0/m, z2.h
; CHECK-NEXT: frintx z1.h, p0/m, z1.h
+; CHECK-NEXT: frintx z2.h, p0/m, z2.h
; CHECK-NEXT: frintx z3.h, p0/m, z3.h
-; CHECK-NEXT: movprfx z24, z0
-; CHECK-NEXT: frintx z24.h, p0/m, z0.h
-; CHECK-NEXT: mov z0.h, w8
-; CHECK-NEXT: fcmge p1.h, p0/z, z2.h, z4.h
-; CHECK-NEXT: fcmge p2.h, p0/z, z1.h, z4.h
-; CHECK-NEXT: fcmge p3.h, p0/z, z3.h, z4.h
-; CHECK-NEXT: fcmgt p4.h, p0/z, z1.h, z0.h
-; CHECK-NEXT: fcvtzs z5.d, p1/m, z2.h
-; CHECK-NEXT: fcmge p1.h, p0/z, z24.h, z4.h
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z6.d, p2/m, z1.h
-; CHECK-NEXT: fcmgt p2.h, p0/z, z2.h, z0.h
-; CHECK-NEXT: fcvtzs z7.d, p3/m, z3.h
-; CHECK-NEXT: fcmgt p5.h, p0/z, z3.h, z0.h
-; CHECK-NEXT: fcmgt p6.h, p0/z, z24.h, z0.h
-; CHECK-NEXT: fcvtzs z4.d, p1/m, z24.h
-; CHECK-NEXT: fcmuo p3.h, p0/z, z2.h, z2.h
-; CHECK-NEXT: sel z0.d, p2, z25.d, z5.d
-; CHECK-NEXT: fcmuo p1.h, p0/z, z1.h, z1.h
-; CHECK-NEXT: sel z1.d, p4, z25.d, z6.d
-; CHECK-NEXT: sel z2.d, p5, z25.d, z7.d
-; CHECK-NEXT: fcmuo p2.h, p0/z, z3.h, z3.h
-; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p0.h, p0/z, z24.h, z24.h
-; CHECK-NEXT: sel z3.d, p6, z25.d, z4.d
-; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z0.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z1.d, p1/m, #0 // =0x0
-; CHECK-NEXT: mov z2.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z3.d, p0/m, #0 // =0x0
-; CHECK-NEXT: addvl sp, sp, #1
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: movprfx z4, z0
+; CHECK-NEXT: frintx z4.h, p0/m, z0.h
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.h
+; CHECK-NEXT: movprfx z0, z2
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z2.h
+; CHECK-NEXT: movprfx z2, z3
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z3.h
+; CHECK-NEXT: movprfx z3, z4
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z4.h
; CHECK-NEXT: ret
%a = call <vscale x 8 x i64> @llvm.lrint.nxv8i64.nxv8f16(<vscale x 8 x half> %x)
ret <vscale x 8 x i64> %a
@@ -141,110 +71,46 @@ define <vscale x 8 x i64> @lrint_v8f16(<vscale x 8 x half> %x) {
define <vscale x 16 x i64> @lrint_v16f16(<vscale x 16 x half> %x) {
; CHECK-LABEL: lrint_v16f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: str p10, [sp, #1, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p9, [sp, #2, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p8, [sp, #3, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p7, [sp, #4, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: uunpkhi z3.s, z0.h
; CHECK-NEXT: uunpklo z2.s, z0.h
-; CHECK-NEXT: mov w8, #31743 // =0x7bff
-; CHECK-NEXT: uunpklo z7.s, z1.h
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z0.h, #-1025 // =0xfffffffffffffbff
+; CHECK-NEXT: uunpkhi z0.s, z0.h
+; CHECK-NEXT: uunpklo z3.s, z1.h
; CHECK-NEXT: uunpkhi z1.s, z1.h
-; CHECK-NEXT: mov z5.d, #0x8000000000000000
-; CHECK-NEXT: mov z31.d, #0x8000000000000000
-; CHECK-NEXT: mov z29.h, w8
-; CHECK-NEXT: uunpkhi z25.d, z3.s
+; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: uunpklo z4.d, z2.s
-; CHECK-NEXT: uunpkhi z6.d, z2.s
-; CHECK-NEXT: uunpklo z24.d, z3.s
-; CHECK-NEXT: uunpklo z26.d, z7.s
-; CHECK-NEXT: uunpkhi z7.d, z7.s
-; CHECK-NEXT: uunpklo z30.d, z1.s
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z3.d, #0x8000000000000000
+; CHECK-NEXT: uunpkhi z2.d, z2.s
+; CHECK-NEXT: uunpklo z5.d, z0.s
+; CHECK-NEXT: uunpkhi z0.d, z0.s
+; CHECK-NEXT: uunpklo z6.d, z3.s
+; CHECK-NEXT: uunpkhi z3.d, z3.s
+; CHECK-NEXT: uunpklo z7.d, z1.s
; CHECK-NEXT: uunpkhi z1.d, z1.s
-; CHECK-NEXT: movprfx z27, z4
-; CHECK-NEXT: frintx z27.h, p0/m, z4.h
-; CHECK-NEXT: movprfx z28, z6
-; CHECK-NEXT: frintx z28.h, p0/m, z6.h
-; CHECK-NEXT: frintx z25.h, p0/m, z25.h
-; CHECK-NEXT: frintx z24.h, p0/m, z24.h
-; CHECK-NEXT: frintx z26.h, p0/m, z26.h
+; CHECK-NEXT: frintx z4.h, p0/m, z4.h
+; CHECK-NEXT: frintx z2.h, p0/m, z2.h
+; CHECK-NEXT: frintx z5.h, p0/m, z5.h
+; CHECK-NEXT: movprfx z24, z0
+; CHECK-NEXT: frintx z24.h, p0/m, z0.h
+; CHECK-NEXT: frintx z6.h, p0/m, z6.h
+; CHECK-NEXT: movprfx z25, z3
+; CHECK-NEXT: frintx z25.h, p0/m, z3.h
; CHECK-NEXT: frintx z7.h, p0/m, z7.h
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov z6.d, #0x8000000000000000
-; CHECK-NEXT: frintx z30.h, p0/m, z30.h
-; CHECK-NEXT: fcmge p4.h, p0/z, z25.h, z0.h
-; CHECK-NEXT: fcmge p1.h, p0/z, z27.h, z0.h
-; CHECK-NEXT: fcmge p2.h, p0/z, z28.h, z0.h
-; CHECK-NEXT: fcmge p3.h, p0/z, z24.h, z0.h
-; CHECK-NEXT: fcvtzs z5.d, p4/m, z25.h
-; CHECK-NEXT: fcmge p5.h, p0/z, z26.h, z0.h
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z27.h
-; CHECK-NEXT: fcvtzs z3.d, p2/m, z28.h
-; CHECK-NEXT: fcmge p4.h, p0/z, z7.h, z0.h
-; CHECK-NEXT: fcvtzs z4.d, p3/m, z24.h
-; CHECK-NEXT: fcmgt p3.h, p0/z, z27.h, z29.h
-; CHECK-NEXT: fcvtzs z6.d, p5/m, z26.h
-; CHECK-NEXT: fcmuo p1.h, p0/z, z27.h, z27.h
-; CHECK-NEXT: mov z27.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z31.d, p4/m, z7.h
-; CHECK-NEXT: fcmgt p5.h, p0/z, z28.h, z29.h
-; CHECK-NEXT: fcmuo p2.h, p0/z, z28.h, z28.h
-; CHECK-NEXT: movprfx z28, z1
-; CHECK-NEXT: frintx z28.h, p0/m, z1.h
-; CHECK-NEXT: fcmge p4.h, p0/z, z30.h, z0.h
-; CHECK-NEXT: fcmgt p6.h, p0/z, z24.h, z29.h
-; CHECK-NEXT: fcmuo p7.h, p0/z, z24.h, z24.h
-; CHECK-NEXT: mov z24.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmgt p8.h, p0/z, z25.h, z29.h
-; CHECK-NEXT: fcvtzs z27.d, p4/m, z30.h
-; CHECK-NEXT: fcmuo p10.h, p0/z, z25.h, z25.h
-; CHECK-NEXT: mov z25.d, #0x8000000000000000
-; CHECK-NEXT: sel z1.d, p5, z24.d, z3.d
-; CHECK-NEXT: fcmge p4.h, p0/z, z28.h, z0.h
-; CHECK-NEXT: sel z0.d, p3, z24.d, z2.d
-; CHECK-NEXT: sel z2.d, p6, z24.d, z4.d
-; CHECK-NEXT: sel z3.d, p8, z24.d, z5.d
-; CHECK-NEXT: mov z1.d, p2/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p9.h, p0/z, z26.h, z29.h
-; CHECK-NEXT: mov z2.d, p7/m, #0 // =0x0
-; CHECK-NEXT: ldr p7, [sp, #4, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcvtzs z25.d, p4/m, z28.h
-; CHECK-NEXT: mov z3.d, p10/m, #0 // =0x0
-; CHECK-NEXT: ldr p10, [sp, #1, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z0.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p5.h, p0/z, z7.h, z29.h
-; CHECK-NEXT: fcmgt p6.h, p0/z, z30.h, z29.h
-; CHECK-NEXT: sel z4.d, p9, z24.d, z6.d
-; CHECK-NEXT: fcmgt p4.h, p0/z, z28.h, z29.h
-; CHECK-NEXT: fcmuo p8.h, p0/z, z7.h, z7.h
-; CHECK-NEXT: sel z5.d, p5, z24.d, z31.d
-; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p9.h, p0/z, z30.h, z30.h
-; CHECK-NEXT: sel z6.d, p6, z24.d, z27.d
-; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload
-; CHECK-NEXT: sel z7.d, p4, z24.d, z25.d
-; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p3.h, p0/z, z26.h, z26.h
-; CHECK-NEXT: mov z5.d, p8/m, #0 // =0x0
-; CHECK-NEXT: ldr p8, [sp, #3, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p0.h, p0/z, z28.h, z28.h
-; CHECK-NEXT: mov z6.d, p9/m, #0 // =0x0
-; CHECK-NEXT: ldr p9, [sp, #2, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z4.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z7.d, p0/m, #0 // =0x0
-; CHECK-NEXT: addvl sp, sp, #1
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: movprfx z26, z1
+; CHECK-NEXT: frintx z26.h, p0/m, z1.h
+; CHECK-NEXT: movprfx z0, z4
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z4.h
+; CHECK-NEXT: movprfx z1, z2
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z2.h
+; CHECK-NEXT: movprfx z2, z5
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z5.h
+; CHECK-NEXT: movprfx z3, z24
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z24.h
+; CHECK-NEXT: movprfx z4, z6
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z6.h
+; CHECK-NEXT: movprfx z5, z25
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z25.h
+; CHECK-NEXT: movprfx z6, z7
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z7.h
+; CHECK-NEXT: movprfx z7, z26
+; CHECK-NEXT: fcvtzs z7.d, p0/m, z26.h
; CHECK-NEXT: ret
%a = call <vscale x 16 x i64> @llvm.lrint.nxv16i64.nxv16f16(<vscale x 16 x half> %x)
ret <vscale x 16 x i64> %a
@@ -253,252 +119,79 @@ define <vscale x 16 x i64> @lrint_v16f16(<vscale x 16 x half> %x) {
define <vscale x 32 x i64> @lrint_v32f16(<vscale x 32 x half> %x) {
; CHECK-LABEL: lrint_v32f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-18
-; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p11, [sp, #8, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p10, [sp, #9, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p9, [sp, #10, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p8, [sp, #11, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p7, [sp, #12, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p6, [sp, #13, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #14, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #15, mul vl] // 2-byte Spill
-; CHECK-NEXT: str z23, [sp, #2, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z22, [sp, #3, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z21, [sp, #4, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z20, [sp, #5, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z19, [sp, #6, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z18, [sp, #7, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z17, [sp, #8, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z16, [sp, #9, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0a, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x11, 0x90, 0x01, 0x1e, 0x22 // sp + 16 + 144 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x40, 0x1c // $d9 @ cfa - 16 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x68, 0x1e, 0x22, 0x40, 0x1c // $d10 @ cfa - 24 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4b, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x60, 0x1e, 0x22, 0x40, 0x1c // $d11 @ cfa - 32 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4c, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x58, 0x1e, 0x22, 0x40, 0x1c // $d12 @ cfa - 40 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4d, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x50, 0x1e, 0x22, 0x40, 0x1c // $d13 @ cfa - 48 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4e, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x48, 0x1e, 0x22, 0x40, 0x1c // $d14 @ cfa - 56 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4f, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x40, 0x1e, 0x22, 0x40, 0x1c // $d15 @ cfa - 64 * VG - 16
-; CHECK-NEXT: uunpklo z4.s, z0.h
-; CHECK-NEXT: uunpkhi z0.s, z0.h
-; CHECK-NEXT: mov w9, #31743 // =0x7bff
-; CHECK-NEXT: uunpklo z5.s, z1.h
+; CHECK-NEXT: uunpkhi z4.s, z3.h
+; CHECK-NEXT: uunpklo z3.s, z3.h
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z28.h, #-1025 // =0xfffffffffffffbff
-; CHECK-NEXT: uunpkhi z29.s, z1.h
-; CHECK-NEXT: mov z7.d, #0x8000000000000000
-; CHECK-NEXT: uunpklo z13.s, z2.h
-; CHECK-NEXT: mov z9.d, #0x8000000000000000
-; CHECK-NEXT: uunpkhi z14.s, z2.h
-; CHECK-NEXT: uunpkhi z17.s, z3.h
-; CHECK-NEXT: uunpklo z6.d, z4.s
-; CHECK-NEXT: uunpkhi z4.d, z4.s
-; CHECK-NEXT: uunpklo z27.d, z0.s
-; CHECK-NEXT: uunpklo z31.d, z5.s
-; CHECK-NEXT: uunpkhi z8.d, z5.s
-; CHECK-NEXT: uunpkhi z30.d, z0.s
-; CHECK-NEXT: uunpkhi z11.d, z29.s
-; CHECK-NEXT: uunpklo z10.d, z29.s
-; CHECK-NEXT: uunpklo z15.s, z3.h
-; CHECK-NEXT: uunpklo z16.d, z14.s
-; CHECK-NEXT: uunpkhi z14.d, z14.s
-; CHECK-NEXT: mov z24.d, #0x8000000000000000
-; CHECK-NEXT: movprfx z5, z27
-; CHECK-NEXT: frintx z5.h, p0/m, z27.h
-; CHECK-NEXT: movprfx z1, z6
-; CHECK-NEXT: frintx z1.h, p0/m, z6.h
+; CHECK-NEXT: uunpkhi z7.s, z2.h
+; CHECK-NEXT: uunpklo z2.s, z2.h
+; CHECK-NEXT: uunpkhi z24.s, z0.h
+; CHECK-NEXT: uunpkhi z25.s, z1.h
+; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: uunpklo z1.s, z1.h
+; CHECK-NEXT: uunpkhi z5.d, z4.s
+; CHECK-NEXT: uunpklo z4.d, z4.s
+; CHECK-NEXT: uunpkhi z6.d, z3.s
+; CHECK-NEXT: uunpklo z3.d, z3.s
+; CHECK-NEXT: uunpkhi z26.d, z7.s
+; CHECK-NEXT: uunpklo z7.d, z7.s
+; CHECK-NEXT: uunpkhi z27.d, z2.s
+; CHECK-NEXT: uunpkhi z28.d, z24.s
+; CHECK-NEXT: uunpklo z2.d, z2.s
+; CHECK-NEXT: uunpkhi z29.d, z25.s
+; CHECK-NEXT: uunpklo z25.d, z25.s
+; CHECK-NEXT: frintx z5.h, p0/m, z5.h
; CHECK-NEXT: frintx z4.h, p0/m, z4.h
-; CHECK-NEXT: movprfx z12, z31
-; CHECK-NEXT: frintx z12.h, p0/m, z31.h
-; CHECK-NEXT: movprfx z27, z8
-; CHECK-NEXT: frintx z27.h, p0/m, z8.h
-; CHECK-NEXT: movprfx z6, z30
-; CHECK-NEXT: frintx z6.h, p0/m, z30.h
-; CHECK-NEXT: movprfx z31, z10
-; CHECK-NEXT: frintx z31.h, p0/m, z10.h
-; CHECK-NEXT: mov z8.d, #0x8000000000000000
-; CHECK-NEXT: frintx z11.h, p0/m, z11.h
-; CHECK-NEXT: movprfx z3, z16
-; CHECK-NEXT: frintx z3.h, p0/m, z16.h
-; CHECK-NEXT: mov z30.h, w9
-; CHECK-NEXT: uunpklo z10.d, z13.s
-; CHECK-NEXT: uunpkhi z13.d, z13.s
-; CHECK-NEXT: uunpkhi z20.d, z15.s
-; CHECK-NEXT: uunpklo z16.d, z17.s
-; CHECK-NEXT: mov z25.d, #0x8000000000000000
-; CHECK-NEXT: mov z0.d, #0x8000000000000000
-; CHECK-NEXT: mov z18.d, #0x8000000000000000
-; CHECK-NEXT: uunpklo z15.d, z15.s
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z21.d, #0x8000000000000000
-; CHECK-NEXT: frintx z10.h, p0/m, z10.h
-; CHECK-NEXT: mov z26.d, #0x8000000000000000
-; CHECK-NEXT: mov z29.d, #0x7fffffffffffffff
-; CHECK-NEXT: movprfx z19, z13
-; CHECK-NEXT: frintx z19.h, p0/m, z13.h
-; CHECK-NEXT: movprfx z13, z14
-; CHECK-NEXT: frintx z13.h, p0/m, z14.h
-; CHECK-NEXT: frintx z20.h, p0/m, z20.h
-; CHECK-NEXT: frintx z16.h, p0/m, z16.h
-; CHECK-NEXT: mov z22.d, #0x8000000000000000
-; CHECK-NEXT: mov z23.d, #0x8000000000000000
-; CHECK-NEXT: frintx z15.h, p0/m, z15.h
-; CHECK-NEXT: mov z14.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p4.h, p0/z, z4.h, z28.h
-; CHECK-NEXT: fcmge p2.h, p0/z, z12.h, z28.h
-; CHECK-NEXT: fcmgt p9.h, p0/z, z12.h, z30.h
-; CHECK-NEXT: fcmuo p8.h, p0/z, z12.h, z12.h
-; CHECK-NEXT: fcvtzs z7.d, p4/m, z4.h
-; CHECK-NEXT: fcvtzs z8.d, p2/m, z12.h
-; CHECK-NEXT: mov z12.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p4.h, p0/z, z27.h, z28.h
-; CHECK-NEXT: fcmuo p10.h, p0/z, z11.h, z11.h
-; CHECK-NEXT: fcmge p3.h, p0/z, z5.h, z28.h
-; CHECK-NEXT: mov z8.d, p9/m, z29.d
-; CHECK-NEXT: fcvtzs z9.d, p4/m, z27.h
-; CHECK-NEXT: fcmge p4.h, p0/z, z11.h, z28.h
-; CHECK-NEXT: fcvtzs z24.d, p3/m, z5.h
-; CHECK-NEXT: mov z8.d, p8/m, #0 // =0x0
-; CHECK-NEXT: fcmge p1.h, p0/z, z6.h, z28.h
-; CHECK-NEXT: fcmge p5.h, p0/z, z1.h, z28.h
-; CHECK-NEXT: str z8, [x8, #4, mul vl]
-; CHECK-NEXT: fcvtzs z12.d, p4/m, z11.h
-; CHECK-NEXT: fcmgt p4.h, p0/z, z11.h, z30.h
-; CHECK-NEXT: uunpkhi z11.d, z17.s
-; CHECK-NEXT: mov z17.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z25.d, p1/m, z6.h
-; CHECK-NEXT: fcvtzs z0.d, p5/m, z1.h
-; CHECK-NEXT: fcmge p6.h, p0/z, z10.h, z28.h
-; CHECK-NEXT: frintx z11.h, p0/m, z11.h
-; CHECK-NEXT: fcmge p3.h, p0/z, z31.h, z28.h
-; CHECK-NEXT: fcmge p1.h, p0/z, z13.h, z28.h
-; CHECK-NEXT: fcvtzs z18.d, p6/m, z10.h
-; CHECK-NEXT: fcmgt p11.h, p0/z, z10.h, z30.h
-; CHECK-NEXT: fcvtzs z2.d, p3/m, z31.h
-; CHECK-NEXT: fcmge p5.h, p0/z, z11.h, z28.h
-; CHECK-NEXT: fcvtzs z21.d, p1/m, z13.h
-; CHECK-NEXT: fcmge p2.h, p0/z, z20.h, z28.h
-; CHECK-NEXT: fcmge p3.h, p0/z, z16.h, z28.h
-; CHECK-NEXT: fcmuo p1.h, p0/z, z10.h, z10.h
-; CHECK-NEXT: sel z10.d, p4, z29.d, z12.d
-; CHECK-NEXT: sel z12.d, p11, z29.d, z18.d
-; CHECK-NEXT: fcvtzs z26.d, p5/m, z11.h
-; CHECK-NEXT: fcvtzs z22.d, p2/m, z20.h
-; CHECK-NEXT: fcvtzs z23.d, p3/m, z16.h
-; CHECK-NEXT: mov z10.d, p10/m, #0 // =0x0
-; CHECK-NEXT: mov z12.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p4.h, p0/z, z11.h, z30.h
-; CHECK-NEXT: fcmge p6.h, p0/z, z19.h, z28.h
-; CHECK-NEXT: str z10, [x8, #7, mul vl]
-; CHECK-NEXT: fcmge p7.h, p0/z, z3.h, z28.h
-; CHECK-NEXT: str z12, [x8, #8, mul vl]
-; CHECK-NEXT: fcmge p2.h, p0/z, z15.h, z28.h
-; CHECK-NEXT: mov z28.d, #0x8000000000000000
-; CHECK-NEXT: mov z26.d, p4/m, z29.d
-; CHECK-NEXT: fcmgt p5.h, p0/z, z16.h, z30.h
-; CHECK-NEXT: fcvtzs z14.d, p6/m, z19.h
-; CHECK-NEXT: fcvtzs z17.d, p7/m, z3.h
-; CHECK-NEXT: fcmgt p3.h, p0/z, z20.h, z30.h
-; CHECK-NEXT: fcvtzs z28.d, p2/m, z15.h
-; CHECK-NEXT: fcmuo p1.h, p0/z, z11.h, z11.h
-; CHECK-NEXT: sel z11.d, p5, z29.d, z23.d
-; CHECK-NEXT: fcmuo p2.h, p0/z, z16.h, z16.h
-; CHECK-NEXT: fcmgt p4.h, p0/z, z19.h, z30.h
-; CHECK-NEXT: sel z16.d, p3, z29.d, z22.d
-; CHECK-NEXT: mov z26.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p3.h, p0/z, z15.h, z30.h
-; CHECK-NEXT: fcmgt p1.h, p0/z, z13.h, z30.h
-; CHECK-NEXT: mov z11.d, p2/m, #0 // =0x0
-; CHECK-NEXT: str z26, [x8, #15, mul vl]
-; CHECK-NEXT: sel z26.d, p4, z29.d, z14.d
-; CHECK-NEXT: fcmuo p6.h, p0/z, z20.h, z20.h
-; CHECK-NEXT: fcmgt p2.h, p0/z, z3.h, z30.h
-; CHECK-NEXT: str z11, [x8, #14, mul vl]
-; CHECK-NEXT: mov z28.d, p3/m, z29.d
-; CHECK-NEXT: fcmuo p4.h, p0/z, z13.h, z13.h
-; CHECK-NEXT: fcmuo p3.h, p0/z, z3.h, z3.h
-; CHECK-NEXT: sel z3.d, p1, z29.d, z21.d
-; CHECK-NEXT: mov z16.d, p6/m, #0 // =0x0
-; CHECK-NEXT: sel z11.d, p2, z29.d, z17.d
-; CHECK-NEXT: fcmgt p12.h, p0/z, z27.h, z30.h
-; CHECK-NEXT: mov z3.d, p4/m, #0 // =0x0
-; CHECK-NEXT: str z16, [x8, #13, mul vl]
-; CHECK-NEXT: fcmuo p6.h, p0/z, z15.h, z15.h
-; CHECK-NEXT: mov z11.d, p3/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p1.h, p0/z, z4.h, z30.h
-; CHECK-NEXT: str z3, [x8, #11, mul vl]
-; CHECK-NEXT: fcmuo p5.h, p0/z, z19.h, z19.h
-; CHECK-NEXT: mov z9.d, p12/m, z29.d
-; CHECK-NEXT: str z11, [x8, #10, mul vl]
-; CHECK-NEXT: fcmgt p2.h, p0/z, z5.h, z30.h
-; CHECK-NEXT: mov z28.d, p6/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p4.h, p0/z, z6.h, z30.h
-; CHECK-NEXT: sel z3.d, p1, z29.d, z7.d
-; CHECK-NEXT: mov z26.d, p5/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p3.h, p0/z, z27.h, z27.h
-; CHECK-NEXT: str z28, [x8, #12, mul vl]
-; CHECK-NEXT: fcmgt p6.h, p0/z, z31.h, z30.h
-; CHECK-NEXT: sel z7.d, p2, z29.d, z24.d
-; CHECK-NEXT: str z26, [x8, #9, mul vl]
-; CHECK-NEXT: sel z24.d, p4, z29.d, z25.d
-; CHECK-NEXT: fcmgt p1.h, p0/z, z1.h, z30.h
-; CHECK-NEXT: fcmuo p5.h, p0/z, z31.h, z31.h
-; CHECK-NEXT: mov z9.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z2.d, p6/m, z29.d
-; CHECK-NEXT: fcmuo p2.h, p0/z, z6.h, z6.h
-; CHECK-NEXT: fcmuo p3.h, p0/z, z5.h, z5.h
-; CHECK-NEXT: str z9, [x8, #5, mul vl]
-; CHECK-NEXT: mov z0.d, p1/m, z29.d
-; CHECK-NEXT: mov z2.d, p5/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p4.h, p0/z, z4.h, z4.h
-; CHECK-NEXT: fcmuo p0.h, p0/z, z1.h, z1.h
-; CHECK-NEXT: mov z24.d, p2/m, #0 // =0x0
-; CHECK-NEXT: str z2, [x8, #6, mul vl]
-; CHECK-NEXT: mov z7.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z3.d, p4/m, #0 // =0x0
-; CHECK-NEXT: str z24, [x8, #3, mul vl]
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
-; CHECK-NEXT: str z7, [x8, #2, mul vl]
-; CHECK-NEXT: str z3, [x8, #1, mul vl]
+; CHECK-NEXT: frintx z6.h, p0/m, z6.h
+; CHECK-NEXT: frintx z3.h, p0/m, z3.h
+; CHECK-NEXT: frintx z26.h, p0/m, z26.h
+; CHECK-NEXT: frintx z7.h, p0/m, z7.h
+; CHECK-NEXT: frintx z27.h, p0/m, z27.h
+; CHECK-NEXT: frintx z2.h, p0/m, z2.h
+; CHECK-NEXT: frintx z28.h, p0/m, z28.h
+; CHECK-NEXT: frintx z29.h, p0/m, z29.h
+; CHECK-NEXT: frintx z25.h, p0/m, z25.h
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.h
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.h
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.h
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.h
+; CHECK-NEXT: fcvtzs z26.d, p0/m, z26.h
+; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.h
+; CHECK-NEXT: fcvtzs z27.d, p0/m, z27.h
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.h
+; CHECK-NEXT: fcvtzs z28.d, p0/m, z28.h
+; CHECK-NEXT: fcvtzs z29.d, p0/m, z29.h
+; CHECK-NEXT: fcvtzs z25.d, p0/m, z25.h
+; CHECK-NEXT: str z5, [x8, #15, mul vl]
+; CHECK-NEXT: uunpkhi z5.d, z1.s
+; CHECK-NEXT: uunpklo z1.d, z1.s
+; CHECK-NEXT: str z4, [x8, #14, mul vl]
+; CHECK-NEXT: uunpkhi z4.d, z0.s
+; CHECK-NEXT: uunpklo z0.d, z0.s
+; CHECK-NEXT: str z3, [x8, #12, mul vl]
+; CHECK-NEXT: uunpklo z3.d, z24.s
+; CHECK-NEXT: str z6, [x8, #13, mul vl]
+; CHECK-NEXT: str z26, [x8, #11, mul vl]
+; CHECK-NEXT: frintx z5.h, p0/m, z5.h
+; CHECK-NEXT: frintx z1.h, p0/m, z1.h
+; CHECK-NEXT: str z7, [x8, #10, mul vl]
+; CHECK-NEXT: frintx z4.h, p0/m, z4.h
+; CHECK-NEXT: frintx z0.h, p0/m, z0.h
+; CHECK-NEXT: str z27, [x8, #9, mul vl]
+; CHECK-NEXT: frintx z3.h, p0/m, z3.h
+; CHECK-NEXT: str z2, [x8, #8, mul vl]
+; CHECK-NEXT: str z29, [x8, #7, mul vl]
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.h
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.h
+; CHECK-NEXT: str z25, [x8, #6, mul vl]
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.h
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
+; CHECK-NEXT: str z28, [x8, #3, mul vl]
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.h
+; CHECK-NEXT: str z5, [x8, #5, mul vl]
+; CHECK-NEXT: str z1, [x8, #4, mul vl]
+; CHECK-NEXT: str z3, [x8, #2, mul vl]
+; CHECK-NEXT: str z4, [x8, #1, mul vl]
; CHECK-NEXT: str z0, [x8]
-; CHECK-NEXT: ldr z23, [sp, #2, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z22, [sp, #3, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z21, [sp, #4, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z20, [sp, #5, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z19, [sp, #6, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z18, [sp, #7, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z17, [sp, #8, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z16, [sp, #9, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z15, [sp, #10, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z14, [sp, #11, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p7, [sp, #12, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p6, [sp, #13, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p5, [sp, #14, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p4, [sp, #15, mul vl] // 2-byte Reload
-; CHECK-NEXT: addvl sp, sp, #18
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
%a = call <vscale x 32 x i64> @llvm.lrint.nxv32i64.nxv32f16(<vscale x 32 x half> %x)
ret <vscale x 32 x i64> %a
@@ -508,19 +201,8 @@ define <vscale x 1 x i64> @lrint_v1f32(<vscale x 1 x float> %x) {
; CHECK-LABEL: lrint_v1f32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov w8, #-553648128 // =0xdf000000
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z1.s, w8
-; CHECK-NEXT: mov w8, #1593835519 // =0x5effffff
; CHECK-NEXT: frintx z0.s, p0/m, z0.s
-; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z1.s
-; CHECK-NEXT: mov z1.s, w8
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.s
-; CHECK-NEXT: fcmgt p1.s, p0/z, z0.s, z1.s
-; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
; CHECK-NEXT: ret
%a = call <vscale x 1 x i64> @llvm.lrint.nxv1i64.nxv1f32(<vscale x 1 x float> %x)
ret <vscale x 1 x i64> %a
@@ -530,19 +212,8 @@ define <vscale x 2 x i64> @lrint_v2f32(<vscale x 2 x float> %x) {
; CHECK-LABEL: lrint_v2f32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov w8, #-553648128 // =0xdf000000
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z1.s, w8
-; CHECK-NEXT: mov w8, #1593835519 // =0x5effffff
; CHECK-NEXT: frintx z0.s, p0/m, z0.s
-; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z1.s
-; CHECK-NEXT: mov z1.s, w8
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.s
-; CHECK-NEXT: fcmgt p1.s, p0/z, z0.s, z1.s
-; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
; CHECK-NEXT: ret
%a = call <vscale x 2 x i64> @llvm.lrint.nxv2i64.nxv2f32(<vscale x 2 x float> %x)
ret <vscale x 2 x i64> %a
@@ -553,28 +224,14 @@ define <vscale x 4 x i64> @lrint_v4f32(<vscale x 4 x float> %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: uunpklo z1.d, z0.s
; CHECK-NEXT: uunpkhi z0.d, z0.s
-; CHECK-NEXT: mov w8, #-553648128 // =0xdf000000
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: mov w8, #1593835519 // =0x5effffff
-; CHECK-NEXT: mov z3.d, #0x8000000000000000
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov z5.d, #0x7fffffffffffffff
; CHECK-NEXT: frintx z1.s, p0/m, z1.s
-; CHECK-NEXT: frintx z0.s, p0/m, z0.s
-; CHECK-NEXT: fcmge p1.s, p0/z, z1.s, z2.s
-; CHECK-NEXT: fcmge p2.s, p0/z, z0.s, z2.s
-; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: fcmuo p3.s, p0/z, z1.s, z1.s
-; CHECK-NEXT: fcvtzs z4.d, p1/m, z1.s
-; CHECK-NEXT: fcmgt p1.s, p0/z, z1.s, z2.s
-; CHECK-NEXT: fcvtzs z3.d, p2/m, z0.s
-; CHECK-NEXT: fcmgt p2.s, p0/z, z0.s, z2.s
-; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
-; CHECK-NEXT: sel z0.d, p1, z5.d, z4.d
-; CHECK-NEXT: sel z1.d, p2, z5.d, z3.d
-; CHECK-NEXT: mov z0.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
+; CHECK-NEXT: movprfx z2, z0
+; CHECK-NEXT: frintx z2.s, p0/m, z0.s
+; CHECK-NEXT: movprfx z0, z1
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z1.s
+; CHECK-NEXT: movprfx z1, z2
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z2.s
; CHECK-NEXT: ret
%a = call <vscale x 4 x i64> @llvm.lrint.nxv4i64.nxv4f32(<vscale x 4 x float> %x)
ret <vscale x 4 x i64> %a
@@ -583,61 +240,25 @@ define <vscale x 4 x i64> @lrint_v4f32(<vscale x 4 x float> %x) {
define <vscale x 8 x i64> @lrint_v8f32(<vscale x 8 x float> %x) {
; CHECK-LABEL: lrint_v8f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: uunpklo z2.d, z0.s
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov w8, #-553648128 // =0xdf000000
; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: uunpklo z3.d, z1.s
; CHECK-NEXT: uunpkhi z1.d, z1.s
-; CHECK-NEXT: mov z4.s, w8
-; CHECK-NEXT: mov w8, #1593835519 // =0x5effffff
-; CHECK-NEXT: mov z5.d, #0x8000000000000000
-; CHECK-NEXT: mov z7.d, #0x8000000000000000
-; CHECK-NEXT: mov z24.d, #0x8000000000000000
-; CHECK-NEXT: mov z25.s, w8
+; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: frintx z2.s, p0/m, z2.s
-; CHECK-NEXT: mov z26.d, #0x8000000000000000
-; CHECK-NEXT: movprfx z6, z0
-; CHECK-NEXT: frintx z6.s, p0/m, z0.s
+; CHECK-NEXT: movprfx z4, z0
+; CHECK-NEXT: frintx z4.s, p0/m, z0.s
; CHECK-NEXT: frintx z3.s, p0/m, z3.s
-; CHECK-NEXT: frintx z1.s, p0/m, z1.s
-; CHECK-NEXT: fcmge p1.s, p0/z, z2.s, z4.s
-; CHECK-NEXT: fcmge p2.s, p0/z, z6.s, z4.s
-; CHECK-NEXT: fcmge p3.s, p0/z, z3.s, z4.s
-; CHECK-NEXT: fcmgt p4.s, p0/z, z2.s, z25.s
-; CHECK-NEXT: fcvtzs z5.d, p1/m, z2.s
-; CHECK-NEXT: fcmge p1.s, p0/z, z1.s, z4.s
-; CHECK-NEXT: mov z4.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcvtzs z7.d, p2/m, z6.s
-; CHECK-NEXT: fcvtzs z24.d, p3/m, z3.s
-; CHECK-NEXT: fcmgt p3.s, p0/z, z6.s, z25.s
-; CHECK-NEXT: fcmgt p5.s, p0/z, z3.s, z25.s
-; CHECK-NEXT: fcvtzs z26.d, p1/m, z1.s
-; CHECK-NEXT: sel z0.d, p4, z4.d, z5.d
-; CHECK-NEXT: fcmgt p1.s, p0/z, z1.s, z25.s
-; CHECK-NEXT: fcmuo p4.s, p0/z, z6.s, z6.s
-; CHECK-NEXT: fcmuo p6.s, p0/z, z3.s, z3.s
-; CHECK-NEXT: fcmuo p2.s, p0/z, z2.s, z2.s
-; CHECK-NEXT: sel z2.d, p5, z4.d, z24.d
-; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p0.s, p0/z, z1.s, z1.s
-; CHECK-NEXT: sel z1.d, p3, z4.d, z7.d
-; CHECK-NEXT: sel z3.d, p1, z4.d, z26.d
-; CHECK-NEXT: mov z2.d, p6/m, #0 // =0x0
-; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z1.d, p4/m, #0 // =0x0
-; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z0.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z3.d, p0/m, #0 // =0x0
-; CHECK-NEXT: addvl sp, sp, #1
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: movprfx z5, z1
+; CHECK-NEXT: frintx z5.s, p0/m, z1.s
+; CHECK-NEXT: movprfx z0, z2
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z2.s
+; CHECK-NEXT: movprfx z1, z4
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z4.s
+; CHECK-NEXT: movprfx z2, z3
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z3.s
+; CHECK-NEXT: movprfx z3, z5
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z5.s
; CHECK-NEXT: ret
%a = call <vscale x 8 x i64> @llvm.lrint.nxv8i64.nxv8f32(<vscale x 8 x float> %x)
ret <vscale x 8 x i64> %a
@@ -646,114 +267,43 @@ define <vscale x 8 x i64> @lrint_v8f32(<vscale x 8 x float> %x) {
define <vscale x 16 x i64> @lrint_v16f32(<vscale x 16 x float> %x) {
; CHECK-LABEL: lrint_v16f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-3
-; CHECK-NEXT: str p10, [sp, #1, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p9, [sp, #2, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p8, [sp, #3, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p7, [sp, #4, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: str z9, [sp, #1, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z8, [sp, #2, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x48, 0x1e, 0x22 // sp + 16 + 24 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x40, 0x1c // $d9 @ cfa - 16 * VG - 16
; CHECK-NEXT: uunpklo z4.d, z0.s
-; CHECK-NEXT: uunpkhi z5.d, z0.s
-; CHECK-NEXT: mov w8, #-553648128 // =0xdf000000
-; CHECK-NEXT: uunpkhi z7.d, z1.s
-; CHECK-NEXT: uunpklo z24.d, z2.s
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: uunpklo z6.d, z1.s
+; CHECK-NEXT: uunpkhi z0.d, z0.s
+; CHECK-NEXT: uunpklo z5.d, z1.s
+; CHECK-NEXT: uunpkhi z1.d, z1.s
+; CHECK-NEXT: uunpklo z6.d, z2.s
; CHECK-NEXT: uunpkhi z2.d, z2.s
-; CHECK-NEXT: mov z0.d, #0x8000000000000000
-; CHECK-NEXT: mov z1.d, #0x8000000000000000
-; CHECK-NEXT: mov z27.d, #0x8000000000000000
-; CHECK-NEXT: mov z28.d, #0x8000000000000000
-; CHECK-NEXT: movprfx z25, z4
-; CHECK-NEXT: frintx z25.s, p0/m, z4.s
+; CHECK-NEXT: uunpklo z7.d, z3.s
+; CHECK-NEXT: uunpkhi z3.d, z3.s
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: frintx z4.s, p0/m, z4.s
+; CHECK-NEXT: movprfx z24, z0
+; CHECK-NEXT: frintx z24.s, p0/m, z0.s
; CHECK-NEXT: frintx z5.s, p0/m, z5.s
-; CHECK-NEXT: mov z4.s, w8
-; CHECK-NEXT: mov w8, #1593835519 // =0x5effffff
-; CHECK-NEXT: frintx z7.s, p0/m, z7.s
-; CHECK-NEXT: frintx z24.s, p0/m, z24.s
-; CHECK-NEXT: movprfx z30, z2
-; CHECK-NEXT: frintx z30.s, p0/m, z2.s
+; CHECK-NEXT: movprfx z25, z1
+; CHECK-NEXT: frintx z25.s, p0/m, z1.s
; CHECK-NEXT: frintx z6.s, p0/m, z6.s
-; CHECK-NEXT: uunpklo z2.d, z3.s
-; CHECK-NEXT: mov z29.s, w8
-; CHECK-NEXT: mov z26.d, #0x8000000000000000
-; CHECK-NEXT: mov z31.d, #0x8000000000000000
-; CHECK-NEXT: mov z8.d, #0x8000000000000000
-; CHECK-NEXT: mov z9.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmge p5.s, p0/z, z25.s, z4.s
-; CHECK-NEXT: fcmge p1.s, p0/z, z5.s, z4.s
-; CHECK-NEXT: fcmge p3.s, p0/z, z7.s, z4.s
-; CHECK-NEXT: fcmge p4.s, p0/z, z24.s, z4.s
-; CHECK-NEXT: fcvtzs z0.d, p5/m, z25.s
-; CHECK-NEXT: fcvtzs z1.d, p1/m, z5.s
-; CHECK-NEXT: fcvtzs z27.d, p3/m, z7.s
-; CHECK-NEXT: fcmge p2.s, p0/z, z6.s, z4.s
-; CHECK-NEXT: fcvtzs z28.d, p4/m, z24.s
-; CHECK-NEXT: fcmgt p3.s, p0/z, z25.s, z29.s
-; CHECK-NEXT: fcmge p4.s, p0/z, z30.s, z4.s
-; CHECK-NEXT: fcmuo p1.s, p0/z, z25.s, z25.s
-; CHECK-NEXT: movprfx z25, z2
-; CHECK-NEXT: frintx z25.s, p0/m, z2.s
-; CHECK-NEXT: uunpkhi z2.d, z3.s
-; CHECK-NEXT: fcvtzs z26.d, p2/m, z6.s
-; CHECK-NEXT: mov z0.d, p3/m, z9.d
-; CHECK-NEXT: fcmgt p5.s, p0/z, z5.s, z29.s
-; CHECK-NEXT: fcvtzs z31.d, p4/m, z30.s
-; CHECK-NEXT: fcmuo p2.s, p0/z, z5.s, z5.s
-; CHECK-NEXT: movprfx z5, z2
-; CHECK-NEXT: frintx z5.s, p0/m, z2.s
-; CHECK-NEXT: mov z0.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcmge p4.s, p0/z, z25.s, z4.s
-; CHECK-NEXT: fcmgt p6.s, p0/z, z6.s, z29.s
-; CHECK-NEXT: mov z1.d, p5/m, z9.d
-; CHECK-NEXT: fcmgt p8.s, p0/z, z7.s, z29.s
-; CHECK-NEXT: fcmuo p10.s, p0/z, z7.s, z7.s
-; CHECK-NEXT: mov z7.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z8.d, p4/m, z25.s
-; CHECK-NEXT: mov z1.d, p2/m, #0 // =0x0
-; CHECK-NEXT: sel z2.d, p6, z9.d, z26.d
-; CHECK-NEXT: sel z3.d, p8, z9.d, z27.d
-; CHECK-NEXT: fcmge p4.s, p0/z, z5.s, z4.s
-; CHECK-NEXT: fcmgt p9.s, p0/z, z24.s, z29.s
-; CHECK-NEXT: fcmgt p5.s, p0/z, z30.s, z29.s
-; CHECK-NEXT: mov z3.d, p10/m, #0 // =0x0
-; CHECK-NEXT: ldr p10, [sp, #1, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmgt p6.s, p0/z, z25.s, z29.s
-; CHECK-NEXT: fcvtzs z7.d, p4/m, z5.s
-; CHECK-NEXT: fcmgt p4.s, p0/z, z5.s, z29.s
-; CHECK-NEXT: sel z4.d, p9, z9.d, z28.d
-; CHECK-NEXT: fcmuo p7.s, p0/z, z6.s, z6.s
-; CHECK-NEXT: sel z6.d, p6, z9.d, z8.d
-; CHECK-NEXT: ldr z8, [sp, #2, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p8.s, p0/z, z30.s, z30.s
-; CHECK-NEXT: fcmuo p9.s, p0/z, z25.s, z25.s
-; CHECK-NEXT: mov z7.d, p4/m, z9.d
-; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z2.d, p7/m, #0 // =0x0
-; CHECK-NEXT: ldr p7, [sp, #4, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p3.s, p0/z, z24.s, z24.s
-; CHECK-NEXT: fcmuo p0.s, p0/z, z5.s, z5.s
-; CHECK-NEXT: sel z5.d, p5, z9.d, z31.d
-; CHECK-NEXT: ldr z9, [sp, #1, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z6.d, p9/m, #0 // =0x0
-; CHECK-NEXT: ldr p9, [sp, #2, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z5.d, p8/m, #0 // =0x0
-; CHECK-NEXT: ldr p8, [sp, #3, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z4.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z7.d, p0/m, #0 // =0x0
-; CHECK-NEXT: addvl sp, sp, #3
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: movprfx z26, z2
+; CHECK-NEXT: frintx z26.s, p0/m, z2.s
+; CHECK-NEXT: frintx z7.s, p0/m, z7.s
+; CHECK-NEXT: movprfx z27, z3
+; CHECK-NEXT: frintx z27.s, p0/m, z3.s
+; CHECK-NEXT: movprfx z0, z4
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z4.s
+; CHECK-NEXT: movprfx z1, z24
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z24.s
+; CHECK-NEXT: movprfx z2, z5
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z5.s
+; CHECK-NEXT: movprfx z3, z25
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z25.s
+; CHECK-NEXT: movprfx z4, z6
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z6.s
+; CHECK-NEXT: movprfx z5, z26
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z26.s
+; CHECK-NEXT: movprfx z6, z7
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z7.s
+; CHECK-NEXT: movprfx z7, z27
+; CHECK-NEXT: fcvtzs z7.d, p0/m, z27.s
; CHECK-NEXT: ret
%a = call <vscale x 16 x i64> @llvm.lrint.nxv16i64.nxv16f32(<vscale x 16 x float> %x)
ret <vscale x 16 x i64> %a
@@ -762,251 +312,71 @@ define <vscale x 16 x i64> @lrint_v16f32(<vscale x 16 x float> %x) {
define <vscale x 32 x i64> @lrint_v32f32(<vscale x 32 x float> %x) {
; CHECK-LABEL: lrint_v32f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-18
-; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p11, [sp, #8, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p10, [sp, #9, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p9, [sp, #10, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p8, [sp, #11, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p7, [sp, #12, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p6, [sp, #13, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #14, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #15, mul vl] // 2-byte Spill
-; CHECK-NEXT: str z23, [sp, #2, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z22, [sp, #3, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z21, [sp, #4, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z20, [sp, #5, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z19, [sp, #6, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z18, [sp, #7, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z17, [sp, #8, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z16, [sp, #9, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0a, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x11, 0x98, 0x01, 0x1e, 0x22 // sp + 16 + 152 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x40, 0x1c // $d9 @ cfa - 16 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x68, 0x1e, 0x22, 0x40, 0x1c // $d10 @ cfa - 24 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4b, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x60, 0x1e, 0x22, 0x40, 0x1c // $d11 @ cfa - 32 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4c, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x58, 0x1e, 0x22, 0x40, 0x1c // $d12 @ cfa - 40 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4d, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x50, 0x1e, 0x22, 0x40, 0x1c // $d13 @ cfa - 48 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4e, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x48, 0x1e, 0x22, 0x40, 0x1c // $d14 @ cfa - 56 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4f, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x40, 0x1e, 0x22, 0x40, 0x1c // $d15 @ cfa - 64 * VG - 16
-; CHECK-NEXT: uunpklo z24.d, z0.s
-; CHECK-NEXT: uunpklo z26.d, z1.s
-; CHECK-NEXT: mov w9, #-553648128 // =0xdf000000
-; CHECK-NEXT: uunpklo z28.d, z2.s
-; CHECK-NEXT: uunpkhi z30.d, z2.s
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: uunpkhi z25.d, z0.s
-; CHECK-NEXT: uunpkhi z13.d, z3.s
-; CHECK-NEXT: uunpklo z14.d, z4.s
-; CHECK-NEXT: uunpkhi z27.d, z1.s
-; CHECK-NEXT: uunpklo z9.d, z3.s
-; CHECK-NEXT: mov z29.s, w9
-; CHECK-NEXT: movprfx z0, z24
-; CHECK-NEXT: frintx z0.s, p0/m, z24.s
-; CHECK-NEXT: movprfx z24, z26
-; CHECK-NEXT: frintx z24.s, p0/m, z26.s
-; CHECK-NEXT: mov w9, #1593835519 // =0x5effffff
-; CHECK-NEXT: movprfx z10, z28
-; CHECK-NEXT: frintx z10.s, p0/m, z28.s
-; CHECK-NEXT: frintx z30.s, p0/m, z30.s
-; CHECK-NEXT: uunpklo z17.d, z5.s
-; CHECK-NEXT: movprfx z1, z25
-; CHECK-NEXT: frintx z1.s, p0/m, z25.s
-; CHECK-NEXT: movprfx z15, z13
-; CHECK-NEXT: frintx z15.s, p0/m, z13.s
-; CHECK-NEXT: movprfx z13, z14
-; CHECK-NEXT: frintx z13.s, p0/m, z14.s
-; CHECK-NEXT: uunpkhi z14.d, z4.s
-; CHECK-NEXT: uunpkhi z18.d, z5.s
-; CHECK-NEXT: uunpkhi z19.d, z6.s
-; CHECK-NEXT: movprfx z25, z27
-; CHECK-NEXT: frintx z25.s, p0/m, z27.s
-; CHECK-NEXT: mov z27.d, #0x8000000000000000
-; CHECK-NEXT: mov z11.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p3.s, p0/z, z24.s, z29.s
-; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: mov z12.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p5.s, p0/z, z10.s, z29.s
-; CHECK-NEXT: frintx z9.s, p0/m, z9.s
-; CHECK-NEXT: uunpklo z20.d, z7.s
-; CHECK-NEXT: movprfx z5, z14
-; CHECK-NEXT: frintx z5.s, p0/m, z14.s
-; CHECK-NEXT: movprfx z14, z17
-; CHECK-NEXT: frintx z14.s, p0/m, z17.s
-; CHECK-NEXT: movprfx z17, z18
-; CHECK-NEXT: frintx z17.s, p0/m, z18.s
-; CHECK-NEXT: fcmge p6.s, p0/z, z30.s, z29.s
-; CHECK-NEXT: uunpkhi z7.d, z7.s
-; CHECK-NEXT: mov z31.s, w9
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z26.d, #0x8000000000000000
-; CHECK-NEXT: frintx z19.s, p0/m, z19.s
+; CHECK-NEXT: uunpkhi z24.d, z7.s
+; CHECK-NEXT: uunpkhi z25.d, z6.s
; CHECK-NEXT: uunpklo z6.d, z6.s
-; CHECK-NEXT: mov z28.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z27.d, p3/m, z24.s
-; CHECK-NEXT: fcvtzs z11.d, p5/m, z10.s
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov z16.d, #0x8000000000000000
-; CHECK-NEXT: movprfx z22, z7
-; CHECK-NEXT: frintx z22.s, p0/m, z7.s
-; CHECK-NEXT: fcvtzs z12.d, p6/m, z30.s
-; CHECK-NEXT: frintx z20.s, p0/m, z20.s
-; CHECK-NEXT: mov z21.d, #0x8000000000000000
-; CHECK-NEXT: mov z23.d, #0x8000000000000000
-; CHECK-NEXT: mov z8.d, #0x8000000000000000
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: uunpklo z7.d, z7.s
+; CHECK-NEXT: uunpkhi z26.d, z5.s
+; CHECK-NEXT: uunpklo z5.d, z5.s
+; CHECK-NEXT: uunpkhi z27.d, z4.s
+; CHECK-NEXT: uunpkhi z28.d, z1.s
+; CHECK-NEXT: uunpklo z4.d, z4.s
+; CHECK-NEXT: uunpkhi z29.d, z3.s
+; CHECK-NEXT: uunpklo z3.d, z3.s
+; CHECK-NEXT: frintx z24.s, p0/m, z24.s
; CHECK-NEXT: frintx z6.s, p0/m, z6.s
-; CHECK-NEXT: mov z3.d, #0x7fffffffffffffff
-; CHECK-NEXT: mov z18.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z29.s
-; CHECK-NEXT: fcmge p2.s, p0/z, z1.s, z29.s
-; CHECK-NEXT: fcmge p4.s, p0/z, z25.s, z29.s
-; CHECK-NEXT: fcmgt p9.s, p0/z, z10.s, z31.s
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.s
-; CHECK-NEXT: mov z0.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z26.d, p2/m, z1.s
-; CHECK-NEXT: fcvtzs z28.d, p4/m, z25.s
-; CHECK-NEXT: mov z11.d, p9/m, z3.d
-; CHECK-NEXT: fcmuo p8.s, p0/z, z10.s, z10.s
-; CHECK-NEXT: mov z10.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p5.s, p0/z, z9.s, z29.s
-; CHECK-NEXT: fcmge p3.s, p0/z, z15.s, z29.s
-; CHECK-NEXT: fcmge p6.s, p0/z, z13.s, z29.s
-; CHECK-NEXT: mov z11.d, p8/m, #0 // =0x0
-; CHECK-NEXT: fcvtzs z10.d, p5/m, z9.s
-; CHECK-NEXT: fcvtzs z4.d, p3/m, z15.s
-; CHECK-NEXT: fcvtzs z16.d, p6/m, z13.s
-; CHECK-NEXT: fcmge p1.s, p0/z, z17.s, z29.s
-; CHECK-NEXT: fcmge p2.s, p0/z, z19.s, z29.s
-; CHECK-NEXT: fcmgt p12.s, p0/z, z30.s, z31.s
-; CHECK-NEXT: fcmgt p5.s, p0/z, z15.s, z31.s
-; CHECK-NEXT: fcvtzs z21.d, p1/m, z17.s
-; CHECK-NEXT: fcmge p3.s, p0/z, z20.s, z29.s
-; CHECK-NEXT: fcvtzs z23.d, p2/m, z19.s
-; CHECK-NEXT: sel z7.d, p12, z3.d, z12.d
-; CHECK-NEXT: fcmgt p11.s, p0/z, z13.s, z31.s
-; CHECK-NEXT: mov z4.d, p5/m, z3.d
-; CHECK-NEXT: fcmge p4.s, p0/z, z22.s, z29.s
-; CHECK-NEXT: fcvtzs z0.d, p3/m, z20.s
-; CHECK-NEXT: fcmge p6.s, p0/z, z5.s, z29.s
-; CHECK-NEXT: fcmge p7.s, p0/z, z14.s, z29.s
-; CHECK-NEXT: sel z12.d, p11, z3.d, z16.d
-; CHECK-NEXT: fcvtzs z8.d, p4/m, z22.s
-; CHECK-NEXT: fcmuo p1.s, p0/z, z13.s, z13.s
-; CHECK-NEXT: fcmge p2.s, p0/z, z6.s, z29.s
-; CHECK-NEXT: mov z29.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z18.d, p7/m, z14.s
-; CHECK-NEXT: fcmuo p10.s, p0/z, z15.s, z15.s
-; CHECK-NEXT: mov z15.d, #0x8000000000000000
-; CHECK-NEXT: mov z12.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p4.s, p0/z, z22.s, z31.s
-; CHECK-NEXT: fcvtzs z29.d, p2/m, z6.s
-; CHECK-NEXT: fcmgt p5.s, p0/z, z20.s, z31.s
-; CHECK-NEXT: str z12, [x8, #8, mul vl]
-; CHECK-NEXT: fcvtzs z15.d, p6/m, z5.s
-; CHECK-NEXT: mov z4.d, p10/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p3.s, p0/z, z19.s, z31.s
-; CHECK-NEXT: mov z8.d, p4/m, z3.d
-; CHECK-NEXT: fcmuo p1.s, p0/z, z22.s, z22.s
-; CHECK-NEXT: str z4, [x8, #7, mul vl]
-; CHECK-NEXT: mov z0.d, p5/m, z3.d
-; CHECK-NEXT: fcmuo p2.s, p0/z, z20.s, z20.s
-; CHECK-NEXT: fcmuo p6.s, p0/z, z19.s, z19.s
-; CHECK-NEXT: fcmgt p4.s, p0/z, z5.s, z31.s
-; CHECK-NEXT: mov z8.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p5.s, p0/z, z5.s, z5.s
-; CHECK-NEXT: sel z5.d, p3, z3.d, z23.d
-; CHECK-NEXT: mov z0.d, p2/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p3.s, p0/z, z6.s, z31.s
-; CHECK-NEXT: str z8, [x8, #15, mul vl]
-; CHECK-NEXT: fcmgt p1.s, p0/z, z17.s, z31.s
-; CHECK-NEXT: str z0, [x8, #14, mul vl]
-; CHECK-NEXT: mov z5.d, p6/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p2.s, p0/z, z14.s, z31.s
-; CHECK-NEXT: sel z0.d, p3, z3.d, z29.d
-; CHECK-NEXT: fcmuo p6.s, p0/z, z6.s, z6.s
-; CHECK-NEXT: str z5, [x8, #13, mul vl]
-; CHECK-NEXT: sel z6.d, p4, z3.d, z15.d
-; CHECK-NEXT: sel z5.d, p1, z3.d, z21.d
-; CHECK-NEXT: fcmuo p4.s, p0/z, z17.s, z17.s
-; CHECK-NEXT: sel z29.d, p2, z3.d, z18.d
-; CHECK-NEXT: mov z6.d, p5/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p3.s, p0/z, z14.s, z14.s
-; CHECK-NEXT: mov z0.d, p6/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p1.s, p0/z, z1.s, z31.s
-; CHECK-NEXT: str z6, [x8, #9, mul vl]
-; CHECK-NEXT: mov z5.d, p4/m, #0 // =0x0
-; CHECK-NEXT: str z0, [x8, #12, mul vl]
-; CHECK-NEXT: mov z29.d, p3/m, #0 // =0x0
-; CHECK-NEXT: str z5, [x8, #11, mul vl]
-; CHECK-NEXT: sel z5.d, p1, z3.d, z26.d
-; CHECK-NEXT: fcmgt p2.s, p0/z, z24.s, z31.s
-; CHECK-NEXT: str z29, [x8, #10, mul vl]
-; CHECK-NEXT: ldr z4, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: str z11, [x8, #4, mul vl]
-; CHECK-NEXT: fcmgt p4.s, p0/z, z25.s, z31.s
-; CHECK-NEXT: fcmuo p3.s, p0/z, z30.s, z30.s
-; CHECK-NEXT: sel z26.d, p2, z3.d, z27.d
-; CHECK-NEXT: fcmgt p6.s, p0/z, z9.s, z31.s
-; CHECK-NEXT: fcmgt p1.s, p0/z, z4.s, z31.s
-; CHECK-NEXT: fcmuo p5.s, p0/z, z9.s, z9.s
-; CHECK-NEXT: sel z6.d, p4, z3.d, z28.d
-; CHECK-NEXT: mov z7.d, p3/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p2.s, p0/z, z25.s, z25.s
-; CHECK-NEXT: sel z0.d, p6, z3.d, z10.d
-; CHECK-NEXT: fcmuo p3.s, p0/z, z24.s, z24.s
-; CHECK-NEXT: fcmuo p4.s, p0/z, z1.s, z1.s
-; CHECK-NEXT: sel z1.d, p1, z3.d, z2.d
-; CHECK-NEXT: str z7, [x8, #5, mul vl]
-; CHECK-NEXT: fcmuo p0.s, p0/z, z4.s, z4.s
-; CHECK-NEXT: mov z0.d, p5/m, #0 // =0x0
-; CHECK-NEXT: mov z6.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z26.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z5.d, p4/m, #0 // =0x0
-; CHECK-NEXT: str z0, [x8, #6, mul vl]
-; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
-; CHECK-NEXT: str z6, [x8, #3, mul vl]
-; CHECK-NEXT: str z26, [x8, #2, mul vl]
-; CHECK-NEXT: str z5, [x8, #1, mul vl]
-; CHECK-NEXT: str z1, [x8]
-; CHECK-NEXT: addvl sp, sp, #1
-; CHECK-NEXT: ldr z23, [sp, #2, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z22, [sp, #3, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z21, [sp, #4, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z20, [sp, #5, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z19, [sp, #6, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z18, [sp, #7, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z17, [sp, #8, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z16, [sp, #9, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z15, [sp, #10, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z14, [sp, #11, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p7, [sp, #12, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p6, [sp, #13, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p5, [sp, #14, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p4, [sp, #15, mul vl] // 2-byte Reload
-; CHECK-NEXT: addvl sp, sp, #18
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: uunpklo z1.d, z1.s
+; CHECK-NEXT: frintx z7.s, p0/m, z7.s
+; CHECK-NEXT: frintx z25.s, p0/m, z25.s
+; CHECK-NEXT: frintx z26.s, p0/m, z26.s
+; CHECK-NEXT: frintx z5.s, p0/m, z5.s
+; CHECK-NEXT: frintx z27.s, p0/m, z27.s
+; CHECK-NEXT: frintx z28.s, p0/m, z28.s
+; CHECK-NEXT: frintx z4.s, p0/m, z4.s
+; CHECK-NEXT: frintx z29.s, p0/m, z29.s
+; CHECK-NEXT: frintx z3.s, p0/m, z3.s
+; CHECK-NEXT: fcvtzs z24.d, p0/m, z24.s
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.s
+; CHECK-NEXT: frintx z1.s, p0/m, z1.s
+; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.s
+; CHECK-NEXT: fcvtzs z25.d, p0/m, z25.s
+; CHECK-NEXT: fcvtzs z26.d, p0/m, z26.s
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.s
+; CHECK-NEXT: fcvtzs z27.d, p0/m, z27.s
+; CHECK-NEXT: fcvtzs z28.d, p0/m, z28.s
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.s
+; CHECK-NEXT: fcvtzs z29.d, p0/m, z29.s
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.s
+; CHECK-NEXT: str z24, [x8, #15, mul vl]
+; CHECK-NEXT: uunpkhi z24.d, z2.s
+; CHECK-NEXT: uunpklo z2.d, z2.s
+; CHECK-NEXT: str z6, [x8, #12, mul vl]
+; CHECK-NEXT: uunpkhi z6.d, z0.s
+; CHECK-NEXT: uunpklo z0.d, z0.s
+; CHECK-NEXT: str z7, [x8, #14, mul vl]
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.s
+; CHECK-NEXT: str z25, [x8, #13, mul vl]
+; CHECK-NEXT: str z26, [x8, #11, mul vl]
+; CHECK-NEXT: frintx z24.s, p0/m, z24.s
+; CHECK-NEXT: frintx z2.s, p0/m, z2.s
+; CHECK-NEXT: str z5, [x8, #10, mul vl]
+; CHECK-NEXT: frintx z6.s, p0/m, z6.s
+; CHECK-NEXT: frintx z0.s, p0/m, z0.s
+; CHECK-NEXT: str z27, [x8, #9, mul vl]
+; CHECK-NEXT: str z4, [x8, #8, mul vl]
+; CHECK-NEXT: str z29, [x8, #7, mul vl]
+; CHECK-NEXT: fcvtzs z24.d, p0/m, z24.s
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.s
+; CHECK-NEXT: str z3, [x8, #6, mul vl]
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.s
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-NEXT: str z28, [x8, #3, mul vl]
+; CHECK-NEXT: str z1, [x8, #2, mul vl]
+; CHECK-NEXT: str z24, [x8, #5, mul vl]
+; CHECK-NEXT: str z2, [x8, #4, mul vl]
+; CHECK-NEXT: str z6, [x8, #1, mul vl]
+; CHECK-NEXT: str z0, [x8]
; CHECK-NEXT: ret
%a = call <vscale x 32 x i64> @llvm.lrint.nxv32i64.nxv32f32(<vscale x 32 x float> %x)
ret <vscale x 32 x i64> %a
@@ -1016,19 +386,8 @@ define <vscale x 1 x i64> @lrint_v1f64(<vscale x 1 x double> %x) {
; CHECK-LABEL: lrint_v1f64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z1.d, x8
-; CHECK-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff
; CHECK-NEXT: frintx z0.d, p0/m, z0.d
-; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z1.d
-; CHECK-NEXT: mov z1.d, x8
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.d
-; CHECK-NEXT: fcmgt p1.d, p0/z, z0.d, z1.d
-; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
; CHECK-NEXT: ret
%a = call <vscale x 1 x i64> @llvm.lrint.nxv1i64.nxv1f64(<vscale x 1 x double> %x)
ret <vscale x 1 x i64> %a
@@ -1038,19 +397,8 @@ define <vscale x 2 x i64> @lrint_v2f64(<vscale x 2 x double> %x) {
; CHECK-LABEL: lrint_v2f64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z1.d, x8
-; CHECK-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff
; CHECK-NEXT: frintx z0.d, p0/m, z0.d
-; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z1.d
-; CHECK-NEXT: mov z1.d, x8
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.d
-; CHECK-NEXT: fcmgt p1.d, p0/z, z0.d, z1.d
-; CHECK-NEXT: mov z1.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: sel z0.d, p1, z1.d, z2.d
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
; CHECK-NEXT: ret
%a = call <vscale x 2 x i64> @llvm.lrint.nxv2i64.nxv2f64(<vscale x 2 x double> %x)
ret <vscale x 2 x i64> %a
@@ -1060,27 +408,10 @@ define <vscale x 4 x i64> @lrint_v4f64(<vscale x 4 x double> %x) {
; CHECK-LABEL: lrint_v4f64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000
-; CHECK-NEXT: mov z3.d, #0x8000000000000000
-; CHECK-NEXT: mov z2.d, x8
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff
; CHECK-NEXT: frintx z0.d, p0/m, z0.d
; CHECK-NEXT: frintx z1.d, p0/m, z1.d
-; CHECK-NEXT: mov z5.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z2.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z1.d, z2.d
-; CHECK-NEXT: mov z2.d, x8
-; CHECK-NEXT: fcmuo p3.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: fcvtzs z4.d, p1/m, z0.d
-; CHECK-NEXT: fcmgt p1.d, p0/z, z0.d, z2.d
-; CHECK-NEXT: fcvtzs z3.d, p2/m, z1.d
-; CHECK-NEXT: fcmgt p2.d, p0/z, z1.d, z2.d
-; CHECK-NEXT: fcmuo p0.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: sel z0.d, p1, z5.d, z4.d
-; CHECK-NEXT: sel z1.d, p2, z5.d, z3.d
-; CHECK-NEXT: mov z0.d, p3/m, #0 // =0x0
-; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
; CHECK-NEXT: ret
%a = call <vscale x 4 x i64> @llvm.lrint.nxv4i64.nxv4f64(<vscale x 4 x double> %x)
ret <vscale x 4 x i64> %a
@@ -1089,56 +420,15 @@ define <vscale x 4 x i64> @lrint_v4f64(<vscale x 4 x double> %x) {
define <vscale x 8 x i64> @lrint_v8f64(<vscale x 8 x double> %x) {
; CHECK-LABEL: lrint_v8f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000
-; CHECK-NEXT: mov z4.d, #0x8000000000000000
-; CHECK-NEXT: mov z5.d, x8
-; CHECK-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff
-; CHECK-NEXT: mov z6.d, #0x8000000000000000
; CHECK-NEXT: frintx z0.d, p0/m, z0.d
; CHECK-NEXT: frintx z1.d, p0/m, z1.d
; CHECK-NEXT: frintx z2.d, p0/m, z2.d
-; CHECK-NEXT: mov z24.d, x8
; CHECK-NEXT: frintx z3.d, p0/m, z3.d
-; CHECK-NEXT: mov z7.d, #0x8000000000000000
-; CHECK-NEXT: mov z25.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z5.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z1.d, z5.d
-; CHECK-NEXT: fcmge p3.d, p0/z, z2.d, z5.d
-; CHECK-NEXT: fcmgt p4.d, p0/z, z0.d, z24.d
-; CHECK-NEXT: fcvtzs z4.d, p1/m, z0.d
-; CHECK-NEXT: fcmge p1.d, p0/z, z3.d, z5.d
-; CHECK-NEXT: mov z5.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z6.d, p2/m, z1.d
-; CHECK-NEXT: fcvtzs z7.d, p3/m, z2.d
-; CHECK-NEXT: fcmuo p2.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: fcmgt p3.d, p0/z, z1.d, z24.d
-; CHECK-NEXT: sel z0.d, p4, z25.d, z4.d
-; CHECK-NEXT: fcmgt p4.d, p0/z, z2.d, z24.d
-; CHECK-NEXT: fcvtzs z5.d, p1/m, z3.d
-; CHECK-NEXT: fcmgt p1.d, p0/z, z3.d, z24.d
-; CHECK-NEXT: fcmuo p5.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: mov z0.d, p2/m, #0 // =0x0
-; CHECK-NEXT: sel z1.d, p3, z25.d, z6.d
-; CHECK-NEXT: fcmuo p6.d, p0/z, z2.d, z2.d
-; CHECK-NEXT: sel z2.d, p4, z25.d, z7.d
-; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p0.d, p0/z, z3.d, z3.d
-; CHECK-NEXT: sel z3.d, p1, z25.d, z5.d
-; CHECK-NEXT: mov z1.d, p5/m, #0 // =0x0
-; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z2.d, p6/m, #0 // =0x0
-; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z3.d, p0/m, #0 // =0x0
-; CHECK-NEXT: addvl sp, sp, #1
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
; CHECK-NEXT: ret
%a = call <vscale x 8 x i64> @llvm.lrint.nxv8i64.nxv8f64(<vscale x 8 x double> %x)
ret <vscale x 8 x i64> %a
@@ -1147,103 +437,23 @@ define <vscale x 8 x i64> @lrint_v8f64(<vscale x 8 x double> %x) {
define <vscale x 16 x i64> @lrint_v16f64(<vscale x 16 x double> %x) {
; CHECK-LABEL: lrint_v16f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-3
-; CHECK-NEXT: str p10, [sp, #1, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p9, [sp, #2, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p8, [sp, #3, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p7, [sp, #4, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: str z9, [sp, #1, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z8, [sp, #2, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x48, 0x1e, 0x22 // sp + 16 + 24 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x40, 0x1c // $d9 @ cfa - 16 * VG - 16
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000
-; CHECK-NEXT: mov z25.d, #0x8000000000000000
-; CHECK-NEXT: mov z28.d, #0x8000000000000000
-; CHECK-NEXT: mov z26.d, #0x8000000000000000
-; CHECK-NEXT: mov z27.d, #0x8000000000000000
-; CHECK-NEXT: movprfx z24, z0
-; CHECK-NEXT: frintx z24.d, p0/m, z0.d
-; CHECK-NEXT: frintx z3.d, p0/m, z3.d
-; CHECK-NEXT: mov z0.d, x8
+; CHECK-NEXT: frintx z0.d, p0/m, z0.d
; CHECK-NEXT: frintx z1.d, p0/m, z1.d
-; CHECK-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff
; CHECK-NEXT: frintx z2.d, p0/m, z2.d
+; CHECK-NEXT: frintx z3.d, p0/m, z3.d
; CHECK-NEXT: frintx z4.d, p0/m, z4.d
-; CHECK-NEXT: frintx z6.d, p0/m, z6.d
-; CHECK-NEXT: mov z30.d, x8
-; CHECK-NEXT: mov z29.d, #0x8000000000000000
; CHECK-NEXT: frintx z5.d, p0/m, z5.d
+; CHECK-NEXT: frintx z6.d, p0/m, z6.d
; CHECK-NEXT: frintx z7.d, p0/m, z7.d
-; CHECK-NEXT: mov z31.d, #0x8000000000000000
-; CHECK-NEXT: mov z8.d, #0x7fffffffffffffff
-; CHECK-NEXT: mov z9.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p1.d, p0/z, z24.d, z0.d
-; CHECK-NEXT: fcmge p4.d, p0/z, z3.d, z0.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z1.d, z0.d
-; CHECK-NEXT: fcmge p3.d, p0/z, z2.d, z0.d
-; CHECK-NEXT: fcvtzs z25.d, p1/m, z24.d
-; CHECK-NEXT: fcvtzs z28.d, p4/m, z3.d
-; CHECK-NEXT: fcvtzs z26.d, p2/m, z1.d
-; CHECK-NEXT: fcmge p5.d, p0/z, z4.d, z0.d
-; CHECK-NEXT: fcvtzs z27.d, p3/m, z2.d
-; CHECK-NEXT: fcmgt p4.d, p0/z, z24.d, z30.d
-; CHECK-NEXT: fcmuo p1.d, p0/z, z24.d, z24.d
-; CHECK-NEXT: mov z24.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p7.d, p0/z, z6.d, z0.d
-; CHECK-NEXT: fcvtzs z29.d, p5/m, z4.d
-; CHECK-NEXT: fcmge p3.d, p0/z, z5.d, z0.d
-; CHECK-NEXT: fcmgt p5.d, p0/z, z1.d, z30.d
-; CHECK-NEXT: fcvtzs z24.d, p7/m, z6.d
-; CHECK-NEXT: fcmgt p6.d, p0/z, z2.d, z30.d
-; CHECK-NEXT: fcmge p7.d, p0/z, z7.d, z0.d
-; CHECK-NEXT: fcvtzs z31.d, p3/m, z5.d
-; CHECK-NEXT: sel z0.d, p4, z8.d, z25.d
-; CHECK-NEXT: fcmgt p8.d, p0/z, z3.d, z30.d
-; CHECK-NEXT: fcmgt p9.d, p0/z, z4.d, z30.d
-; CHECK-NEXT: mov z0.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcvtzs z9.d, p7/m, z7.d
-; CHECK-NEXT: fcmuo p2.d, p0/z, z1.d, z1.d
-; CHECK-NEXT: sel z1.d, p5, z8.d, z26.d
-; CHECK-NEXT: fcmuo p3.d, p0/z, z2.d, z2.d
-; CHECK-NEXT: sel z2.d, p6, z8.d, z27.d
-; CHECK-NEXT: fcmgt p5.d, p0/z, z5.d, z30.d
-; CHECK-NEXT: fcmgt p6.d, p0/z, z6.d, z30.d
-; CHECK-NEXT: mov z1.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z2.d, p3/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p7.d, p0/z, z7.d, z30.d
-; CHECK-NEXT: fcmuo p10.d, p0/z, z3.d, z3.d
-; CHECK-NEXT: sel z3.d, p8, z8.d, z28.d
-; CHECK-NEXT: fcmuo p4.d, p0/z, z4.d, z4.d
-; CHECK-NEXT: sel z4.d, p9, z8.d, z29.d
-; CHECK-NEXT: fcmuo p8.d, p0/z, z5.d, z5.d
-; CHECK-NEXT: sel z5.d, p5, z8.d, z31.d
-; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p9.d, p0/z, z6.d, z6.d
-; CHECK-NEXT: sel z6.d, p6, z8.d, z24.d
-; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z3.d, p10/m, #0 // =0x0
-; CHECK-NEXT: ldr p10, [sp, #1, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z4.d, p4/m, #0 // =0x0
-; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z5.d, p8/m, #0 // =0x0
-; CHECK-NEXT: ldr p8, [sp, #3, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z6.d, p9/m, #0 // =0x0
-; CHECK-NEXT: ldr p9, [sp, #2, mul vl] // 2-byte Reload
-; CHECK-NEXT: fcmuo p0.d, p0/z, z7.d, z7.d
-; CHECK-NEXT: sel z7.d, p7, z8.d, z9.d
-; CHECK-NEXT: ldr z9, [sp, #1, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z8, [sp, #2, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr p7, [sp, #4, mul vl] // 2-byte Reload
-; CHECK-NEXT: mov z7.d, p0/m, #0 // =0x0
-; CHECK-NEXT: addvl sp, sp, #3
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.d
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.d
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.d
+; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.d
; CHECK-NEXT: ret
%a = call <vscale x 16 x i64> @llvm.lrint.nxv16i64.nxv16f64(<vscale x 16 x double> %x)
ret <vscale x 16 x i64> %a
@@ -1252,242 +462,71 @@ define <vscale x 16 x i64> @lrint_v16f64(<vscale x 16 x double> %x) {
define <vscale x 32 x i64> @lrint_v32f64(<vscale x 32 x double> %x) {
; CHECK-LABEL: lrint_v32f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: addvl sp, sp, #-18
-; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p11, [sp, #8, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p10, [sp, #9, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p9, [sp, #10, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p8, [sp, #11, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p7, [sp, #12, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p6, [sp, #13, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p5, [sp, #14, mul vl] // 2-byte Spill
-; CHECK-NEXT: str p4, [sp, #15, mul vl] // 2-byte Spill
-; CHECK-NEXT: str z23, [sp, #2, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z22, [sp, #3, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z21, [sp, #4, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z20, [sp, #5, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z19, [sp, #6, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z18, [sp, #7, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z17, [sp, #8, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z16, [sp, #9, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0a, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x11, 0x90, 0x01, 0x1e, 0x22 // sp + 16 + 144 * VG
-; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x40, 0x1c // $d9 @ cfa - 16 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x68, 0x1e, 0x22, 0x40, 0x1c // $d10 @ cfa - 24 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4b, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x60, 0x1e, 0x22, 0x40, 0x1c // $d11 @ cfa - 32 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4c, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x58, 0x1e, 0x22, 0x40, 0x1c // $d12 @ cfa - 40 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4d, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x50, 0x1e, 0x22, 0x40, 0x1c // $d13 @ cfa - 48 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4e, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x48, 0x1e, 0x22, 0x40, 0x1c // $d14 @ cfa - 56 * VG - 16
-; CHECK-NEXT: .cfi_escape 0x10, 0x4f, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x40, 0x1e, 0x22, 0x40, 0x1c // $d15 @ cfa - 64 * VG - 16
-; CHECK-NEXT: ldr z0, [x0]
-; CHECK-NEXT: ldr z7, [x0, #3, mul vl]
+; CHECK-NEXT: ldr z0, [x0, #15, mul vl]
+; CHECK-NEXT: ldr z1, [x0, #14, mul vl]
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: ldr z27, [x0, #4, mul vl]
-; CHECK-NEXT: ldr z4, [x0, #2, mul vl]
-; CHECK-NEXT: mov x9, #-4332462841530417152 // =0xc3e0000000000000
-; CHECK-NEXT: mov z25.d, x9
-; CHECK-NEXT: ldr z2, [x0, #1, mul vl]
-; CHECK-NEXT: ldr z29, [x0, #6, mul vl]
+; CHECK-NEXT: ldr z2, [x0, #13, mul vl]
+; CHECK-NEXT: ldr z3, [x0, #12, mul vl]
+; CHECK-NEXT: ldr z4, [x0, #11, mul vl]
+; CHECK-NEXT: ldr z5, [x0, #10, mul vl]
+; CHECK-NEXT: ldr z6, [x0, #9, mul vl]
+; CHECK-NEXT: ldr z7, [x0, #8, mul vl]
; CHECK-NEXT: frintx z0.d, p0/m, z0.d
-; CHECK-NEXT: frintx z7.d, p0/m, z7.d
-; CHECK-NEXT: ldr z31, [x0, #7, mul vl]
-; CHECK-NEXT: movprfx z14, z27
-; CHECK-NEXT: frintx z14.d, p0/m, z27.d
+; CHECK-NEXT: frintx z1.d, p0/m, z1.d
+; CHECK-NEXT: ldr z24, [x0, #7, mul vl]
+; CHECK-NEXT: ldr z25, [x0, #6, mul vl]
+; CHECK-NEXT: frintx z2.d, p0/m, z2.d
+; CHECK-NEXT: frintx z3.d, p0/m, z3.d
+; CHECK-NEXT: ldr z26, [x0, #5, mul vl]
+; CHECK-NEXT: ldr z27, [x0, #4, mul vl]
; CHECK-NEXT: frintx z4.d, p0/m, z4.d
-; CHECK-NEXT: ldr z27, [x0, #5, mul vl]
-; CHECK-NEXT: ldr z15, [x0, #8, mul vl]
-; CHECK-NEXT: mov x9, #4890909195324358655 // =0x43dfffffffffffff
-; CHECK-NEXT: movprfx z3, z2
-; CHECK-NEXT: frintx z3.d, p0/m, z2.d
-; CHECK-NEXT: mov z2.d, #0x8000000000000000
-; CHECK-NEXT: mov z24.d, #0x8000000000000000
-; CHECK-NEXT: mov z30.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z25.d
-; CHECK-NEXT: movprfx z28, z27
-; CHECK-NEXT: frintx z28.d, p0/m, z27.d
+; CHECK-NEXT: ldr z28, [x0, #3, mul vl]
+; CHECK-NEXT: ldr z29, [x0, #2, mul vl]
+; CHECK-NEXT: frintx z5.d, p0/m, z5.d
+; CHECK-NEXT: ldr z30, [x0, #1, mul vl]
+; CHECK-NEXT: ldr z31, [x0]
+; CHECK-NEXT: frintx z6.d, p0/m, z6.d
+; CHECK-NEXT: frintx z7.d, p0/m, z7.d
+; CHECK-NEXT: frintx z24.d, p0/m, z24.d
+; CHECK-NEXT: frintx z25.d, p0/m, z25.d
+; CHECK-NEXT: frintx z26.d, p0/m, z26.d
+; CHECK-NEXT: frintx z27.d, p0/m, z27.d
+; CHECK-NEXT: frintx z28.d, p0/m, z28.d
; CHECK-NEXT: frintx z29.d, p0/m, z29.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z7.d, z25.d
-; CHECK-NEXT: mov z1.d, x9
-; CHECK-NEXT: mov z6.d, #0x8000000000000000
-; CHECK-NEXT: fcmge p3.d, p0/z, z14.d, z25.d
-; CHECK-NEXT: ldr z11, [x0, #13, mul vl]
-; CHECK-NEXT: ldr z18, [x0, #11, mul vl]
-; CHECK-NEXT: fcmge p5.d, p0/z, z4.d, z25.d
-; CHECK-NEXT: ldr z19, [x0, #9, mul vl]
-; CHECK-NEXT: movprfx z20, z31
-; CHECK-NEXT: frintx z20.d, p0/m, z31.d
-; CHECK-NEXT: frintx z15.d, p0/m, z15.d
-; CHECK-NEXT: ldr z9, [x0, #15, mul vl]
-; CHECK-NEXT: ldr z10, [x0, #14, mul vl]
-; CHECK-NEXT: fcvtzs z2.d, p1/m, z0.d
-; CHECK-NEXT: fcvtzs z24.d, p2/m, z7.d
-; CHECK-NEXT: mov z12.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z30.d, p3/m, z14.d
-; CHECK-NEXT: mov z31.d, #0x8000000000000000
-; CHECK-NEXT: frintx z18.d, p0/m, z18.d
-; CHECK-NEXT: fcmge p1.d, p0/z, z28.d, z25.d
-; CHECK-NEXT: mov z5.d, #0x8000000000000000
-; CHECK-NEXT: ldr z8, [x0, #12, mul vl]
-; CHECK-NEXT: fcmgt p10.d, p0/z, z14.d, z1.d
-; CHECK-NEXT: ldr z13, [x0, #10, mul vl]
-; CHECK-NEXT: fcvtzs z6.d, p5/m, z4.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z29.d, z25.d
-; CHECK-NEXT: mov z16.d, #0x8000000000000000
-; CHECK-NEXT: mov z17.d, #0x8000000000000000
-; CHECK-NEXT: frintx z10.d, p0/m, z10.d
-; CHECK-NEXT: frintx z9.d, p0/m, z9.d
-; CHECK-NEXT: mov z21.d, #0x8000000000000000
-; CHECK-NEXT: fcvtzs z12.d, p1/m, z28.d
-; CHECK-NEXT: frintx z13.d, p0/m, z13.d
-; CHECK-NEXT: mov z22.d, #0x8000000000000000
-; CHECK-NEXT: frintx z8.d, p0/m, z8.d
-; CHECK-NEXT: mov z26.d, #0x8000000000000000
-; CHECK-NEXT: mov z27.d, #0x7fffffffffffffff
-; CHECK-NEXT: fcvtzs z31.d, p2/m, z29.d
-; CHECK-NEXT: mov z23.d, #0x8000000000000000
-; CHECK-NEXT: fcmuo p8.d, p0/z, z14.d, z14.d
-; CHECK-NEXT: movprfx z14, z19
-; CHECK-NEXT: frintx z14.d, p0/m, z19.d
-; CHECK-NEXT: movprfx z19, z11
-; CHECK-NEXT: frintx z19.d, p0/m, z11.d
-; CHECK-NEXT: mov z11.d, #0x8000000000000000
-; CHECK-NEXT: mov z30.d, p10/m, z27.d
-; CHECK-NEXT: fcmge p4.d, p0/z, z3.d, z25.d
-; CHECK-NEXT: fcmge p5.d, p0/z, z20.d, z25.d
-; CHECK-NEXT: mov z30.d, p8/m, #0 // =0x0
-; CHECK-NEXT: fcmge p6.d, p0/z, z15.d, z25.d
-; CHECK-NEXT: fcvtzs z5.d, p4/m, z3.d
-; CHECK-NEXT: fcmge p1.d, p0/z, z18.d, z25.d
-; CHECK-NEXT: str z30, [x8, #4, mul vl]
-; CHECK-NEXT: fcvtzs z16.d, p5/m, z20.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z19.d, z25.d
-; CHECK-NEXT: fcvtzs z17.d, p6/m, z15.d
-; CHECK-NEXT: fcmgt p5.d, p0/z, z20.d, z1.d
-; CHECK-NEXT: fcmge p3.d, p0/z, z10.d, z25.d
-; CHECK-NEXT: fcvtzs z21.d, p1/m, z18.d
-; CHECK-NEXT: fcvtzs z22.d, p2/m, z19.d
-; CHECK-NEXT: fcmgt p11.d, p0/z, z15.d, z1.d
-; CHECK-NEXT: fcmge p4.d, p0/z, z9.d, z25.d
-; CHECK-NEXT: fcmge p6.d, p0/z, z14.d, z25.d
-; CHECK-NEXT: fcvtzs z23.d, p3/m, z10.d
-; CHECK-NEXT: fcmge p7.d, p0/z, z13.d, z25.d
-; CHECK-NEXT: fcmuo p1.d, p0/z, z15.d, z15.d
-; CHECK-NEXT: sel z15.d, p5, z27.d, z16.d
-; CHECK-NEXT: sel z16.d, p11, z27.d, z17.d
-; CHECK-NEXT: fcvtzs z26.d, p4/m, z9.d
-; CHECK-NEXT: fcvtzs z11.d, p6/m, z14.d
-; CHECK-NEXT: fcmge p2.d, p0/z, z8.d, z25.d
-; CHECK-NEXT: mov z25.d, #0x8000000000000000
-; CHECK-NEXT: mov z16.d, p1/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p4.d, p0/z, z9.d, z1.d
-; CHECK-NEXT: fcmgt p5.d, p0/z, z10.d, z1.d
-; CHECK-NEXT: str z16, [x8, #8, mul vl]
-; CHECK-NEXT: fcvtzs z25.d, p2/m, z8.d
-; CHECK-NEXT: fcmgt p3.d, p0/z, z19.d, z1.d
-; CHECK-NEXT: fcmuo p9.d, p0/z, z20.d, z20.d
-; CHECK-NEXT: mov z20.d, #0x8000000000000000
-; CHECK-NEXT: mov z26.d, p4/m, z27.d
-; CHECK-NEXT: fcmuo p1.d, p0/z, z9.d, z9.d
-; CHECK-NEXT: sel z9.d, p5, z27.d, z23.d
-; CHECK-NEXT: fcmuo p2.d, p0/z, z10.d, z10.d
-; CHECK-NEXT: sel z10.d, p3, z27.d, z22.d
-; CHECK-NEXT: fcvtzs z20.d, p7/m, z13.d
-; CHECK-NEXT: mov z15.d, p9/m, #0 // =0x0
-; CHECK-NEXT: mov z26.d, p1/m, #0 // =0x0
-; CHECK-NEXT: mov z9.d, p2/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p4.d, p0/z, z14.d, z1.d
-; CHECK-NEXT: str z15, [x8, #7, mul vl]
-; CHECK-NEXT: fcmgt p3.d, p0/z, z8.d, z1.d
-; CHECK-NEXT: str z26, [x8, #15, mul vl]
-; CHECK-NEXT: fcmuo p6.d, p0/z, z19.d, z19.d
-; CHECK-NEXT: str z9, [x8, #14, mul vl]
-; CHECK-NEXT: fcmgt p1.d, p0/z, z18.d, z1.d
-; CHECK-NEXT: fcmgt p2.d, p0/z, z13.d, z1.d
-; CHECK-NEXT: sel z26.d, p4, z27.d, z11.d
-; CHECK-NEXT: mov z25.d, p3/m, z27.d
-; CHECK-NEXT: fcmuo p4.d, p0/z, z18.d, z18.d
-; CHECK-NEXT: mov z10.d, p6/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p3.d, p0/z, z13.d, z13.d
-; CHECK-NEXT: sel z9.d, p2, z27.d, z20.d
-; CHECK-NEXT: fcmgt p12.d, p0/z, z28.d, z1.d
-; CHECK-NEXT: str z10, [x8, #13, mul vl]
-; CHECK-NEXT: fcmuo p6.d, p0/z, z8.d, z8.d
-; CHECK-NEXT: sel z8.d, p1, z27.d, z21.d
-; CHECK-NEXT: mov z9.d, p3/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p1.d, p0/z, z3.d, z1.d
-; CHECK-NEXT: fcmuo p5.d, p0/z, z14.d, z14.d
-; CHECK-NEXT: mov z8.d, p4/m, #0 // =0x0
-; CHECK-NEXT: mov z12.d, p12/m, z27.d
-; CHECK-NEXT: str z9, [x8, #10, mul vl]
-; CHECK-NEXT: mov z25.d, p6/m, #0 // =0x0
-; CHECK-NEXT: fcmgt p2.d, p0/z, z4.d, z1.d
-; CHECK-NEXT: str z8, [x8, #11, mul vl]
-; CHECK-NEXT: mov z5.d, p1/m, z27.d
-; CHECK-NEXT: fcmgt p4.d, p0/z, z7.d, z1.d
-; CHECK-NEXT: str z25, [x8, #12, mul vl]
-; CHECK-NEXT: mov z26.d, p5/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p3.d, p0/z, z28.d, z28.d
-; CHECK-NEXT: mov z6.d, p2/m, z27.d
-; CHECK-NEXT: fcmgt p6.d, p0/z, z29.d, z1.d
-; CHECK-NEXT: str z26, [x8, #9, mul vl]
-; CHECK-NEXT: fcmgt p1.d, p0/z, z0.d, z1.d
-; CHECK-NEXT: mov z24.d, p4/m, z27.d
-; CHECK-NEXT: mov z12.d, p3/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p5.d, p0/z, z29.d, z29.d
-; CHECK-NEXT: fcmuo p2.d, p0/z, z7.d, z7.d
-; CHECK-NEXT: sel z25.d, p6, z27.d, z31.d
-; CHECK-NEXT: str z12, [x8, #5, mul vl]
-; CHECK-NEXT: fcmuo p3.d, p0/z, z4.d, z4.d
-; CHECK-NEXT: fcmuo p4.d, p0/z, z3.d, z3.d
-; CHECK-NEXT: mov z25.d, p5/m, #0 // =0x0
-; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
-; CHECK-NEXT: sel z0.d, p1, z27.d, z2.d
-; CHECK-NEXT: mov z24.d, p2/m, #0 // =0x0
-; CHECK-NEXT: mov z6.d, p3/m, #0 // =0x0
+; CHECK-NEXT: frintx z30.d, p0/m, z30.d
+; CHECK-NEXT: frintx z31.d, p0/m, z31.d
+; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
+; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
+; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
+; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.d
+; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.d
+; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.d
+; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.d
+; CHECK-NEXT: fcvtzs z24.d, p0/m, z24.d
+; CHECK-NEXT: fcvtzs z25.d, p0/m, z25.d
+; CHECK-NEXT: fcvtzs z26.d, p0/m, z26.d
+; CHECK-NEXT: fcvtzs z27.d, p0/m, z27.d
+; CHECK-NEXT: fcvtzs z28.d, p0/m, z28.d
+; CHECK-NEXT: fcvtzs z29.d, p0/m, z29.d
+; CHECK-NEXT: fcvtzs z30.d, p0/m, z30.d
+; CHECK-NEXT: fcvtzs z31.d, p0/m, z31.d
+; CHECK-NEXT: str z0, [x8, #15, mul vl]
+; CHECK-NEXT: str z1, [x8, #14, mul vl]
+; CHECK-NEXT: str z2, [x8, #13, mul vl]
+; CHECK-NEXT: str z3, [x8, #12, mul vl]
+; CHECK-NEXT: str z4, [x8, #11, mul vl]
+; CHECK-NEXT: str z5, [x8, #10, mul vl]
+; CHECK-NEXT: str z6, [x8, #9, mul vl]
+; CHECK-NEXT: str z7, [x8, #8, mul vl]
+; CHECK-NEXT: str z24, [x8, #7, mul vl]
; CHECK-NEXT: str z25, [x8, #6, mul vl]
-; CHECK-NEXT: mov z5.d, p4/m, #0 // =0x0
-; CHECK-NEXT: str z24, [x8, #3, mul vl]
-; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
-; CHECK-NEXT: str z6, [x8, #2, mul vl]
-; CHECK-NEXT: str z5, [x8, #1, mul vl]
-; CHECK-NEXT: str z0, [x8]
-; CHECK-NEXT: ldr z23, [sp, #2, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z22, [sp, #3, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z21, [sp, #4, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z20, [sp, #5, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z19, [sp, #6, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z18, [sp, #7, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z17, [sp, #8, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z16, [sp, #9, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z15, [sp, #10, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z14, [sp, #11, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
-; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p7, [sp, #12, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p6, [sp, #13, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p5, [sp, #14, mul vl] // 2-byte Reload
-; CHECK-NEXT: ldr p4, [sp, #15, mul vl] // 2-byte Reload
-; CHECK-NEXT: addvl sp, sp, #18
-; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: str z26, [x8, #5, mul vl]
+; CHECK-NEXT: str z27, [x8, #4, mul vl]
+; CHECK-NEXT: str z28, [x8, #3, mul vl]
+; CHECK-NEXT: str z29, [x8, #2, mul vl]
+; CHECK-NEXT: str z30, [x8, #1, mul vl]
+; CHECK-NEXT: str z31, [x8]
; CHECK-NEXT: ret
%a = call <vscale x 32 x i64> @llvm.lrint.nxv32i64.nxv16f64(<vscale x 32 x double> %x)
ret <vscale x 32 x i64> %a
>From 9d4d91d3dadc77c8814d8dcca64c2c0de24e21c7 Mon Sep 17 00:00:00 2001
From: Sander de Smalen <sander.desmalen at arm.com>
Date: Tue, 21 Jul 2026 13:24:53 +0000
Subject: [PATCH 3/3] Various small changes
* Fixed issue with lowering v8bf16 -> v8i32 when using 256b SVE (as that would otherwise go down a legalisation route specifically added for 128b NEON).
* Removed unnecessary condition for `SrcVT != MVT::nxv2f32` in CanHandleNatively, as this no longer applies.
* Renamed `tryLowerFPToIntToSVE` -> `LowerFPToIntToSVE`
* Moved bail out for saturating narrowing converts (fixed-length SVE) to `LowerFixedLengthFPToIntToSVE`
---
.../Target/AArch64/AArch64ISelLowering.cpp | 34 +++++----
llvm/lib/Target/AArch64/AArch64ISelLowering.h | 2 +-
.../AArch64/sve-fixed-length-fp-to-int-sat.ll | 69 +++++++++++++++++++
3 files changed, 89 insertions(+), 16 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 6b12415db14dd..313b3391c63b7 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -5095,7 +5095,7 @@ SDValue AArch64TargetLowering::LowerVectorFP_TO_INT(SDValue Op,
DAG.getNode(ISD::FP_EXTEND, DL, NewVT, Op.getOperand(0)));
}
- if (SDValue Res = tryLowerFPToIntToSVE(Op, DAG))
+ if (SDValue Res = LowerFPToIntToSVE(Op, DAG))
return Res;
uint64_t VTSize = VT.getFixedSizeInBits();
@@ -5201,13 +5201,12 @@ AArch64TargetLowering::LowerVectorFP_TO_INT_SAT(SDValue Op,
SrcElementVT != MVT::f16 && SrcElementVT != MVT::bf16)
return SDValue();
- if (SDValue Res = tryLowerFPToIntToSVE(Op, DAG))
+ if (SDValue Res = LowerFPToIntToSVE(Op, DAG))
return Res;
// Returns true if the operation can be matched by an isel pattern directly.
auto CanHandleNatively = [&DstVT, &SatWidth](EVT SrcVT) -> bool {
- return SrcVT != MVT::nxv2f32 &&
- SrcVT.getScalarSizeInBits() == DstVT.getScalarSizeInBits() &&
+ return SrcVT.getScalarSizeInBits() == DstVT.getScalarSizeInBits() &&
SrcVT.getScalarSizeInBits() == SatWidth;
};
@@ -5248,7 +5247,7 @@ AArch64TargetLowering::LowerVectorFP_TO_INT_SAT(SDValue Op,
if (PromVT && !Expand(*PromVT)) {
// When promoting the input type, SatWidth stays unchanged.
SrcVal = DAG.getNode(ISD::FP_EXTEND, DL, *PromVT, SrcVal);
- if (*PromVT != MVT::v8f32)
+ if (*PromVT != MVT::v8f32 || isTypeLegal(MVT::v8f32))
return DAG.getNode(Op.getOpcode(), DL, DstVT, SrcVal, Op.getOperand(1));
// If we are extending to a wider type (e.g. v8f16 -> v8f32) due to lack
@@ -34744,8 +34743,8 @@ static unsigned getSVEOpcodeForFPToInt(unsigned Opc) {
}
}
-SDValue AArch64TargetLowering::tryLowerFPToIntToSVE(SDValue Op,
- SelectionDAG &DAG) const {
+SDValue AArch64TargetLowering::LowerFPToIntToSVE(SDValue Op,
+ SelectionDAG &DAG) const {
// Strict FP_TO_INT is not yet implemented.
if (Op->isStrictFPOpcode())
return SDValue();
@@ -34785,11 +34784,6 @@ SDValue AArch64TargetLowering::tryLowerFPToIntToSVE(SDValue Op,
Op->getFlags());
}
- // FIXME: LowerFixedLengthFPToIntToSVE doesn't properly implement
- // saturation yet.
- if (VT.getScalarSizeInBits() < InVT.getScalarSizeInBits())
- return SDValue();
-
bool UseSVE = !Subtarget->isNeonAvailable();
if (useSVEForFixedLengthVectorVT(VT, UseSVE) ||
useSVEForFixedLengthVectorVT(InVT, UseSVE))
@@ -34802,16 +34796,26 @@ SDValue
AArch64TargetLowering::LowerFixedLengthFPToIntToSVE(SDValue Op,
SelectionDAG &DAG) const {
EVT VT = Op.getValueType();
+ unsigned Opc = Op.getOpcode();
assert(VT.isFixedLengthVector() && "Expected fixed length vector type!");
assert(!Op->isStrictFPOpcode() && "Strict FP_TO_INT not yet supported");
unsigned Opcode = getSVEOpcodeForFPToInt(Op.getOpcode());
- SDLoc DL(Op);
+ bool IsSaturating = Opc == ISD::FP_TO_UINT_SAT || Opc == ISD::FP_TO_SINT_SAT;
+ assert((!IsSaturating || (VT.getVectorElementType() ==
+ cast<VTSDNode>(Op.getOperand(1))->getVT())) &&
+ "Can't handle saturation to a different type than the destination VT");
+
SDValue Val = Op.getOperand(0);
EVT SrcVT = Val.getValueType();
- EVT ContainerDstVT = getContainerForFixedLengthVector(DAG, VT);
- EVT ContainerSrcVT = getContainerForFixedLengthVector(DAG, SrcVT);
+ // FIXME: Saturating to smaller type isn't properly supported yet.
+ if (VT.bitsLT(SrcVT) && IsSaturating)
+ return SDValue();
+
+ SDLoc DL(Op);
+ EVT ContainerSrcVT = getContainerForFixedLengthVector(DAG, SrcVT);
+ EVT ContainerDstVT = getContainerForFixedLengthVector(DAG, VT);
if (VT.bitsGT(SrcVT)) {
EVT CvtVT = ContainerDstVT.changeVectorElementType(
*DAG.getContext(), ContainerSrcVT.getVectorElementType());
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 6827356b7c194..9c2ea0faee5ec 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -811,7 +811,7 @@ class AArch64TargetLowering : public TargetLowering {
SDValue LowerFCANONICALIZE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerAVG(SDValue Op, SelectionDAG &DAG, unsigned NewOp) const;
- SDValue tryLowerFPToIntToSVE(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerFPToIntToSVE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFixedLengthVectorIntDivideToSVE(SDValue Op,
SelectionDAG &DAG) const;
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int-sat.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int-sat.ll
index 67fcb506c64b2..a079e902ea664 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int-sat.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int-sat.ll
@@ -197,3 +197,72 @@ define void @test_signed_v16f16_v16i32(ptr %p) {
store <16 x i32> %cvt, ptr %p
ret void
}
+
+; bfloat
+
+define void @test_signed_v16bf16_v16i16(ptr %p) {
+; CHECK-LABEL: test_signed_v16bf16_v16i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ptrue p0.s, vl8
+; CHECK-NEXT: mov z2.s, #32767 // =0x7fff
+; CHECK-NEXT: mov z3.s, #-32768 // =0xffffffffffff8000
+; CHECK-NEXT: uunpklo z1.s, z1.h
+; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: lsl z1.s, z1.s, #16
+; CHECK-NEXT: lsl z0.s, z0.s, #16
+; CHECK-NEXT: fcvtzs z1.s, p0/m, z1.s
+; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-NEXT: smin z1.s, p0/m, z1.s, z2.s
+; CHECK-NEXT: smin z0.s, p0/m, z0.s, z2.s
+; CHECK-NEXT: smax z1.s, p0/m, z1.s, z3.s
+; CHECK-NEXT: smax z0.s, p0/m, z0.s, z3.s
+; CHECK-NEXT: ptrue p0.h, vl8
+; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h
+; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
+; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ptrue p0.h, vl16
+; CHECK-NEXT: st1h { z0.h }, p0, [x0]
+; CHECK-NEXT: ret
+ %ld = load <16 x bfloat>, ptr %p
+ %cvt = call <16 x i16> @llvm.fptosi.sat(<16 x bfloat> %ld)
+ store <16 x i16> %cvt, ptr %p
+ ret void
+}
+
+define void @test_signed_v8bf16_v8i32(ptr %p) {
+; CHECK-LABEL: test_signed_v8bf16_v8i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: ptrue p0.s, vl8
+; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: lsl z0.s, z0.s, #16
+; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-NEXT: st1w { z0.s }, p0, [x0]
+; CHECK-NEXT: ret
+ %ld = load <8 x bfloat>, ptr %p
+ %cvt = call <8 x i32> @llvm.fptosi.sat(<8 x bfloat> %ld)
+ store <8 x i32> %cvt, ptr %p
+ ret void
+}
+
+define void @test_signed_v16bf16_v16i32(ptr %p) {
+; CHECK-LABEL: test_signed_v16bf16_v16i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q1, q0, [x0]
+; CHECK-NEXT: ptrue p0.s, vl8
+; CHECK-NEXT: mov x8, #8 // =0x8
+; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: uunpklo z1.s, z1.h
+; CHECK-NEXT: lsl z0.s, z0.s, #16
+; CHECK-NEXT: lsl z1.s, z1.s, #16
+; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-NEXT: fcvtzs z1.s, p0/m, z1.s
+; CHECK-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2]
+; CHECK-NEXT: st1w { z1.s }, p0, [x0]
+; CHECK-NEXT: ret
+ %ld = load <16 x bfloat>, ptr %p
+ %cvt = call <16 x i32> @llvm.fptosi.sat(<16 x bfloat> %ld)
+ store <16 x i32> %cvt, ptr %p
+ ret void
+}
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