[llvm] [AArch64] Reuse NeoverseN1 and N2 scheduling models for A76/A77/A78. (PR #211209)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 22 02:17:01 PDT 2026
https://github.com/davemgreen created https://github.com/llvm/llvm-project/pull/211209
We do not have native scheduling models for some of the Cortex-A generations of CPUs, so they were still using the old Cortex-A57 model. Whilst not perfectly accurate, the NeoverseN1 and NoeverseN2 scheduling models should be a better fit for these CPUs. I mostly just tried to make sure the number of pipelines matches between the neoverse core and the cortex core. If we need something more accurate then we can start adding new models for the CPUs.
>From 4760ae1b4393e649ec18bd86371707399ffa97c8 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Wed, 22 Jul 2026 10:12:43 +0100
Subject: [PATCH] [AArch64] Reuse NeoverseN1 and N2 scheduling models for
A76/A77/A78.
We do not have native scheduling models for some of the Cortex-A generations of
CPUs, so they were still using the old Cortex-A57 model. Whilst not perfectly
accurate, the NeoverseN1 and NoeverseN2 scheduling models should be a better
fit for these CPUs. I mostly just tried to make sure the number of pipelines
matches between the neoverse core and the cortex core. If we need something
more accurate then we can start adding new models for the CPUs.
---
llvm/lib/Target/AArch64/AArch64Processors.td | 12 ++---
.../AArch64/Cortex/A76-basic-instructions.s | 38 +++++++++++++++
.../AArch64/Cortex/A78-basic-instructions.s | 46 +++++++++++++++++++
3 files changed, 90 insertions(+), 6 deletions(-)
create mode 100644 llvm/test/tools/llvm-mca/AArch64/Cortex/A76-basic-instructions.s
create mode 100644 llvm/test/tools/llvm-mca/AArch64/Cortex/A78-basic-instructions.s
diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td
index e71aa4d2779e6..0ee9aa5a882de 100644
--- a/llvm/lib/Target/AArch64/AArch64Processors.td
+++ b/llvm/lib/Target/AArch64/AArch64Processors.td
@@ -1317,17 +1317,17 @@ def : ProcessorModel<"cortex-a73", CortexA57Model, ProcessorFeatures.A53,
[TuneA73]>;
def : ProcessorModel<"cortex-a75", CortexA57Model, ProcessorFeatures.A55,
[TuneA75]>;
-def : ProcessorModel<"cortex-a76", CortexA57Model, ProcessorFeatures.A76,
+def : ProcessorModel<"cortex-a76", NeoverseN1Model, ProcessorFeatures.A76,
[TuneA76]>;
-def : ProcessorModel<"cortex-a76ae", CortexA57Model, ProcessorFeatures.A76,
+def : ProcessorModel<"cortex-a76ae", NeoverseN1Model, ProcessorFeatures.A76,
[TuneA76]>;
-def : ProcessorModel<"cortex-a77", CortexA57Model, ProcessorFeatures.A77,
+def : ProcessorModel<"cortex-a77", NeoverseN2Model, ProcessorFeatures.A77,
[TuneA77]>;
-def : ProcessorModel<"cortex-a78", CortexA57Model, ProcessorFeatures.A78,
+def : ProcessorModel<"cortex-a78", NeoverseN2Model, ProcessorFeatures.A78,
[TuneA78]>;
-def : ProcessorModel<"cortex-a78ae", CortexA57Model, ProcessorFeatures.A78AE,
+def : ProcessorModel<"cortex-a78ae", NeoverseN2Model, ProcessorFeatures.A78AE,
[TuneA78AE]>;
-def : ProcessorModel<"cortex-a78c", CortexA57Model, ProcessorFeatures.A78C,
+def : ProcessorModel<"cortex-a78c", NeoverseN2Model, ProcessorFeatures.A78C,
[TuneA78C]>;
def : ProcessorModel<"cortex-a710", NeoverseN2Model, ProcessorFeatures.A710,
[TuneA710]>;
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/A76-basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/A76-basic-instructions.s
new file mode 100644
index 0000000000000..4a11e910097dc
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/A76-basic-instructions.s
@@ -0,0 +1,38 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a76 -instruction-tables < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a76ae -instruction-tables < %s | FileCheck %s
+
+# These CPUs currently reuse the NeoverseN1 scheduling model
+
+add w2, w3, #4095
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.33 add w2, w3, #4095
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - N1UnitB
+# CHECK-NEXT: [1.0] - N1UnitD
+# CHECK-NEXT: [1.1] - N1UnitD
+# CHECK-NEXT: [2.0] - N1UnitL
+# CHECK-NEXT: [2.1] - N1UnitL
+# CHECK-NEXT: [3] - N1UnitM
+# CHECK-NEXT: [4.0] - N1UnitS
+# CHECK-NEXT: [4.1] - N1UnitS
+# CHECK-NEXT: [5] - N1UnitV0
+# CHECK-NEXT: [6] - N1UnitV1
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1.0] [1.1] [2.0] [2.1] [3] [4.0] [4.1] [5] [6]
+# CHECK-NEXT: - - - - - 0.33 0.33 0.33 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1.0] [1.1] [2.0] [2.1] [3] [4.0] [4.1] [5] [6] Instructions:
+# CHECK-NEXT: - - - - - 0.33 0.33 0.33 - - add w2, w3, #4095
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/A78-basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/A78-basic-instructions.s
new file mode 100644
index 0000000000000..b97f18974060b
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/A78-basic-instructions.s
@@ -0,0 +1,46 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a77 -instruction-tables < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a78 -instruction-tables < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a78ae -instruction-tables < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a78c -instruction-tables < %s | FileCheck %s
+
+# These CPUs currently reuse the NeoverseN2 scheduling model
+
+add w2, w3, #4095
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 add w2, w3, #4095
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - N2UnitB
+# CHECK-NEXT: [0.1] - N2UnitB
+# CHECK-NEXT: [1.0] - N2UnitD
+# CHECK-NEXT: [1.1] - N2UnitD
+# CHECK-NEXT: [2.0] - N2UnitFlg
+# CHECK-NEXT: [2.1] - N2UnitFlg
+# CHECK-NEXT: [2.2] - N2UnitFlg
+# CHECK-NEXT: [3] - N2UnitL2
+# CHECK-NEXT: [4.0] - N2UnitL01
+# CHECK-NEXT: [4.1] - N2UnitL01
+# CHECK-NEXT: [5] - N2UnitM0
+# CHECK-NEXT: [6] - N2UnitM1
+# CHECK-NEXT: [7.0] - N2UnitS
+# CHECK-NEXT: [7.1] - N2UnitS
+# CHECK-NEXT: [8] - N2UnitV0
+# CHECK-NEXT: [9] - N2UnitV1
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9]
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] Instructions:
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - add w2, w3, #4095
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