[llvm] [AArch64] Add A57 schedule model for CAS instructions (PR #211195)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 22 01:03:02 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: Andrew Savonichev (asavonic)
<details>
<summary>Changes</summary>
CAS instructions (B, H, W, X variants) are not described in the ARM Cortex-A57 Software Optimization Guide. There used to be no schedule model for them, so `llvm-mca` was unable to analyze code containing these instructions:
llvm-mca -mtriple=aarch64 -mcpu=cortex-a57 -mattr=+lse casb.s
error: found an unsupported instruction in the input assembly
sequence, use -skip-unsupported-instructions=lack-sched to ignore
these on the input.
note: instruction: casb w0, w1, [sp]
The patch adds a basic schedule model of 14 cycles (as measured on Cortex-A78 with llvm-exegesis) and L/S utilized pipelines (this is a guess, the reality is likely more complicated).
---
Full diff: https://github.com/llvm/llvm-project/pull/211195.diff
3 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64SchedA57.td (+4)
- (modified) llvm/lib/Target/AArch64/AArch64SchedA57WriteRes.td (+3)
- (added) llvm/test/tools/llvm-mca/AArch64/Cortex/A57-cas.s (+78)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA57.td b/llvm/lib/Target/AArch64/AArch64SchedA57.td
index 9260379fb5b27..dcc793966abed 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA57.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA57.td
@@ -690,5 +690,9 @@ def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRWpre)>;
def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRXpost)>;
def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRXpre)>;
def : InstRW<[A57Write_2cyc_2S], (instrs STURQi)>;
+def : InstRW<[A57Write_14cyc_1L_1S], (instrs CASB, CASH, CASW, CASX)>;
+def : InstRW<[A57Write_14cyc_1L_1S], (instrs CASAB, CASAH, CASAW, CASAX)>;
+def : InstRW<[A57Write_14cyc_1L_1S], (instrs CASLB, CASLH, CASLW, CASLX)>;
+def : InstRW<[A57Write_14cyc_1L_1S], (instrs CASALB, CASALH, CASALW, CASALX)>;
} // SchedModel = CortexA57Model
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA57WriteRes.td b/llvm/lib/Target/AArch64/AArch64SchedA57WriteRes.td
index fd16e98bff805..3883325d1b870 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA57WriteRes.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA57WriteRes.td
@@ -190,6 +190,9 @@ def A57Write_4cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
let Latency = 4;
let NumMicroOps = 2;
}
+def A57Write_14cyc_1L_1S : SchedWriteRes<[A57UnitL, A57UnitS]> {
+ let Latency = 14;
+}
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/A57-cas.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/A57-cas.s
new file mode 100644
index 0000000000000..c00860e6eb1b6
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/A57-cas.s
@@ -0,0 +1,78 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a57 -mattr=+lse -instruction-tables < %s | FileCheck %s
+
+caslb w0, w1, [sp]
+casalb w0, w1, [sp]
+casab w0, w1, [sp]
+casb w0, w1, [sp]
+casal w0, w1, [sp]
+casa w0, w1, [sp]
+casl w0, w1, [sp]
+cas w0, w1, [sp]
+casah w0, w1, [sp]
+casalh w0, w1, [sp]
+caslh w0, w1, [sp]
+cash w0, w1, [sp]
+casal x0, x1, [sp]
+casl x0, x1, [sp]
+cas x0, x1, [sp]
+casa x0, x1, [sp]
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 14 1.00 * * U caslb w0, w1, [sp]
+# CHECK-NEXT: 1 14 1.00 * * U casalb w0, w1, [sp]
+# CHECK-NEXT: 1 14 1.00 * * U casab w0, w1, [sp]
+# CHECK-NEXT: 1 14 1.00 * * U casb w0, w1, [sp]
+# CHECK-NEXT: 1 14 1.00 * * U casal w0, w1, [sp]
+# CHECK-NEXT: 1 14 1.00 * * U casa w0, w1, [sp]
+# CHECK-NEXT: 1 14 1.00 * * U casl w0, w1, [sp]
+# CHECK-NEXT: 1 14 1.00 * * U cas w0, w1, [sp]
+# CHECK-NEXT: 1 14 1.00 * * U casah w0, w1, [sp]
+# CHECK-NEXT: 1 14 1.00 * * U casalh w0, w1, [sp]
+# CHECK-NEXT: 1 14 1.00 * * U caslh w0, w1, [sp]
+# CHECK-NEXT: 1 14 1.00 * * U cash w0, w1, [sp]
+# CHECK-NEXT: 1 14 1.00 * * U casal x0, x1, [sp]
+# CHECK-NEXT: 1 14 1.00 * * U casl x0, x1, [sp]
+# CHECK-NEXT: 1 14 1.00 * * U cas x0, x1, [sp]
+# CHECK-NEXT: 1 14 1.00 * * U casa x0, x1, [sp]
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - A57UnitB
+# CHECK-NEXT: [1.0] - A57UnitI
+# CHECK-NEXT: [1.1] - A57UnitI
+# CHECK-NEXT: [2] - A57UnitL
+# CHECK-NEXT: [3] - A57UnitM
+# CHECK-NEXT: [4] - A57UnitS
+# CHECK-NEXT: [5] - A57UnitW
+# CHECK-NEXT: [6] - A57UnitX
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6]
+# CHECK-NEXT: - - - 16.00 - 16.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: - - - 1.00 - 1.00 - - caslb w0, w1, [sp]
+# CHECK-NEXT: - - - 1.00 - 1.00 - - casalb w0, w1, [sp]
+# CHECK-NEXT: - - - 1.00 - 1.00 - - casab w0, w1, [sp]
+# CHECK-NEXT: - - - 1.00 - 1.00 - - casb w0, w1, [sp]
+# CHECK-NEXT: - - - 1.00 - 1.00 - - casal w0, w1, [sp]
+# CHECK-NEXT: - - - 1.00 - 1.00 - - casa w0, w1, [sp]
+# CHECK-NEXT: - - - 1.00 - 1.00 - - casl w0, w1, [sp]
+# CHECK-NEXT: - - - 1.00 - 1.00 - - cas w0, w1, [sp]
+# CHECK-NEXT: - - - 1.00 - 1.00 - - casah w0, w1, [sp]
+# CHECK-NEXT: - - - 1.00 - 1.00 - - casalh w0, w1, [sp]
+# CHECK-NEXT: - - - 1.00 - 1.00 - - caslh w0, w1, [sp]
+# CHECK-NEXT: - - - 1.00 - 1.00 - - cash w0, w1, [sp]
+# CHECK-NEXT: - - - 1.00 - 1.00 - - casal x0, x1, [sp]
+# CHECK-NEXT: - - - 1.00 - 1.00 - - casl x0, x1, [sp]
+# CHECK-NEXT: - - - 1.00 - 1.00 - - cas x0, x1, [sp]
+# CHECK-NEXT: - - - 1.00 - 1.00 - - casa x0, x1, [sp]
``````````
</details>
https://github.com/llvm/llvm-project/pull/211195
More information about the llvm-commits
mailing list