[llvm] [CodeGen] Add MachineRegisterClassInfo analysis pass (PR #210826)

[Matt Arsenault via llvm-commits]

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@@ -71,6 +71,8 @@ class SIPreAllocateWWMRegsLegacy : public MachineFunctionPass {
     AU.addRequired<LiveIntervalsWrapperPass>();
     AU.addRequired<VirtRegMapWrapperLegacy>();
     AU.addRequired<LiveRegMatrixWrapperLegacy>();
+    // TODO: Update RCI with the additional reserved registers the pass sets.
+    AU.addRequired<MachineRegisterClassInfoWrapperPass>();
     AU.setPreservesAll();
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arsenm wrote:

We probably should add test coverage trying to break this too. I'm surprised there wasn't any test fallout 

https://github.com/llvm/llvm-project/pull/210826