[llvm] Add missing opcode for offset validity check (PR #211186)

[Santanu Das via llvm-commits]

https://github.com/quic-santdas created https://github.com/llvm/llvm-project/pull/211186

During offset validity check, the common API in HexagonInstrInfo does not handle the opcode. Adding it fixes wherever offset calculation is made for the instruction.

>From 4081005553f34edebc1475327ad7832a570fc813 Mon Sep 17 00:00:00 2001
From: quic-santdas <quic_santdas at quicinc.com>
Date: Mon, 25 Nov 2024 03:48:18 -0800
Subject: [PATCH] Add missing opcode for offset validity check

During offset validity check, the common API in HexagonInstrInfo
does not handle the opcode. Adding it fixes wherever offset
calculation is made for the instruction.

Change-Id: Ic3e31c69f8e68985f6c892b0554e4be8a0010384
Reviewed-on: https://review-hexagon.quicinc.com/c/llvm/llvm-project/+/458581
Reviewed-by: Yashas Andaluri <quic_yandalur at quicinc.com>
Reviewed-by: Santanu Das <santdas at qti.qualcomm.com>
Tested-by: hex build <hexbuild at quicinc.com>
---
 llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp  |  1 +
 .../CodeGen/Hexagon/amode-opt-vS32Ub-pred.mir | 30 +++++++++++++++++++
 2 files changed, 31 insertions(+)
 create mode 100644 llvm/test/CodeGen/Hexagon/amode-opt-vS32Ub-pred.mir

diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 3bc4e2f050262..daeb384515578 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -2833,6 +2833,7 @@ bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
   case Hexagon::V6_vL32b_nt_cur_npred_ai:
   case Hexagon::V6_vL32b_nt_tmp_pred_ai:
   case Hexagon::V6_vL32b_nt_tmp_npred_ai:
+  case Hexagon::V6_vS32Ub_pred_ai:
   case Hexagon::V6_vS32Ub_npred_ai:
   case Hexagon::V6_vgathermh_pseudo:
   case Hexagon::V6_vgather_vscatter_mh_pseudo:
diff --git a/llvm/test/CodeGen/Hexagon/amode-opt-vS32Ub-pred.mir b/llvm/test/CodeGen/Hexagon/amode-opt-vS32Ub-pred.mir
new file mode 100644
index 0000000000000..df8c470d9ec4e
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/amode-opt-vS32Ub-pred.mir
@@ -0,0 +1,30 @@
+# RUN: llc -mtriple=hexagon -mcpu=hexagonv65 -mhvx -run-pass=amode-opt %s -o /dev/null
+# REQUIRES: asserts
+
+# Tests that we don't hit the unreachable code with message
+# Failed Opcode is : V6_vS32Ub_pred_ai
+# No offset range is defined for this opcode
+#
+# The amode-opt pass folds an A2_addi into the base register of a load/store.
+# For V6_vS32Ub_pred_ai the opcode was missing from isValidOffset(), causing
+# an unreachable to be hit.
+
+--- |
+  target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
+  target triple = "hexagon"
+
+  define void @test(ptr %p) {
+    ret void
+  }
+...
+
+---
+name:            test
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $r0, $p0, $v0
+
+    $r1 = A2_addi $r0, 64
+    V6_vS32Ub_pred_ai $p0, $r1, 0, $v0
+...