[llvm] [RISCV] Support uimm5 operands for Xqcicm cmovs (PR #210955)

[Sudharsan Veeravalli via llvm-commits]

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@@ -376,10 +377,12 @@ bool RISCVExpandPseudo::expandCCOpToCMov(MachineBasicBlock &MBB,
   case RISCV::BGEU:
     CMovRegOpcode = RISCV::QC_MVLTU;
     CMovImmOpcode = RISCV::QC_MVLTUI;
+    IsSigned = false;
     break;
   case RISCV::BLTU:
     CMovRegOpcode = RISCV::QC_MVGEU;
     CMovImmOpcode = RISCV::QC_MVGEUI;
+    IsSigned = false;
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svs-quic wrote:

I think for these two case we will almost always chose the CMovRegOpcode with the immediate being loaded into a register. I have added the IsSigned check here as well but wasn't able to figure out a test.

Any thoughts?

https://github.com/llvm/llvm-project/pull/210955