[llvm] [AArch64][SVE] Allow scalable factor-3 interleaved accesses (PR #200424)

[David Green via llvm-commits]

davemgreen wrote:

> There was an unsafe PR for i1 deinterleaves/interleaves here: #209231.

That was something a little different. This is for standard i1 intrinsics, not deinterleaving-loads / stores. They might need to be lowered to stack loads/stores still, but should do so in a way that uses valid types not attempt to store the i1 vectors directly.

https://github.com/llvm/llvm-project/pull/200424