[llvm] 3ef7c5a - [GlobalISel][AMDGPU][test] fix cttz/cltz tests in no-assert builds (#210926)
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Tue Jul 21 03:36:45 PDT 2026
Author: Alan Li
Date: 2026-07-21T10:36:40Z
New Revision: 3ef7c5afbc977d238ab1d69473dbf3da3e3347b3
URL: https://github.com/llvm/llvm-project/commit/3ef7c5afbc977d238ab1d69473dbf3da3e3347b3
DIFF: https://github.com/llvm/llvm-project/commit/3ef7c5afbc977d238ab1d69473dbf3da3e3347b3.diff
LOG: [GlobalISel][AMDGPU][test] fix cttz/cltz tests in no-assert builds (#210926)
A follow up PR of https://github.com/llvm/llvm-project/pull/198438
This is to address post commit test issues:
https://lab.llvm.org/buildbot/#/builders/202/builds/726
Keep the normal combine and unknown-input baseline coverage enabled in
all builds, and move the named rule-disable checks into an
assertion-only test.
Added:
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ctlz-cttz-zero-poison-disable-rule.ll
Modified:
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ctlz-cttz-zero-poison.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ctlz-cttz-zero-poison-disable-rule.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ctlz-cttz-zero-poison-disable-rule.ll
new file mode 100644
index 0000000000000..f9f0ef47552de
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ctlz-cttz-zero-poison-disable-rule.ll
@@ -0,0 +1,86 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -global-isel \
+; RUN: --amdgpuprelegalizercombiner-disable-rule=ctlz_to_ctlz_zero_poison,cttz_to_cttz_zero_poison \
+; RUN: --amdgpupostlegalizercombiner-disable-rule=ctlz_to_ctlz_zero_poison,cttz_to_cttz_zero_poison \
+; RUN: %s -o - | FileCheck -check-prefix=GCN-NOCOMBINE %s
+; REQUIRES: asserts
+
+; Verify the baseline lowering when the CTLZ/CTTZ -> *_ZERO_POISON combines
+; are disabled. The symbolic combiner rule names are available only in
+; assertion-enabled builds.
+
+declare i32 @llvm.ctlz.i32(i32, i1)
+declare i32 @llvm.cttz.i32(i32, i1)
+declare i64 @llvm.ctlz.i64(i64, i1)
+declare i64 @llvm.cttz.i64(i64, i1)
+
+define i32 @ctlz_or1(i32 %x) {
+; GCN-NOCOMBINE-LABEL: ctlz_or1:
+; GCN-NOCOMBINE: ; %bb.0:
+; GCN-NOCOMBINE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NOCOMBINE-NEXT: v_or_b32_e32 v0, 1, v0
+; GCN-NOCOMBINE-NEXT: v_ffbh_u32_e32 v0, v0
+; GCN-NOCOMBINE-NEXT: v_min_u32_e32 v0, 32, v0
+; GCN-NOCOMBINE-NEXT: s_setpc_b64 s[30:31]
+ %or = or i32 %x, 1
+ %r = call i32 @llvm.ctlz.i32(i32 %or, i1 false)
+ ret i32 %r
+}
+
+define i32 @cttz_or1(i32 %x) {
+; GCN-NOCOMBINE-LABEL: cttz_or1:
+; GCN-NOCOMBINE: ; %bb.0:
+; GCN-NOCOMBINE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NOCOMBINE-NEXT: v_or_b32_e32 v0, 1, v0
+; GCN-NOCOMBINE-NEXT: v_ffbl_b32_e32 v0, v0
+; GCN-NOCOMBINE-NEXT: v_min_u32_e32 v0, 32, v0
+; GCN-NOCOMBINE-NEXT: s_setpc_b64 s[30:31]
+ %or = or i32 %x, 1
+ %r = call i32 @llvm.cttz.i32(i32 %or, i1 false)
+ ret i32 %r
+}
+
+define i32 @ctlz_shl1(i32 %n) {
+; GCN-NOCOMBINE-LABEL: ctlz_shl1:
+; GCN-NOCOMBINE: ; %bb.0:
+; GCN-NOCOMBINE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NOCOMBINE-NEXT: v_lshlrev_b32_e64 v0, v0, 1
+; GCN-NOCOMBINE-NEXT: v_ffbh_u32_e32 v0, v0
+; GCN-NOCOMBINE-NEXT: v_min_u32_e32 v0, 32, v0
+; GCN-NOCOMBINE-NEXT: s_setpc_b64 s[30:31]
+ %s = shl i32 1, %n
+ %r = call i32 @llvm.ctlz.i32(i32 %s, i1 false)
+ ret i32 %r
+}
+
+define i64 @ctlz_or1_i64(i64 %x) {
+; GCN-NOCOMBINE-LABEL: ctlz_or1_i64:
+; GCN-NOCOMBINE: ; %bb.0:
+; GCN-NOCOMBINE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NOCOMBINE-NEXT: v_or_b32_e32 v0, 1, v0
+; GCN-NOCOMBINE-NEXT: v_ffbh_u32_e32 v0, v0
+; GCN-NOCOMBINE-NEXT: v_ffbh_u32_e32 v1, v1
+; GCN-NOCOMBINE-NEXT: v_add_u32_e64 v0, v0, 32 clamp
+; GCN-NOCOMBINE-NEXT: v_min3_u32 v0, v1, v0, 64
+; GCN-NOCOMBINE-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NOCOMBINE-NEXT: s_setpc_b64 s[30:31]
+ %or = or i64 %x, 1
+ %r = call i64 @llvm.ctlz.i64(i64 %or, i1 false)
+ ret i64 %r
+}
+
+define i64 @cttz_or1_i64(i64 %x) {
+; GCN-NOCOMBINE-LABEL: cttz_or1_i64:
+; GCN-NOCOMBINE: ; %bb.0:
+; GCN-NOCOMBINE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NOCOMBINE-NEXT: v_or_b32_e32 v0, 1, v0
+; GCN-NOCOMBINE-NEXT: v_ffbl_b32_e32 v1, v1
+; GCN-NOCOMBINE-NEXT: v_ffbl_b32_e32 v0, v0
+; GCN-NOCOMBINE-NEXT: v_add_u32_e64 v1, v1, 32 clamp
+; GCN-NOCOMBINE-NEXT: v_min3_u32 v0, v0, v1, 64
+; GCN-NOCOMBINE-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NOCOMBINE-NEXT: s_setpc_b64 s[30:31]
+ %or = or i64 %x, 1
+ %r = call i64 @llvm.cttz.i64(i64 %or, i1 false)
+ ret i64 %r
+}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ctlz-cttz-zero-poison.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ctlz-cttz-zero-poison.ll
index c292117f371f3..832bf4cd757df 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ctlz-cttz-zero-poison.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ctlz-cttz-zero-poison.ll
@@ -1,9 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -global-isel %s -o - | FileCheck -check-prefix=GCN %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -global-isel \
-; RUN: --amdgpuprelegalizercombiner-disable-rule=ctlz_to_ctlz_zero_poison,cttz_to_cttz_zero_poison \
-; RUN: --amdgpupostlegalizercombiner-disable-rule=ctlz_to_ctlz_zero_poison,cttz_to_cttz_zero_poison \
-; RUN: %s -o - | FileCheck -check-prefix=GCN-NOCOMBINE %s
; Demonstrate the CTLZ/CTTZ -> *_ZERO_POISON combine on AMDGPU. AMDGPU
; custom-lowers G_CTLZ/G_CTTZ as v_ffbh_u32 / v_ffbl_b32 followed by
@@ -11,8 +7,7 @@
; bitwidth. When the input is provably nonzero, the combine switches to
; G_CTLZ_ZERO_POISON / G_CTTZ_ZERO_POISON and the clamp disappears.
;
-; GCN = combine enabled (this PR) -> no v_min_u32 32 clamp
-; GCN-NOCOMBINE = combine disabled (baseline) -> v_min_u32 32 clamp present
+; GCN = combine enabled -> no v_min_u32 32 clamp
declare i32 @llvm.ctlz.i32(i32, i1)
declare i32 @llvm.cttz.i32(i32, i1)
@@ -26,14 +21,6 @@ define i32 @ctlz_or1(i32 %x) {
; GCN-NEXT: v_or_b32_e32 v0, 1, v0
; GCN-NEXT: v_ffbh_u32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NOCOMBINE-LABEL: ctlz_or1:
-; GCN-NOCOMBINE: ; %bb.0:
-; GCN-NOCOMBINE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NOCOMBINE-NEXT: v_or_b32_e32 v0, 1, v0
-; GCN-NOCOMBINE-NEXT: v_ffbh_u32_e32 v0, v0
-; GCN-NOCOMBINE-NEXT: v_min_u32_e32 v0, 32, v0
-; GCN-NOCOMBINE-NEXT: s_setpc_b64 s[30:31]
%or = or i32 %x, 1
%r = call i32 @llvm.ctlz.i32(i32 %or, i1 false)
ret i32 %r
@@ -46,14 +33,6 @@ define i32 @cttz_or1(i32 %x) {
; GCN-NEXT: v_or_b32_e32 v0, 1, v0
; GCN-NEXT: v_ffbl_b32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NOCOMBINE-LABEL: cttz_or1:
-; GCN-NOCOMBINE: ; %bb.0:
-; GCN-NOCOMBINE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NOCOMBINE-NEXT: v_or_b32_e32 v0, 1, v0
-; GCN-NOCOMBINE-NEXT: v_ffbl_b32_e32 v0, v0
-; GCN-NOCOMBINE-NEXT: v_min_u32_e32 v0, 32, v0
-; GCN-NOCOMBINE-NEXT: s_setpc_b64 s[30:31]
%or = or i32 %x, 1
%r = call i32 @llvm.cttz.i32(i32 %or, i1 false)
ret i32 %r
@@ -66,14 +45,6 @@ define i32 @ctlz_shl1(i32 %n) {
; GCN-NEXT: v_lshlrev_b32_e64 v0, v0, 1
; GCN-NEXT: v_ffbh_u32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NOCOMBINE-LABEL: ctlz_shl1:
-; GCN-NOCOMBINE: ; %bb.0:
-; GCN-NOCOMBINE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NOCOMBINE-NEXT: v_lshlrev_b32_e64 v0, v0, 1
-; GCN-NOCOMBINE-NEXT: v_ffbh_u32_e32 v0, v0
-; GCN-NOCOMBINE-NEXT: v_min_u32_e32 v0, 32, v0
-; GCN-NOCOMBINE-NEXT: s_setpc_b64 s[30:31]
%s = shl i32 1, %n
%r = call i32 @llvm.ctlz.i32(i32 %s, i1 false)
ret i32 %r
@@ -90,17 +61,6 @@ define i64 @ctlz_or1_i64(i64 %x) {
; GCN-NEXT: v_min_u32_e32 v0, v1, v0
; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NOCOMBINE-LABEL: ctlz_or1_i64:
-; GCN-NOCOMBINE: ; %bb.0:
-; GCN-NOCOMBINE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NOCOMBINE-NEXT: v_or_b32_e32 v0, 1, v0
-; GCN-NOCOMBINE-NEXT: v_ffbh_u32_e32 v0, v0
-; GCN-NOCOMBINE-NEXT: v_ffbh_u32_e32 v1, v1
-; GCN-NOCOMBINE-NEXT: v_add_u32_e64 v0, v0, 32 clamp
-; GCN-NOCOMBINE-NEXT: v_min3_u32 v0, v1, v0, 64
-; GCN-NOCOMBINE-NEXT: v_mov_b32_e32 v1, 0
-; GCN-NOCOMBINE-NEXT: s_setpc_b64 s[30:31]
%or = or i64 %x, 1
%r = call i64 @llvm.ctlz.i64(i64 %or, i1 false)
ret i64 %r
@@ -117,18 +77,61 @@ define i64 @cttz_or1_i64(i64 %x) {
; GCN-NEXT: v_min_u32_e32 v0, v0, v1
; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_setpc_b64 s[30:31]
-;
-; GCN-NOCOMBINE-LABEL: cttz_or1_i64:
-; GCN-NOCOMBINE: ; %bb.0:
-; GCN-NOCOMBINE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NOCOMBINE-NEXT: v_or_b32_e32 v0, 1, v0
-; GCN-NOCOMBINE-NEXT: v_ffbl_b32_e32 v1, v1
-; GCN-NOCOMBINE-NEXT: v_ffbl_b32_e32 v0, v0
-; GCN-NOCOMBINE-NEXT: v_add_u32_e64 v1, v1, 32 clamp
-; GCN-NOCOMBINE-NEXT: v_min3_u32 v0, v0, v1, 64
-; GCN-NOCOMBINE-NEXT: v_mov_b32_e32 v1, 0
-; GCN-NOCOMBINE-NEXT: s_setpc_b64 s[30:31]
%or = or i64 %x, 1
%r = call i64 @llvm.cttz.i64(i64 %or, i1 false)
ret i64 %r
}
+
+; Keep the uncombined lowering covered in every build configuration. These
+; cases do not depend on assertion-only symbolic combiner rule names: an
+; unknown input must retain the zero-input clamp.
+
+define i32 @ctlz_unknown_i32(i32 %x) {
+; GCN-LABEL: ctlz_unknown_i32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_ffbh_u32_e32 v0, v0
+; GCN-NEXT: v_min_u32_e32 v0, 32, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %r = call i32 @llvm.ctlz.i32(i32 %x, i1 false)
+ ret i32 %r
+}
+
+define i32 @cttz_unknown_i32(i32 %x) {
+; GCN-LABEL: cttz_unknown_i32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_ffbl_b32_e32 v0, v0
+; GCN-NEXT: v_min_u32_e32 v0, 32, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %r = call i32 @llvm.cttz.i32(i32 %x, i1 false)
+ ret i32 %r
+}
+
+define i64 @ctlz_unknown_i64(i64 %x) {
+; GCN-LABEL: ctlz_unknown_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_ffbh_u32_e32 v0, v0
+; GCN-NEXT: v_ffbh_u32_e32 v1, v1
+; GCN-NEXT: v_add_u32_e64 v0, v0, 32 clamp
+; GCN-NEXT: v_min3_u32 v0, v1, v0, 64
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %r = call i64 @llvm.ctlz.i64(i64 %x, i1 false)
+ ret i64 %r
+}
+
+define i64 @cttz_unknown_i64(i64 %x) {
+; GCN-LABEL: cttz_unknown_i64:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_ffbl_b32_e32 v1, v1
+; GCN-NEXT: v_ffbl_b32_e32 v0, v0
+; GCN-NEXT: v_add_u32_e64 v1, v1, 32 clamp
+; GCN-NEXT: v_min3_u32 v0, v0, v1, 64
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %r = call i64 @llvm.cttz.i64(i64 %x, i1 false)
+ ret i64 %r
+}
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