[llvm] AMDGPU/GlobalISel: Legalize bf16 fpext (PR #210887)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 20 23:35:44 PDT 2026
https://github.com/vangthao95 created https://github.com/llvm/llvm-project/pull/210887
Use custom lowering for fpext from bf16, based on SDAG's ISD::BF16_TO_FP lowering.
>From e1c8464b5d2f154d5268868db6c45ad96f325924 Mon Sep 17 00:00:00 2001
From: Vang Thao <Vang.Thao at amd.com>
Date: Tue, 21 Jul 2026 02:06:16 -0400
Subject: [PATCH] AMDGPU/GlobalISel: Legalize bf16 fpext
Use custom lowering for fpext from bf16, based on SDAG's
ISD::BF16_TO_FP lowering.
---
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 35 ++-
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h | 3 +
llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll | 134 ++++++++++++
llvm/test/CodeGen/AMDGPU/llvm.exp.ll | 140 ++++++++----
llvm/test/CodeGen/AMDGPU/llvm.exp10.ll | 140 ++++++++----
llvm/test/CodeGen/AMDGPU/llvm.exp2.ll | 135 ++++++++----
llvm/test/CodeGen/AMDGPU/llvm.log.ll | 205 ++++++++++++------
llvm/test/CodeGen/AMDGPU/llvm.log10.ll | 205 ++++++++++++------
llvm/test/CodeGen/AMDGPU/llvm.log2.ll | 177 ++++++++++-----
9 files changed, 845 insertions(+), 329 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 87e85bef7c701..3f5d4744faf01 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -1155,8 +1155,12 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
FPTruncActions.legalFor({{S32, S64}, {S16, S32}});
}
FPTruncActions.scalarize(0).lower();
-
- getActionDefinitionsBuilder(G_FPEXT)
+ .getActionDefinitionsBuilder(G_FPEXT)
+ .customIf([](const LegalityQuery &Query) {
+ // Custom lowering for bf16 fpext.
+ unsigned DstSize = Query.Types[0].getSizeInBits();
+ return Query.Types[1].isBFloat16() && (DstSize == 32 || DstSize == 64);
+ })
.legalFor({{S64, S32}, {S32, S16}})
.narrowScalarFor({{S64, S16}}, changeElementSizeTo(0, S32))
.scalarize(0);
@@ -2373,6 +2377,8 @@ bool AMDGPULegalizerInfo::legalizeCustom(
return legalizeFFREXP(MI, MRI, B);
case TargetOpcode::G_FSQRT:
return legalizeFSQRT(MI, MRI, B);
+ case TargetOpcode::G_FPEXT:
+ return legalizeFPExt(MI, MRI, B);
case TargetOpcode::G_UDIV:
case TargetOpcode::G_UREM:
case TargetOpcode::G_UDIVREM:
@@ -6167,6 +6173,31 @@ bool AMDGPULegalizerInfo::legalizeFSQRT(MachineInstr &MI,
return false;
}
+// Expand a bf16 fpext. This is based on the SDAG ISD::BF16_TO_FP lowering.
+bool AMDGPULegalizerInfo::legalizeFPExt(MachineInstr &MI,
+ MachineRegisterInfo &MRI,
+ MachineIRBuilder &B) const {
+ Register Dst = MI.getOperand(0).getReg();
+ Register Src = MI.getOperand(1).getReg();
+ LLT DstTy = MRI.getType(Dst);
+ assert(MRI.getType(Src).isBFloat16() &&
+ "expected a bf16 source for custom fpext lowering");
+
+ const LLT I32 = LLT::integer(32);
+ auto Ext = B.buildAnyExt(I32, B.buildBitcast(I16, Src));
+ auto Shift = B.buildShl(I32, Ext, B.buildConstant(I32, 16));
+
+ if (DstTy.getSizeInBits() == 32) {
+ B.buildBitcast(Dst, Shift);
+ } else {
+ assert(DstTy == LLT::float64() && "unexpected fpext destination type");
+ B.buildFPExt(Dst, B.buildBitcast(LLT::float32(), Shift));
+ }
+
+ MI.eraseFromParent();
+ return true;
+}
+
// Expand llvm.amdgcn.rsq.clamp on targets that don't support the instruction.
// FIXME: Why do we handle this one but not other removed instructions?
//
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
index 89819fe990f5a..697e87d041a03 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
@@ -189,6 +189,9 @@ class AMDGPULegalizerInfo final : public LegalizerInfo {
bool legalizeFSQRT(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
+ bool legalizeFPExt(MachineInstr &MI, MachineRegisterInfo &MRI,
+ MachineIRBuilder &B) const;
+
bool legalizeRsqClampIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll
index 1c5825c3f2633..080838427f2af 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll
@@ -247,3 +247,137 @@ define amdgpu_ps void @fpext_v2f32_to_v2f64_div(<2 x float> %a, ptr addrspace(1)
store <2 x double> %result, ptr addrspace(1) %ptr
ret void
}
+
+define amdgpu_ps float @fpext_bf16_to_f32_uniform(bfloat inreg %a) {
+; GFX11-LABEL: fpext_bf16_to_f32_uniform:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshl_b32 s0, s0, 16
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fpext_bf16_to_f32_uniform:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_lshl_b32 s0, s0, 16
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: ; return to shader part epilog
+ %result = fpext bfloat %a to float
+ ret float %result
+}
+
+define amdgpu_ps float @fpext_bf16_to_f32_div(bfloat %a) {
+; GFX11-LABEL: fpext_bf16_to_f32_div:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fpext_bf16_to_f32_div:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-NEXT: ; return to shader part epilog
+ %result = fpext bfloat %a to float
+ ret float %result
+}
+
+define amdgpu_ps void @fpext_bf16_to_f64_uniform(bfloat inreg %a, ptr addrspace(1) %ptr) {
+; GFX11-LABEL: fpext_bf16_to_f64_uniform:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshl_b32 s0, s0, 16
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_cvt_f64_f32_e32 v[2:3], s0
+; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fpext_bf16_to_f64_uniform:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_lshl_b32 s0, s0, 16
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_cvt_f64_f32_e32 v[2:3], s0
+; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX12-NEXT: s_endpgm
+ %result = fpext bfloat %a to double
+ store double %result, ptr addrspace(1) %ptr
+ ret void
+}
+
+define amdgpu_ps void @fpext_bf16_to_f64_div(bfloat %a, ptr addrspace(1) %ptr) {
+; GFX11-LABEL: fpext_bf16_to_f64_div:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_cvt_f64_f32_e32 v[3:4], v0
+; GFX11-NEXT: global_store_b64 v[1:2], v[3:4], off
+; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fpext_bf16_to_f64_div:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_cvt_f64_f32_e32 v[3:4], v0
+; GFX12-NEXT: global_store_b64 v[1:2], v[3:4], off
+; GFX12-NEXT: s_endpgm
+ %result = fpext bfloat %a to double
+ store double %result, ptr addrspace(1) %ptr
+ ret void
+}
+
+define amdgpu_ps <2 x float> @fpext_v2bf16_to_v2f32_uniform(<2 x bfloat> inreg %a) {
+; GFX11-LABEL: fpext_v2bf16_to_v2f32_uniform:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_lshr_b32 s1, s0, 16
+; GFX11-NEXT: s_lshl_b32 s0, s0, 16
+; GFX11-NEXT: s_lshl_b32 s1, s1, 16
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fpext_v2bf16_to_v2f32_uniform:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_lshr_b32 s1, s0, 16
+; GFX12-NEXT: s_lshl_b32 s0, s0, 16
+; GFX12-NEXT: s_lshl_b32 s1, s1, 16
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX12-NEXT: ; return to shader part epilog
+ %result = fpext <2 x bfloat> %a to <2 x float>
+ ret <2 x float> %result
+}
+
+define amdgpu_ps <2 x float> @fpext_v2bf16_to_v2f32_div(<2 x bfloat> %a) {
+; GFX11-FAKE16-LABEL: fpext_v2bf16_to_v2f32_div:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX11-TRUE16-LABEL: fpext_v2bf16_to_v2f32_div:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX11-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: fpext_v2bf16_to_v2f32_div:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX12-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: fpext_v2bf16_to_v2f32_div:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.h
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX12-TRUE16-NEXT: ; return to shader part epilog
+ %result = fpext <2 x bfloat> %a to <2 x float>
+ ret <2 x float> %result
+}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp.ll
index a5893e8acd786..51de1a3b434bc 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp.ll
@@ -5183,53 +5183,101 @@ define float @v_exp_f32_from_fpext_bf16(bfloat %src) {
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_exp_f32_from_fpext_bf16:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x3fb8aa3b
-; GFX900-NEXT: v_rndne_f32_e32 v2, v1
-; GFX900-NEXT: v_sub_f32_e32 v3, v1, v2
-; GFX900-NEXT: v_fma_f32 v1, v0, s4, -v1
-; GFX900-NEXT: s_mov_b32 s4, 0x32a5705f
-; GFX900-NEXT: v_fma_f32 v1, v0, s4, v1
-; GFX900-NEXT: v_add_f32_e32 v1, v3, v1
-; GFX900-NEXT: v_exp_f32_e32 v1, v1
-; GFX900-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GFX900-NEXT: s_mov_b32 s4, 0xc2ce8ed0
-; GFX900-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x42b17218
-; GFX900-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; GFX900-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_exp_f32_from_fpext_bf16:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b
+; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2
+; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f
+; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1
+; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1
+; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
+; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
+; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; SI-LABEL: v_exp_f32_from_fpext_bf16:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: s_mov_b32 s4, 0x3fb8aa3b
-; SI-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
-; SI-NEXT: v_fma_f32 v2, v0, s4, -v1
-; SI-NEXT: s_mov_b32 s4, 0x32a5705f
-; SI-NEXT: v_rndne_f32_e32 v3, v1
-; SI-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-NEXT: v_sub_f32_e32 v1, v1, v3
-; SI-NEXT: v_add_f32_e32 v1, v1, v2
-; SI-NEXT: v_exp_f32_e32 v1, v1
-; SI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; SI-NEXT: s_mov_b32 s4, 0xc2ce8ed0
-; SI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; SI-NEXT: s_mov_b32 s4, 0x42b17218
-; SI-NEXT: v_ldexp_f32_e32 v1, v1, v2
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; SI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; SI-NEXT: s_setpc_b64 s[30:31]
+; GFX900-GISEL-LABEL: v_exp_f32_from_fpext_bf16:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v2
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-SDAG-LABEL: v_exp_f32_from_fpext_bf16:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b
+; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f
+; SI-SDAG-NEXT: v_rndne_f32_e32 v3, v1
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; SI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v3
+; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
+; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-GISEL-LABEL: v_exp_f32_from_fpext_bf16:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8aa3b
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v2
+; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3
+; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_exp_f32_from_fpext_bf16:
; R600: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp10.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
index 8c7af7cab8c7f..f4819c9ae6910 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
@@ -5245,53 +5245,101 @@ define float @v_exp10_f32_from_fpext_bf16(bfloat %src) {
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_exp10_f32_from_fpext_bf16:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x40549a78
-; GFX900-NEXT: v_rndne_f32_e32 v2, v1
-; GFX900-NEXT: v_sub_f32_e32 v3, v1, v2
-; GFX900-NEXT: v_fma_f32 v1, v0, s4, -v1
-; GFX900-NEXT: s_mov_b32 s4, 0x33979a37
-; GFX900-NEXT: v_fma_f32 v1, v0, s4, v1
-; GFX900-NEXT: v_add_f32_e32 v1, v3, v1
-; GFX900-NEXT: v_exp_f32_e32 v1, v1
-; GFX900-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GFX900-NEXT: s_mov_b32 s4, 0xc23369f4
-; GFX900-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x421a209b
-; GFX900-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; GFX900-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_exp10_f32_from_fpext_bf16:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x40549a78
+; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2
+; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x33979a37
+; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1
+; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1
+; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4
+; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x421a209b
+; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; SI-LABEL: v_exp10_f32_from_fpext_bf16:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: s_mov_b32 s4, 0x40549a78
-; SI-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0
-; SI-NEXT: v_fma_f32 v2, v0, s4, -v1
-; SI-NEXT: s_mov_b32 s4, 0x33979a37
-; SI-NEXT: v_rndne_f32_e32 v3, v1
-; SI-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-NEXT: v_sub_f32_e32 v1, v1, v3
-; SI-NEXT: v_add_f32_e32 v1, v1, v2
-; SI-NEXT: v_exp_f32_e32 v1, v1
-; SI-NEXT: v_cvt_i32_f32_e32 v2, v3
-; SI-NEXT: s_mov_b32 s4, 0xc23369f4
-; SI-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
-; SI-NEXT: s_mov_b32 s4, 0x421a209b
-; SI-NEXT: v_ldexp_f32_e32 v1, v1, v2
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_mov_b32_e32 v2, 0x7f800000
-; SI-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; SI-NEXT: s_setpc_b64 s[30:31]
+; GFX900-GISEL-LABEL: v_exp10_f32_from_fpext_bf16:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v2
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-SDAG-LABEL: v_exp10_f32_from_fpext_bf16:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x40549a78
+; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x33979a37
+; SI-SDAG-NEXT: v_rndne_f32_e32 v3, v1
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; SI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v3
+; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
+; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
+; SI-SDAG-NEXT: s_mov_b32 s4, 0xc23369f4
+; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x421a209b
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-GISEL-LABEL: v_exp10_f32_from_fpext_bf16:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549a78
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x40549a78, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x33979a37
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v2
+; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3
+; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc23369f4
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x421a209b
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
+; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_exp10_f32_from_fpext_bf16:
; R600: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
index f89b2b936e957..27bb8ac56706d 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GCN,SI,GCN-SDAG,SI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GCN,SI,GCN-GISEL,SI-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GCN,SI,GCN-GISEL,SI-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GCN,VI,GCN-SDAG,VI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GCN,VI,GCN-GISEL,VI-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GCN,VI,GCN-GISEL,VI-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-SDAG,GFX900-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-GISEL,GFX900-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-GISEL,GFX900-GISEL %s
; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
@@ -2837,50 +2837,95 @@ define float @v_exp2_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {
}
define float @v_exp2_f32_from_fpext_bf16(bfloat %src) {
-; SI-LABEL: v_exp2_f32_from_fpext_bf16:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: s_mov_b32 s4, 0xc2fc0000
-; SI-NEXT: v_mov_b32_e32 v1, 0x42800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_add_f32_e32 v0, v0, v1
-; SI-NEXT: v_exp_f32_e32 v0, v0
-; SI-NEXT: v_not_b32_e32 v1, 63
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_exp2_f32_from_fpext_bf16:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
+; SI-SDAG-NEXT: v_not_b32_e32 v1, 63
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_exp2_f32_from_fpext_bf16:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; VI-NEXT: s_mov_b32 s4, 0xc2fc0000
-; VI-NEXT: v_mov_b32_e32 v1, 0x42800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_add_f32_e32 v0, v0, v1
-; VI-NEXT: v_exp_f32_e32 v0, v0
-; VI-NEXT: v_not_b32_e32 v1, 63
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; SI-GISEL-LABEL: v_exp2_f32_from_fpext_bf16:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_not_b32_e32 v1, 63
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_exp2_f32_from_fpext_bf16:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX900-NEXT: s_mov_b32 s4, 0xc2fc0000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX900-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-NEXT: v_add_f32_e32 v0, v0, v2
-; GFX900-NEXT: v_exp_f32_e32 v0, v0
-; GFX900-NEXT: v_not_b32_e32 v1, 63
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp2_f32_from_fpext_bf16:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: v_exp_f32_e32 v0, v0
+; VI-SDAG-NEXT: v_not_b32_e32 v1, 63
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp2_f32_from_fpext_bf16:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_not_b32_e32 v1, 63
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-SDAG-LABEL: v_exp2_f32_from_fpext_bf16:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX900-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: v_not_b32_e32 v1, 63
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_exp2_f32_from_fpext_bf16:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_not_b32_e32 v1, 63
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_exp2_f32_from_fpext_bf16:
; R600: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log.ll b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
index 73c5ff59e769b..410f902071fde 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
@@ -6075,28 +6075,52 @@ define float @v_log_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {
}
define float @v_log_f32_from_fpext_bf16(bfloat %src) {
-; SI-LABEL: v_log_f32_from_fpext_bf16:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x3f317217
-; SI-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; SI-NEXT: v_fma_f32 v2, v0, s4, -v1
-; SI-NEXT: s_mov_b32 s4, 0x3377d1cf
-; SI-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_add_f32_e32 v1, v1, v2
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; SI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; SI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log_f32_from_fpext_bf16:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3f317217
+; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-GISEL-LABEL: v_log_f32_from_fpext_bf16:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_log_f32_from_fpext_bf16:
; VI: ; %bb.0:
@@ -6124,51 +6148,100 @@ define float @v_log_f32_from_fpext_bf16(bfloat %src) {
; VI-NEXT: v_sub_f32_e32 v0, v0, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log_f32_from_fpext_bf16:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x3f317217
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, -v1
-; GFX900-NEXT: s_mov_b32 s4, 0x3377d1cf
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
-; GFX900-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX900-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_log_f32_from_fpext_bf16:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3f317217
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log_f32_from_fpext_bf16:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
-; GFX1100-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2
-; GFX1100-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX900-GISEL-LABEL: v_log_f32_from_fpext_bf16:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log_f32_from_fpext_bf16:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log_f32_from_fpext_bf16:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log_f32_from_fpext_bf16:
; R600: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
index b2eaf80900463..e577b5a3205d4 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
@@ -6075,28 +6075,52 @@ define float @v_log10_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {
}
define float @v_log10_f32_from_fpext_bf16(bfloat %src) {
-; SI-LABEL: v_log10_f32_from_fpext_bf16:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x3e9a209a
-; SI-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; SI-NEXT: v_fma_f32 v2, v0, s4, -v1
-; SI-NEXT: s_mov_b32 s4, 0x3284fbcf
-; SI-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_add_f32_e32 v1, v1, v2
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; SI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; SI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log10_f32_from_fpext_bf16:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
+; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-GISEL-LABEL: v_log10_f32_from_fpext_bf16:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_log10_f32_from_fpext_bf16:
; VI: ; %bb.0:
@@ -6124,51 +6148,100 @@ define float @v_log10_f32_from_fpext_bf16(bfloat %src) {
; VI-NEXT: v_sub_f32_e32 v0, v0, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log10_f32_from_fpext_bf16:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x3e9a209a
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, -v1
-; GFX900-NEXT: s_mov_b32 s4, 0x3284fbcf
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
-; GFX900-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX900-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_log10_f32_from_fpext_bf16:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log10_f32_from_fpext_bf16:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
-; GFX1100-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
-; GFX1100-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX900-GISEL-LABEL: v_log10_f32_from_fpext_bf16:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log10_f32_from_fpext_bf16:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log10_f32_from_fpext_bf16:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log10_f32_from_fpext_bf16:
; R600: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log2.ll b/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
index 49e815d8400c5..9253ba8d3a136 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
@@ -1,14 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GFX689,SI,GFX689-SDAG,SI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GFX689,SI,GFX689-GISEL,SI-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GFX689,SI,GFX689-GISEL,SI-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GFX689,VI,GFX689-SDAG,VI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GFX689,VI,GFX689-GISEL,VI-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GFX689,VI,GFX689-GISEL,VI-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-SDAG,GFX900-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-GISEL,GFX900-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-GISEL,GFX900-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-SDAG,GFX1100-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-SDAG,GFX1100-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL,GFX1100-GISEL-FAKE16 %s
; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
@@ -3734,62 +3734,123 @@ define float @v_log2_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {
}
define float @v_log2_f32_from_fpext_bf16(bfloat %src) {
-; SI-LABEL: v_log2_f32_from_fpext_bf16:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log2_f32_from_fpext_bf16:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log2_f32_from_fpext_bf16:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; SI-GISEL-LABEL: v_log2_f32_from_fpext_bf16:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log2_f32_from_fpext_bf16:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log2_f32_from_fpext_bf16:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log2_f32_from_fpext_bf16:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; VI-GISEL-LABEL: v_log2_f32_from_fpext_bf16:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-SDAG-LABEL: v_log2_f32_from_fpext_bf16:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_log2_f32_from_fpext_bf16:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log2_f32_from_fpext_bf16:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log2_f32_from_fpext_bf16:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_f32_from_fpext_bf16:
; R600: ; %bb.0:
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