[llvm] [CodeGen] Add MachineRegisterClassInfo analysis pass (PR #210826)

[Matt Arsenault via llvm-commits]

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@@ -104,6 +104,7 @@
 ; LAXX-NEXT:       Machine Common Subexpression Elimination
 ; LAXX-NEXT:       MachinePostDominator Tree Construction
 ; LAXX-NEXT:       Machine Cycle Info Analysis
+; LAXX-NEXT:       Machine Register Class Info Analysis
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arsenm wrote:

Missing preservation of the analysis somewhere. AMDGPU is probably the only case with legitimate recomputations of this (and later we should take care to incrementally update, after WWM regalloc)

https://github.com/llvm/llvm-project/pull/210826