[llvm] [SelectionDAG] Fold VECREDUCE_AND/OR/XOR of a constant BUILD_VECTOR (PR #210883)
Ankit Kumar Tiwari via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 20 22:58:41 PDT 2026
https://github.com/ankit-cybertron created https://github.com/llvm/llvm-project/pull/210883
Follows up on #207560 and #210126
Adds constant folding for `ISD::VECREDUCE_AND`, `ISD::VECREDUCE_OR`, and `ISD::VECREDUCE_XOR` in SelectionDAG::FoldConstantArithmetic when the input is a BUILD_VECTOR of integer constants. Does not fold undef/poison elements.
Fixes #209108
>From 2b9b0b3692164f9a22bd68ca2a0e249fc3a582fa Mon Sep 17 00:00:00 2001
From: Ankit Kumar Tiwari <ankit.cybertron at gmail.com>
Date: Tue, 21 Jul 2026 06:48:30 +0530
Subject: [PATCH 1/2] Base test for RISCV
---
.../RISCV/rvv/vecreduce-and-constant-fold.ll | 71 +++++++++
.../rvv/vecreduce-orxor-constant-fold.ll | 145 ++++++++++++++++++
2 files changed, 216 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/rvv/vecreduce-and-constant-fold.ll
create mode 100644 llvm/test/CodeGen/RISCV/rvv/vecreduce-orxor-constant-fold.ll
diff --git a/llvm/test/CodeGen/RISCV/rvv/vecreduce-and-constant-fold.ll b/llvm/test/CodeGen/RISCV/rvv/vecreduce-and-constant-fold.ll
new file mode 100644
index 0000000000000..1a914108ef559
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vecreduce-and-constant-fold.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
+
+define i32 @test_and_const() {
+; CHECK-LABEL: test_and_const:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 12401
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: vsext.vf4 v9, v8
+; CHECK-NEXT: vredand.vs v8, v9, v9
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> <i32 -1, i32 15, i32 7, i32 3>)
+ ret i32 %r
+}
+
+define i32 @test_and_const_wide() {
+; CHECK-LABEL: test_and_const_wide:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 10
+; CHECK-NEXT: vid.v v10
+; CHECK-NEXT: li a0, 10
+; CHECK-NEXT: vmadd.vx v10, a0, v8
+; CHECK-NEXT: vredand.vs v8, v10, v10
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> <i32 10, i32 20, i32 30, i32 40, i32 50, i32 60, i32 70, i32 80>)
+ ret i32 %r
+}
+
+define i32 @test_and_nonconst(<4 x i32> %v) {
+; CHECK-LABEL: test_and_nonconst:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vredand.vs v8, v8, v8
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %v)
+ ret i32 %r
+}
+
+define i32 @test_and_poison() {
+; CHECK-LABEL: test_and_poison:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
+; CHECK-NEXT: addi a0, a0, %lo(.LCPI3_0)
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vredand.vs v8, v8, v8
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> <i32 -1, i32 15, i32 poison, i32 3>)
+ ret i32 %r
+}
+
+define i32 @test_and_undef() {
+; CHECK-LABEL: test_and_undef:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
+; CHECK-NEXT: addi a0, a0, %lo(.LCPI4_0)
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vredand.vs v8, v8, v8
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> <i32 -1, i32 15, i32 undef, i32 3>)
+ ret i32 %r
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vecreduce-orxor-constant-fold.ll b/llvm/test/CodeGen/RISCV/rvv/vecreduce-orxor-constant-fold.ll
new file mode 100644
index 0000000000000..da49833924120
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vecreduce-orxor-constant-fold.ll
@@ -0,0 +1,145 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
+
+define i32 @test_or_const() {
+; CHECK-LABEL: test_or_const:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 32848
+; CHECK-NEXT: addi a0, a0, -511
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: vsext.vf4 v9, v8
+; CHECK-NEXT: vredor.vs v8, v9, v9
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> <i32 1, i32 -2, i32 4, i32 8>)
+ ret i32 %r
+}
+
+define i32 @test_or_const_wide() {
+; CHECK-LABEL: test_or_const_wide:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 10
+; CHECK-NEXT: vid.v v10
+; CHECK-NEXT: li a0, 10
+; CHECK-NEXT: vmadd.vx v10, a0, v8
+; CHECK-NEXT: vredor.vs v8, v10, v10
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> <i32 10, i32 20, i32 30, i32 40, i32 50, i32 60, i32 70, i32 80>)
+ ret i32 %r
+}
+
+define i32 @test_or_nonconst(<4 x i32> %v) {
+; CHECK-LABEL: test_or_nonconst:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vredor.vs v8, v8, v8
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %v)
+ ret i32 %r
+}
+
+define i32 @test_or_poison() {
+; CHECK-LABEL: test_or_poison:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
+; CHECK-NEXT: addi a0, a0, %lo(.LCPI3_0)
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vredor.vs v8, v8, v8
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> <i32 1, i32 -2, i32 poison, i32 8>)
+ ret i32 %r
+}
+
+define i32 @test_or_undef() {
+; CHECK-LABEL: test_or_undef:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
+; CHECK-NEXT: addi a0, a0, %lo(.LCPI4_0)
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vredor.vs v8, v8, v8
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> <i32 1, i32 2, i32 undef, i32 -8>)
+ ret i32 %r
+}
+
+define i32 @test_xor_const() {
+; CHECK-LABEL: test_xor_const:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v8, zero
+; CHECK-NEXT: lui a0, 32848
+; CHECK-NEXT: addi a0, a0, -511
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vsext.vf4 v10, v9
+; CHECK-NEXT: vredxor.vs v8, v10, v8
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> <i32 1, i32 -2, i32 4, i32 8>)
+ ret i32 %r
+}
+
+define i32 @test_xor_const_wide() {
+; CHECK-LABEL: test_xor_const_wide:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 10
+; CHECK-NEXT: vid.v v10
+; CHECK-NEXT: li a0, 10
+; CHECK-NEXT: vmadd.vx v10, a0, v8
+; CHECK-NEXT: vmv.s.x v8, zero
+; CHECK-NEXT: vredxor.vs v8, v10, v8
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> <i32 10, i32 20, i32 30, i32 40, i32 50, i32 60, i32 70, i32 80>)
+ ret i32 %r
+}
+
+define i32 @test_xor_nonconst(<4 x i32> %v) {
+; CHECK-LABEL: test_xor_nonconst:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v9, zero
+; CHECK-NEXT: vredxor.vs v8, v8, v9
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %v)
+ ret i32 %r
+}
+
+define i32 @test_xor_poison() {
+; CHECK-LABEL: test_xor_poison:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v8, zero
+; CHECK-NEXT: lui a0, %hi(.LCPI8_0)
+; CHECK-NEXT: addi a0, a0, %lo(.LCPI8_0)
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vredxor.vs v8, v9, v8
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> <i32 1, i32 -2, i32 poison, i32 8>)
+ ret i32 %r
+}
+
+define i32 @test_xor_undef() {
+; CHECK-LABEL: test_xor_undef:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v8, zero
+; CHECK-NEXT: lui a0, %hi(.LCPI9_0)
+; CHECK-NEXT: addi a0, a0, %lo(.LCPI9_0)
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vredxor.vs v8, v9, v8
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %r = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> <i32 1, i32 2, i32 undef, i32 -8>)
+ ret i32 %r
+}
>From 323c221c6fa7b565b880ce705508e74058c05a04 Mon Sep 17 00:00:00 2001
From: Ankit Kumar Tiwari <ankit.cybertron at gmail.com>
Date: Tue, 21 Jul 2026 11:20:26 +0530
Subject: [PATCH 2/2] Add constant folding for VECREDUCE_AND/OR/XOR
---
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 7 ++-
.../RISCV/rvv/vecreduce-and-constant-fold.ll | 22 +--------
.../rvv/vecreduce-orxor-constant-fold.ll | 47 ++-----------------
3 files changed, 12 insertions(+), 64 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 42345c18806d9..862ed8e1dee99 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -7141,6 +7141,9 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
case ISD::VECREDUCE_UMAX:
case ISD::VECREDUCE_UMIN:
case ISD::VECREDUCE_MUL:
+ case ISD::VECREDUCE_AND:
+ case ISD::VECREDUCE_OR:
+ case ISD::VECREDUCE_XOR:
case ISD::STEP_VECTOR: {
SDValue Ops = {N1};
if (SDValue Fold = FoldConstantArithmetic(Opcode, DL, VT, Ops))
@@ -7837,7 +7840,9 @@ SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL,
// Constant fold integer vector reductions with constant BUILD_VECTORs.
if ((Opcode == ISD::VECREDUCE_ADD || Opcode == ISD::VECREDUCE_SMAX ||
Opcode == ISD::VECREDUCE_SMIN || Opcode == ISD::VECREDUCE_UMAX ||
- Opcode == ISD::VECREDUCE_UMIN || Opcode == ISD::VECREDUCE_MUL) &&
+ Opcode == ISD::VECREDUCE_UMIN || Opcode == ISD::VECREDUCE_MUL ||
+ Opcode == ISD::VECREDUCE_OR || Opcode == ISD::VECREDUCE_XOR ||
+ Opcode == ISD::VECREDUCE_AND) &&
ISD::isBuildVectorOfConstantSDNodes(N1.getNode())) {
unsigned EltBits = N1.getValueType().getScalarSizeInBits();
unsigned BaseOpcode = ISD::getVecReduceBaseOpcode(Opcode);
diff --git a/llvm/test/CodeGen/RISCV/rvv/vecreduce-and-constant-fold.ll b/llvm/test/CodeGen/RISCV/rvv/vecreduce-and-constant-fold.ll
index 1a914108ef559..3947b1494e5c6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vecreduce-and-constant-fold.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vecreduce-and-constant-fold.ll
@@ -4,13 +4,7 @@
define i32 @test_and_const() {
; CHECK-LABEL: test_and_const:
; CHECK: # %bb.0:
-; CHECK-NEXT: lui a0, 12401
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmv.s.x v8, a0
-; CHECK-NEXT: vsext.vf4 v9, v8
-; CHECK-NEXT: vredand.vs v8, v9, v9
-; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: li a0, 3
; CHECK-NEXT: ret
%r = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> <i32 -1, i32 15, i32 7, i32 3>)
ret i32 %r
@@ -19,13 +13,7 @@ define i32 @test_and_const() {
define i32 @test_and_const_wide() {
; CHECK-LABEL: test_and_const_wide:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 10
-; CHECK-NEXT: vid.v v10
-; CHECK-NEXT: li a0, 10
-; CHECK-NEXT: vmadd.vx v10, a0, v8
-; CHECK-NEXT: vredand.vs v8, v10, v10
-; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: li a0, 0
; CHECK-NEXT: ret
%r = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> <i32 10, i32 20, i32 30, i32 40, i32 50, i32 60, i32 70, i32 80>)
ret i32 %r
@@ -45,12 +33,6 @@ define i32 @test_and_nonconst(<4 x i32> %v) {
define i32 @test_and_poison() {
; CHECK-LABEL: test_and_poison:
; CHECK: # %bb.0:
-; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
-; CHECK-NEXT: addi a0, a0, %lo(.LCPI3_0)
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: vredand.vs v8, v8, v8
-; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> <i32 -1, i32 15, i32 poison, i32 3>)
ret i32 %r
diff --git a/llvm/test/CodeGen/RISCV/rvv/vecreduce-orxor-constant-fold.ll b/llvm/test/CodeGen/RISCV/rvv/vecreduce-orxor-constant-fold.ll
index da49833924120..b2a5268674edb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vecreduce-orxor-constant-fold.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vecreduce-orxor-constant-fold.ll
@@ -4,13 +4,7 @@
define i32 @test_or_const() {
; CHECK-LABEL: test_or_const:
; CHECK: # %bb.0:
-; CHECK-NEXT: lui a0, 32848
-; CHECK-NEXT: addi a0, a0, -511
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmv.s.x v8, a0
-; CHECK-NEXT: vsext.vf4 v9, v8
-; CHECK-NEXT: vredor.vs v8, v9, v9
-; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: li a0, -1
; CHECK-NEXT: ret
%r = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> <i32 1, i32 -2, i32 4, i32 8>)
ret i32 %r
@@ -19,13 +13,7 @@ define i32 @test_or_const() {
define i32 @test_or_const_wide() {
; CHECK-LABEL: test_or_const_wide:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 10
-; CHECK-NEXT: vid.v v10
-; CHECK-NEXT: li a0, 10
-; CHECK-NEXT: vmadd.vx v10, a0, v8
-; CHECK-NEXT: vredor.vs v8, v10, v10
-; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: li a0, 126
; CHECK-NEXT: ret
%r = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> <i32 10, i32 20, i32 30, i32 40, i32 50, i32 60, i32 70, i32 80>)
ret i32 %r
@@ -45,12 +33,6 @@ define i32 @test_or_nonconst(<4 x i32> %v) {
define i32 @test_or_poison() {
; CHECK-LABEL: test_or_poison:
; CHECK: # %bb.0:
-; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
-; CHECK-NEXT: addi a0, a0, %lo(.LCPI3_0)
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: vredor.vs v8, v8, v8
-; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> <i32 1, i32 -2, i32 poison, i32 8>)
ret i32 %r
@@ -73,14 +55,7 @@ define i32 @test_or_undef() {
define i32 @test_xor_const() {
; CHECK-LABEL: test_xor_const:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmv.s.x v8, zero
-; CHECK-NEXT: lui a0, 32848
-; CHECK-NEXT: addi a0, a0, -511
-; CHECK-NEXT: vmv.s.x v9, a0
-; CHECK-NEXT: vsext.vf4 v10, v9
-; CHECK-NEXT: vredxor.vs v8, v10, v8
-; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: li a0, -13
; CHECK-NEXT: ret
%r = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> <i32 1, i32 -2, i32 4, i32 8>)
ret i32 %r
@@ -89,14 +64,7 @@ define i32 @test_xor_const() {
define i32 @test_xor_const_wide() {
; CHECK-LABEL: test_xor_const_wide:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 10
-; CHECK-NEXT: vid.v v10
-; CHECK-NEXT: li a0, 10
-; CHECK-NEXT: vmadd.vx v10, a0, v8
-; CHECK-NEXT: vmv.s.x v8, zero
-; CHECK-NEXT: vredxor.vs v8, v10, v8
-; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: li a0, 48
; CHECK-NEXT: ret
%r = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> <i32 10, i32 20, i32 30, i32 40, i32 50, i32 60, i32 70, i32 80>)
ret i32 %r
@@ -117,13 +85,6 @@ define i32 @test_xor_nonconst(<4 x i32> %v) {
define i32 @test_xor_poison() {
; CHECK-LABEL: test_xor_poison:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmv.s.x v8, zero
-; CHECK-NEXT: lui a0, %hi(.LCPI8_0)
-; CHECK-NEXT: addi a0, a0, %lo(.LCPI8_0)
-; CHECK-NEXT: vle32.v v9, (a0)
-; CHECK-NEXT: vredxor.vs v8, v9, v8
-; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%r = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> <i32 1, i32 -2, i32 poison, i32 8>)
ret i32 %r
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