[llvm] [NFC][SLP] Precommit tests for ordered fadd-reduction FMA-fusion cost (PR #210835)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 20 15:51:25 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Dmitry Sidorov (MrSidims)
<details>
<summary>Changes</summary>
Baseline coverage for an ordered fadd-of-fmul reduction that is currently vectorized even on FMA-capable targets, breaking the scalar fmul + fadd -> fma fusion. A follow-up teaches the reduction cost model to account for the lost fusion and keep these reductions scalar, at which point these CHECK lines update. Covers X86 avx2, AMDGPU gfx90a and NVPTX sm_80.
It is a pre-requisite for https://github.com/llvm/llvm-project/pull/210399
Assisted-By: Claude Opus 4.8
---
Patch is 46.12 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/210835.diff
3 Files Affected:
- (added) llvm/test/Transforms/SLPVectorizer/AMDGPU/ordered-reduction-fma-fusion.ll (+516)
- (added) llvm/test/Transforms/SLPVectorizer/NVPTX/ordered-reduction-fma-fusion.ll (+46)
- (added) llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss-ordered.ll (+123)
``````````diff
diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/ordered-reduction-fma-fusion.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/ordered-reduction-fma-fusion.ll
new file mode 100644
index 0000000000000..cdd9fcea22d3f
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/ordered-reduction-fma-fusion.ll
@@ -0,0 +1,516 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -passes=slp-vectorizer -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck %s
+
+; gfx90a fuses a scalar fmul feeding a contractable fadd into a single fma, so
+; vectorizing an ordered fadd-of-fmul reduction, a convolution here, would break
+; that fusion. The contract reduction must stay mostly scalar, while the same
+; reduction without contract, where fusion was never possible, is free to vectorize.
+
+define float @conv_contract(ptr addrspace(1) %input, ptr addrspace(4) %mask) {
+; CHECK-LABEL: @conv_contract(
+; CHECK-NEXT: [[IP0:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT:%.*]], i64 0
+; CHECK-NEXT: [[MP0:%.*]] = getelementptr inbounds float, ptr addrspace(4) [[MASK:%.*]], i64 0
+; CHECK-NEXT: [[IP4:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 4
+; CHECK-NEXT: [[IV4:%.*]] = load float, ptr addrspace(1) [[IP4]], align 4
+; CHECK-NEXT: [[IP5:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 8
+; CHECK-NEXT: [[IV5:%.*]] = load float, ptr addrspace(1) [[IP5]], align 4
+; CHECK-NEXT: [[IP6:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 9
+; CHECK-NEXT: [[IP8:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 11
+; CHECK-NEXT: [[IP10:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 16
+; CHECK-NEXT: [[IP12:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 18
+; CHECK-NEXT: [[IP14:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 20
+; CHECK-NEXT: [[IV14:%.*]] = load float, ptr addrspace(1) [[IP14]], align 4
+; CHECK-NEXT: [[IP15:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 24
+; CHECK-NEXT: [[IV15:%.*]] = load float, ptr addrspace(1) [[IP15]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr addrspace(1) [[IP0]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr addrspace(1) [[IP6]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = load <2 x float>, ptr addrspace(1) [[IP8]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = load <2 x float>, ptr addrspace(1) [[IP10]], align 4
+; CHECK-NEXT: [[TMP5:%.*]] = load <2 x float>, ptr addrspace(1) [[IP12]], align 4
+; CHECK-NEXT: [[TMP6:%.*]] = load <16 x float>, ptr addrspace(4) [[MP0]], align 4
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <16 x float> poison, float [[IV4]], i64 4
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <16 x float> [[TMP7]], float [[IV5]], i64 5
+; CHECK-NEXT: [[TMP22:%.*]] = insertelement <16 x float> [[TMP8]], float [[IV14]], i64 14
+; CHECK-NEXT: [[TMP23:%.*]] = insertelement <16 x float> [[TMP22]], float [[IV15]], i64 15
+; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <16 x float> [[TMP23]], <16 x float> [[TMP11]], <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> poison, <16 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP24:%.*]] = shufflevector <16 x float> [[TMP12]], <16 x float> [[TMP13]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 16, i32 17, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+; CHECK-NEXT: [[TMP25:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x float> poison, <16 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <16 x float> [[TMP24]], <16 x float> [[TMP25]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> poison, <16 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP18:%.*]] = shufflevector <16 x float> [[TMP16]], <16 x float> [[TMP17]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 16, i32 17, i32 12, i32 13, i32 14, i32 15>
+; CHECK-NEXT: [[TMP19:%.*]] = shufflevector <2 x float> [[TMP5]], <2 x float> poison, <16 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP20:%.*]] = shufflevector <16 x float> [[TMP18]], <16 x float> [[TMP19]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 14, i32 15>
+; CHECK-NEXT: [[TMP21:%.*]] = fmul contract <16 x float> [[TMP20]], [[TMP6]]
+; CHECK-NEXT: [[ACC14:%.*]] = extractelement <16 x float> [[TMP21]], i64 0
+; CHECK-NEXT: [[PROD15:%.*]] = extractelement <16 x float> [[TMP21]], i64 1
+; CHECK-NEXT: [[ACC15:%.*]] = fadd contract float [[ACC14]], [[PROD15]]
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <16 x float> [[TMP21]], i64 2
+; CHECK-NEXT: [[ACC16:%.*]] = fadd contract float [[ACC15]], [[TMP9]]
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <16 x float> [[TMP21]], i64 3
+; CHECK-NEXT: [[ACC17:%.*]] = fadd contract float [[ACC16]], [[TMP10]]
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <16 x float> [[TMP21]], i64 4
+; CHECK-NEXT: [[ACC18:%.*]] = fadd contract float [[ACC17]], [[TMP14]]
+; CHECK-NEXT: [[TMP15:%.*]] = extractelement <16 x float> [[TMP21]], i64 5
+; CHECK-NEXT: [[ACC19:%.*]] = fadd contract float [[ACC18]], [[TMP15]]
+; CHECK-NEXT: [[TMP28:%.*]] = extractelement <16 x float> [[TMP21]], i64 6
+; CHECK-NEXT: [[ACC6:%.*]] = fadd contract float [[ACC19]], [[TMP28]]
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <16 x float> [[TMP21]], i64 7
+; CHECK-NEXT: [[ACC7:%.*]] = fadd contract float [[ACC6]], [[TMP29]]
+; CHECK-NEXT: [[TMP30:%.*]] = extractelement <16 x float> [[TMP21]], i64 8
+; CHECK-NEXT: [[ACC8:%.*]] = fadd contract float [[ACC7]], [[TMP30]]
+; CHECK-NEXT: [[TMP31:%.*]] = extractelement <16 x float> [[TMP21]], i64 9
+; CHECK-NEXT: [[ACC9:%.*]] = fadd contract float [[ACC8]], [[TMP31]]
+; CHECK-NEXT: [[TMP32:%.*]] = extractelement <16 x float> [[TMP21]], i64 10
+; CHECK-NEXT: [[ACC10:%.*]] = fadd contract float [[ACC9]], [[TMP32]]
+; CHECK-NEXT: [[TMP33:%.*]] = extractelement <16 x float> [[TMP21]], i64 11
+; CHECK-NEXT: [[ACC11:%.*]] = fadd contract float [[ACC10]], [[TMP33]]
+; CHECK-NEXT: [[TMP34:%.*]] = extractelement <16 x float> [[TMP21]], i64 12
+; CHECK-NEXT: [[ACC12:%.*]] = fadd contract float [[ACC11]], [[TMP34]]
+; CHECK-NEXT: [[TMP35:%.*]] = extractelement <16 x float> [[TMP21]], i64 13
+; CHECK-NEXT: [[ACC13:%.*]] = fadd contract float [[ACC12]], [[TMP35]]
+; CHECK-NEXT: [[TMP36:%.*]] = extractelement <16 x float> [[TMP21]], i64 14
+; CHECK-NEXT: [[ACC25:%.*]] = fadd contract float [[ACC13]], [[TMP36]]
+; CHECK-NEXT: [[TMP37:%.*]] = extractelement <16 x float> [[TMP21]], i64 15
+; CHECK-NEXT: [[ACC26:%.*]] = fadd contract float [[ACC25]], [[TMP37]]
+; CHECK-NEXT: [[IP16:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 25
+; CHECK-NEXT: [[MP16:%.*]] = getelementptr inbounds float, ptr addrspace(4) [[MASK]], i64 16
+; CHECK-NEXT: [[IP20:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 32
+; CHECK-NEXT: [[TMP38:%.*]] = load <4 x float>, ptr addrspace(1) [[IP16]], align 4
+; CHECK-NEXT: [[TMP39:%.*]] = load <4 x float>, ptr addrspace(1) [[IP20]], align 4
+; CHECK-NEXT: [[TMP40:%.*]] = load <8 x float>, ptr addrspace(4) [[MP16]], align 4
+; CHECK-NEXT: [[TMP41:%.*]] = shufflevector <4 x float> [[TMP38]], <4 x float> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP42:%.*]] = shufflevector <4 x float> [[TMP39]], <4 x float> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP43:%.*]] = shufflevector <4 x float> [[TMP38]], <4 x float> [[TMP39]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: [[TMP44:%.*]] = fmul contract <8 x float> [[TMP43]], [[TMP40]]
+; CHECK-NEXT: [[TMP45:%.*]] = extractelement <8 x float> [[TMP44]], i64 0
+; CHECK-NEXT: [[ACC27:%.*]] = fadd contract float [[ACC26]], [[TMP45]]
+; CHECK-NEXT: [[TMP46:%.*]] = extractelement <8 x float> [[TMP44]], i64 1
+; CHECK-NEXT: [[ACC28:%.*]] = fadd contract float [[ACC27]], [[TMP46]]
+; CHECK-NEXT: [[TMP47:%.*]] = extractelement <8 x float> [[TMP44]], i64 2
+; CHECK-NEXT: [[ACC29:%.*]] = fadd contract float [[ACC28]], [[TMP47]]
+; CHECK-NEXT: [[TMP48:%.*]] = extractelement <8 x float> [[TMP44]], i64 3
+; CHECK-NEXT: [[ACC30:%.*]] = fadd contract float [[ACC29]], [[TMP48]]
+; CHECK-NEXT: [[TMP49:%.*]] = extractelement <8 x float> [[TMP44]], i64 4
+; CHECK-NEXT: [[ACC20:%.*]] = fadd contract float [[ACC30]], [[TMP49]]
+; CHECK-NEXT: [[TMP50:%.*]] = extractelement <8 x float> [[TMP44]], i64 5
+; CHECK-NEXT: [[ACC21:%.*]] = fadd contract float [[ACC20]], [[TMP50]]
+; CHECK-NEXT: [[TMP51:%.*]] = extractelement <8 x float> [[TMP44]], i64 6
+; CHECK-NEXT: [[ACC22:%.*]] = fadd contract float [[ACC21]], [[TMP51]]
+; CHECK-NEXT: [[TMP52:%.*]] = extractelement <8 x float> [[TMP44]], i64 7
+; CHECK-NEXT: [[ACC23:%.*]] = fadd contract float [[ACC22]], [[TMP52]]
+; CHECK-NEXT: [[IP24:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 36
+; CHECK-NEXT: [[IV20:%.*]] = load float, ptr addrspace(1) [[IP24]], align 4
+; CHECK-NEXT: [[MP20:%.*]] = getelementptr inbounds float, ptr addrspace(4) [[MASK]], i64 24
+; CHECK-NEXT: [[MV20:%.*]] = load float, ptr addrspace(4) [[MP20]], align 4
+; CHECK-NEXT: [[PROD20:%.*]] = fmul contract float [[IV20]], [[MV20]]
+; CHECK-NEXT: [[ACC24:%.*]] = fadd contract float [[ACC23]], [[PROD20]]
+; CHECK-NEXT: ret float [[ACC24]]
+;
+ %ip0 = getelementptr inbounds float, ptr addrspace(1) %input, i64 0
+ %iv0 = load float, ptr addrspace(1) %ip0
+ %mp0 = getelementptr inbounds float, ptr addrspace(4) %mask, i64 0
+ %mv0 = load float, ptr addrspace(4) %mp0
+ %prod0 = fmul contract float %iv0, %mv0
+ %ip1 = getelementptr inbounds float, ptr addrspace(1) %input, i64 1
+ %iv1 = load float, ptr addrspace(1) %ip1
+ %mp1 = getelementptr inbounds float, ptr addrspace(4) %mask, i64 1
+ %mv1 = load float, ptr addrspace(4) %mp1
+ %prod1 = fmul contract float %iv1, %mv1
+ %acc1 = fadd contract float %prod0, %prod1
+ %ip2 = getelementptr inbounds float, ptr addrspace(1) %input, i64 2
+ %iv2 = load float, ptr addrspace(1) %ip2
+ %mp2 = getelementptr inbounds float, ptr addrspace(4) %mask, i64 2
+ %mv2 = load float, ptr addrspace(4) %mp2
+ %prod2 = fmul contract float %iv2, %mv2
+ %acc2 = fadd contract float %acc1, %prod2
+ %ip3 = getelementptr inbounds float, ptr addrspace(1) %input, i64 3
+ %iv3 = load float, ptr addrspace(1) %ip3
+ %mp3 = getelementptr inbounds float, ptr addrspace(4) %mask, i64 3
+ %mv3 = load float, ptr addrspace(4) %mp3
+ %prod3 = fmul contract float %iv3, %mv3
+ %acc3 = fadd contract float %acc2, %prod3
+ %ip4 = getelementptr inbounds float, ptr addrspace(1) %input, i64 4
+ %iv4 = load float, ptr addrspace(1) %ip4
+ %mp4 = getelementptr inbounds float, ptr addrspace(4) %mask, i64 4
+ %mv4 = load float, ptr addrspace(4) %mp4
+ %prod4 = fmul contract float %iv4, %mv4
+ %acc4 = fadd contract float %acc3, %prod4
+ %ip5 = getelementptr inbounds float, ptr addrspace(1) %input, i64 8
+ %iv5 = load float, ptr addrspace(1) %ip5
+ %mp5 = getelementptr inbounds float, ptr addrspace(4) %mask, i64 5
+ %mv5 = load float, ptr addrspace(4) %mp5
+ %prod5 = fmul contract float %iv5, %mv5
+ %acc5 = fadd contract float %acc4, %prod5
+ %ip6 = getelementptr inbounds float, ptr addrspace(1) %input, i64 9
+ %iv6 = load float, ptr addrspace(1) %ip6
+ %mp6 = getelementptr inbounds float, ptr addrspace(4) %mask, i64 6
+ %mv6 = load float, ptr addrspace(4) %mp6
+ %prod6 = fmul contract float %iv6, %mv6
+ %acc6 = fadd contract float %acc5, %prod6
+ %ip7 = getelementptr inbounds float, ptr addrspace(1) %input, i64 10
+ %iv7 = load float, ptr addrspace(1) %ip7
+ %mp7 = getelementptr inbounds float, ptr addrspace(4) %mask, i64 7
+ %mv7 = load float, ptr addrspace(4) %mp7
+ %prod7 = fmul contract float %iv7, %mv7
+ %acc7 = fadd contract float %acc6, %prod7
+ %ip8 = getelementptr inbounds float, ptr addrspace(1) %input, i64 11
+ %iv8 = load float, ptr addrspace(1) %ip8
+ %mp8 = getelementptr inbounds float, ptr addrspace(4) %mask, i64 8
+ %mv8 = load float, ptr addrspace(4) %mp8
+ %prod8 = fmul contract float %iv8, %mv8
+ %acc8 = fadd contract float %acc7, %prod8
+ %ip9 = getelementptr inbounds float, ptr addrspace(1) %input, i64 12
+ %iv9 = load float, ptr addrspace(1) %ip9
+ %mp9 = getelementptr inbounds float, ptr addrspace(4) %mask, i64 9
+ %mv9 = load float, ptr addrspace(4) %mp9
+ %prod9 = fmul contract float %iv9, %mv9
+ %acc9 = fadd contract float %acc8, %prod9
+ %ip10 = getelementptr inbounds float, ptr addrspace(1) %input, i64 16
+ %iv10 = load float, ptr addrspace(1) %ip10
+ %mp10 = getelementptr inbounds float, ptr addrspace(4) %mask, i64 10
+ %mv10 = load float, ptr addrspace(4) %mp10
+ %prod10 = fmul contract float %iv10, %mv10
+ %acc10 = fadd contract float %acc9, %prod10
+ %ip11 = getelementptr inbounds float, ptr addrspace(1) %input, i64 17
+ %iv11 = load float, ptr addrspace(1) %ip11
+ %mp11 = getelementptr inbounds float, ptr addrspace(4) %mask, i64 11
+ %mv11 = load float, ptr addrspace(4) %mp11
+ %prod11 = fmul contract float %iv11, %mv11
+ %acc11 = fadd contract float %acc10, %prod11
+ %ip12 = getelementptr inbounds float, ptr addrspace(1) %input, i64 18
+ %iv12 = load float, ptr addrspace(1) %ip12
+ %mp12 = getelementptr inbounds float, ptr addrspace(4) %mask, i64 12
+ %mv12 = load float, ptr addrspace(4) %mp12
+ %prod12 = fmul contract float %iv12, %mv12
+ %acc12 = fadd contract float %acc11, %prod12
+ %ip13 = getelementptr inbounds float, ptr addrspace(1) %input, i64 19
+ %iv13 = load float, ptr addrspace(1) %ip13
+ %mp13 = getelementptr inbounds float, ptr addrspace(4) %mask, i64 13
+ %mv13 = load float, ptr addrspace(4) %mp13
+ %prod13 = fmul contract float %iv13, %mv13
+ %acc13 = fadd contract float %acc12, %prod13
+ %ip14 = getelementptr inbounds float, ptr addrspace(1) %input, i64 20
+ %iv14 = load float, ptr addrspace(1) %ip14
+ %mp14 = getelementptr inbounds float, ptr addrspace(4) %mask, i64 14
+ %mv14 = load float, ptr addrspace(4) %mp14
+ %prod14 = fmul contract float %iv14, %mv14
+ %acc14 = fadd contract float %acc13, %prod14
+ %ip15 = getelementptr inbounds float, ptr addrspace(1) %input, i64 24
+ %iv15 = load float, ptr addrspace(1) %ip15
+ %mp15 = getelementptr inbounds float, ptr addrspace(4) %mask, i64 15
+ %mv15 = load float, ptr addrspace(4) %mp15
+ %prod15 = fmul contract float %iv15, %mv15
+ %acc15 = fadd contract float %acc14, %prod15
+ %ip16 = getelementptr inbounds float, ptr addrspace(1) %input, i64 25
+ %iv16 = load float, ptr addrspace(1) %ip16
+ %mp16 = getelementptr inbounds float, ptr addrspace(4) %mask, i64 16
+ %mv16 = load float, ptr addrspace(4) %mp16
+ %prod16 = fmul contract float %iv16, %mv16
+ %acc16 = fadd contract float %acc15, %prod16
+ %ip17 = getelementptr inbounds float, ptr addrspace(1) %input, i64 26
+ %iv17 = load float, ptr addrspace(1) %ip17
+ %mp17 = getelementptr inbounds float, ptr addrspace(4) %mask, i64 17
+ %mv17 = load float, ptr addrspace(4) %mp17
+ %prod17 = fmul contract float %iv17, %mv17
+ %acc17 = fadd contract float %acc16, %prod17
+ %ip18 = getelementptr inbounds float, ptr addrspace(1) %input, i64 27
+ %iv18 = load float, ptr addrspace(1) %ip18
+ %mp18 = getelementptr inbounds float, ptr addrspace(4) %mask, i64 18
+ %mv18 = load float, ptr addrspace(4) %mp18
+ %prod18 = fmul contract float %iv18, %mv18
+ %acc18 = fadd contract float %acc17, %prod18
+ %ip19 = getelementptr inbounds float, ptr addrspace(1) %input, i64 28
+ %iv19 = load float, ptr addrspace(1) %ip19
+ %mp19 = getelementptr inbounds float, ptr addrspace(4) %mask, i64 19
+ %mv19 = load float, ptr addrspace(4) %mp19
+ %prod19 = fmul contract float %iv19, %mv19
+ %acc19 = fadd contract float %acc18, %prod19
+ %ip20 = getelementptr inbounds float, ptr addrspace(1) %input, i64 32
+ %iv20 = load float, ptr addrspace(1) %ip20
+ %mp20 = getelementptr inbounds float, ptr addrspace(4) %mask, i64 20
+ %mv20 = load float, ptr addrspace(4) %mp20
+ %prod20 = fmul contract float %iv20, %mv20
+ %acc20 = fadd contract float %acc19, %prod20
+ %ip21 = getelementptr inbounds float, ptr addrspace(1) %input, i64 33
+ %iv21 = load float, ptr addrspace(1) %ip21
+ %mp21 = getelementptr inbounds float, ptr addrspace(4) %mask, i64 21
+ %mv21 = load float, ptr addrspace(4) %mp21
+ %prod21 = fmul contract float %iv21, %mv21
+ %acc21 = fadd contract float %acc20, %prod21
+ %ip22 = getelementptr inbounds float, ptr addrspace(1) %input, i64 34
+ %iv22 = load float, ptr addrspace(1) %ip22
+ %mp22 = getelementptr inbounds float, ptr addrspace(4) %mask, i64 22
+ %mv22 = load float, ptr addrspace(4) %mp22
+ %prod22 = fmul contract float %iv22, %mv22
+ %acc22 = fadd contract float %acc21, %prod22
+ %ip23 = getelementptr inbounds float, ptr addrspace(1) %input, i64 35
+ %iv23 = load float, ptr addrspace(1) %ip23
+ %mp23 = getelementptr inbounds float, ptr addrspace(4) %mask, i64 23
+ %mv23 = load float, ptr addrspace(4) %mp23
+ %prod23 = fmul contract float %iv23, %mv23
+ %acc23 = fadd contract float %acc22, %prod23
+ %ip24 = getelementptr inbounds float, ptr addrspace(1) %input, i64 36
+ %iv24 = load float, ptr addrspace(1) %ip24
+ %mp24 = getelementptr inbounds float, ptr addrspace(4) %mask, i64 24
+ %mv24 = load float, ptr addrspace(4) %mp24
+ %prod24 = fmul contract float %iv24, %mv24
+ %acc24 = fadd contract float %acc23, %prod24
+ ret float %acc24
+}
+
+define float @conv_no_contract(ptr addrspace(1) %input, ptr addrspace(4) %mask) {
+; CHECK-LABEL: @conv_no_contract(
+; CHECK-NEXT: [[IP0:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT:%.*]], i64 0
+; CHECK-NEXT: [[MP0:%.*]] = getelementptr inbounds float, ptr addrspace(4) [[MASK:%.*]], i64 0
+; CHECK-NEXT: [[IP4:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 4
+; CHECK-NEXT: [[IV4:%.*]] = load float, ptr addrspace(1) [[IP4]], align 4
+; CHECK-NEXT: [[IP5:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 8
+; CHECK-NEXT: [[IV5:%.*]] = load float, ptr addrspace(1) [[IP5]], align 4
+; CHECK-NEXT: [[IP6:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 9
+; CHECK-NEXT: [[IP8:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 11
+; CHECK-NEXT: [[IP10:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 16
+; CHECK-NEXT: [[IP12:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 18
+; CHECK-NEXT: [[IP14:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 20
+; CHECK-NEXT: [[IV14:%.*]] = load float, ptr addrspace(1) [[IP14]], align 4
+; CHECK-NEXT: [[IP15:%.*]] = getelementptr inbounds float, ptr addr...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/210835
More information about the llvm-commits
mailing list