[llvm] [RegAlloc] Consider rematerialization over CSR use (PR #206756)
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Mon Jul 20 08:00:59 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: Lukas Sommer (sommerlukas)
<details>
<summary>Changes</summary>
The first use of a callee-saved register incurs additional cost for
saving and restoring.
The existing logic already considers some alternatives such as region
split or spilling and chooses them if they are cheaper than CSR first
time use cost.
However, rematerialization isn't considered as alternative at the
moment. This patch adds consideration of rematerialization in a specific
scope and chooses rematerialization over CSR if it's cheaper.
---
Patch is 491.34 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/206756.diff
60 Files Affected:
- (modified) llvm/lib/CodeGen/RegAllocGreedy.cpp (+102-8)
- (modified) llvm/lib/CodeGen/RegAllocGreedy.h (+3)
- (modified) llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc_immo.ll (+4-4)
- (modified) llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll (+30-30)
- (modified) llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a_fp.ll (+30-30)
- (modified) llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lsfe.ll (+30-30)
- (modified) llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8a_fp.ll (+30-30)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/addsub.ll (+4-5)
- (modified) llvm/test/CodeGen/AArch64/clear-dead-implicit-def-impdef.ll (+14-14)
- (modified) llvm/test/CodeGen/AArch64/combine-comparisons-by-cse.ll (+14-18)
- (modified) llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll (+298-325)
- (modified) llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll (+76-76)
- (modified) llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll (+4-4)
- (modified) llvm/test/CodeGen/AArch64/late-taildup-computed-goto.ll (+19-19)
- (modified) llvm/test/CodeGen/AArch64/llvm.frexp.ll (+160-172)
- (modified) llvm/test/CodeGen/AArch64/llvm.modf.ll (+52-61)
- (modified) llvm/test/CodeGen/AArch64/llvm.sincos.ll (+22-30)
- (modified) llvm/test/CodeGen/AArch64/llvm.sincospi.ll (+28-36)
- (modified) llvm/test/CodeGen/AArch64/regalloc-last-chance-recolor-with-split.mir (+23-23)
- (modified) llvm/test/CodeGen/AArch64/shrink-wrap-byval-inalloca-preallocated.ll (+24-36)
- (modified) llvm/test/CodeGen/AArch64/sme-peephole-opts.ll (+6-5)
- (modified) llvm/test/CodeGen/AArch64/sme-za-control-flow.ll (+37-40)
- (modified) llvm/test/CodeGen/AArch64/sme-za-exceptions.ll (+18-19)
- (modified) llvm/test/CodeGen/AArch64/sme-zt0-state.ll (+50-46)
- (modified) llvm/test/CodeGen/AArch64/stack-protector-darwin-got.ll (+7-11)
- (modified) llvm/test/CodeGen/AArch64/sve-fixed-ld2-alloca.ll (+6-8)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll (+13-15)
- (modified) llvm/test/CodeGen/AArch64/swifterror.ll (+34-44)
- (modified) llvm/test/CodeGen/AArch64/swifttail-call.ll (+2-2)
- (modified) llvm/test/CodeGen/AArch64/tailcc-tail-call.ll (+2-2)
- (modified) llvm/test/CodeGen/AArch64/wineh-try-catch.ll (+15-19)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll (+8-10)
- (modified) llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll (+491-642)
- (modified) llvm/test/CodeGen/AMDGPU/i128-add-carry-chain.ll (+23-24)
- (added) llvm/test/CodeGen/AMDGPU/remat-csr.mir (+76)
- (modified) llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll (+11-15)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll (+103-107)
- (modified) llvm/test/CodeGen/RISCV/atomic-signext.ll (+20-28)
- (modified) llvm/test/CodeGen/RISCV/double-convert.ll (+38-43)
- (modified) llvm/test/CodeGen/RISCV/float-convert.ll (+64-75)
- (modified) llvm/test/CodeGen/RISCV/forced-atomics.ll (+30-42)
- (modified) llvm/test/CodeGen/RISCV/half-convert.ll (+64-75)
- (modified) llvm/test/CodeGen/RISCV/machine-outliner-and-machine-copy-propagation.ll (+7-7)
- (modified) llvm/test/CodeGen/RISCV/pr135206.ll (+6-6)
- (modified) llvm/test/CodeGen/RISCV/reduce-unnecessary-extension.ll (+2-4)
- (modified) llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll (+30-36)
- (modified) llvm/test/CodeGen/RISCV/remat.ll (+56-68)
- (modified) llvm/test/CodeGen/RISCV/rv64-double-convert.ll (+18-19)
- (modified) llvm/test/CodeGen/RISCV/rv64-float-convert.ll (+18-19)
- (modified) llvm/test/CodeGen/RISCV/rv64-half-convert.ll (+18-19)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll (+4-7)
- (modified) llvm/test/CodeGen/RISCV/rvv/localvar.ll (+24-32)
- (modified) llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll (+51-45)
- (modified) llvm/test/CodeGen/RISCV/rvv/stores-of-loads-merging.ll (+15-18)
- (modified) llvm/test/CodeGen/RISCV/sextw-removal.ll (+4-8)
- (modified) llvm/test/CodeGen/RISCV/shrinkwrap.ll (+72-80)
- (modified) llvm/test/CodeGen/RISCV/stack-guard-global.ll (+6-7)
- (modified) llvm/test/CodeGen/RISCV/stack-protector-target.ll (+14-16)
``````````diff
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 6b8a9b8190f9a..de02558de5233 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2372,6 +2372,87 @@ BlockFrequency RAGreedy::calcSpillCost(const LiveInterval &LI) {
return BlockFrequency(SpillCost);
}
+bool RAGreedy::shouldAvoidCSRForRemat(const LiveInterval &VirtReg,
+ AllocationOrder &Order) const {
+ if (!VirtReg.isSpillable())
+ return false;
+
+ // This logic is intentionally narrow: handle a single concrete value
+ // whose def can be cheaply rematerialized at every use.
+ const VNInfo *OnlyVNI = nullptr;
+ for (const VNInfo *VNI : VirtReg.vnis()) {
+ if (!VNI || VNI->isUnused())
+ continue;
+ if (VNI->isPHIDef())
+ return false;
+ if (OnlyVNI)
+ return false;
+ OnlyVNI = VNI;
+ }
+ if (!OnlyVNI)
+ return false;
+
+ MachineInstr *DefMI = LIS->getInstructionFromIndex(OnlyVNI->def);
+ if (!DefMI || DefMI->isImplicitDef() || !TII->isReMaterializable(*DefMI) ||
+ !TII->isAsCheapAsAMove(*DefMI))
+ return false;
+
+ // This logic aims to address a specific problem: The first use of CSR for
+ // cheap-to-rematerialize live ranges because they cross calls, not because
+ // pressure requires it. With this check and the check for an available for a
+ // register that is not a first-use CSR below, we can scope this.
+ if (!Matrix->checkRegMaskInterference(VirtReg))
+ return false;
+
+ SmallPtrSet<MachineInstr *, 8> VisitedUses;
+ unsigned NumUses = 0;
+ for (MachineOperand &MO : MRI->use_nodbg_operands(VirtReg.reg())) {
+ if (MO.isUndef())
+ continue;
+
+ MachineInstr *UseMI = MO.getParent();
+ if (!VisitedUses.insert(UseMI).second)
+ continue;
+
+ SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI).getRegSlot(true);
+ if (!VirtRegAuxInfo::allUsesAvailableAt(DefMI, UseIdx, *LIS, *MRI, *TII))
+ return false;
+
+ // Check if any register that is not a first-use CSR is available as
+ // destination for the rematerialization.
+ SlotIndex PrevIdx = UseIdx.getPrevSlot();
+ bool HasNoFirstCSRReg = false;
+ for (MCRegister RematPhysReg : Order) {
+ if (EvictAdvisor->isUnusedCalleeSavedReg(RematPhysReg))
+ continue;
+ if (!Matrix->checkInterference(PrevIdx, UseIdx, RematPhysReg)) {
+ HasNoFirstCSRReg = true;
+ break;
+ }
+ }
+ if (!HasNoFirstCSRReg)
+ return false;
+
+ ++NumUses;
+ }
+
+ if (!NumUses)
+ return false;
+
+ // Ideally, this would be handled with the CSR cost model, but the scales
+ // differ. The rationale for allowing a fan-out of 3 is simple: Saving and
+ // restoring the CSR will require at least two moves, so we can allow three
+ // uses, as the first is free and the two materializations will at most have
+ // the same cost as CSR save/restore.
+ // FIXME: Properly integrate into CSR cost model.
+ if (NumUses > 3)
+ return false;
+
+ LLVM_DEBUG(dbgs() << " rejecting CSR: cheap remat available for " << NumUses
+ << " use(s) with no-first-CSR registers\n");
+ return true;
+}
+
/// Using a CSR for the first time has a cost because it causes push|pop
/// to be added to prologue|epilogue. Splitting a cold section of the live
/// range can have lower cost than using the CSR for the first time;
@@ -2381,19 +2462,23 @@ BlockFrequency RAGreedy::calcSpillCost(const LiveInterval &LI) {
MCRegister RAGreedy::tryAssignCSRFirstTime(
const LiveInterval &VirtReg, AllocationOrder &Order, MCRegister PhysReg,
uint8_t &CostPerUseLimit, SmallVectorImpl<Register> &NewVRegs) {
- if (ExtraInfo->getStage(VirtReg) == RS_Spill && VirtReg.isSpillable()) {
- // We choose spill over using the CSR for the first time if the spill cost
- // is lower than CSRCost.
+ LiveRangeStage Stage = ExtraInfo->getStage(VirtReg);
+
+ if (Stage == RS_Spill && VirtReg.isSpillable()) {
+ // We choose spill or rematerialize over using the CSR for the first time if
+ // the spill cost is lower than CSRCost.
SA->analyze(&VirtReg);
- if (calcSpillCost(VirtReg) >= CSRCost)
+ if (calcSpillCost(VirtReg) >= CSRCost &&
+ !shouldAvoidCSRForRemat(VirtReg, Order)) {
return PhysReg;
+ }
- // We are going to spill, set CostPerUseLimit to 1 to make sure that
- // we will not use a callee-saved register in tryEvict.
+ // We are going to spill or rematerialize, set CostPerUseLimit to 1 to make
+ // sure that we will not use a callee-saved register in tryEvict.
CostPerUseLimit = 1;
return MCRegister();
}
- if (ExtraInfo->getStage(VirtReg) < RS_Split) {
+ if (Stage < RS_Split) {
// We choose pre-splitting over using the CSR for the first time if
// the cost of splitting is lower than CSRCost.
SA->analyze(&VirtReg);
@@ -2401,14 +2486,23 @@ MCRegister RAGreedy::tryAssignCSRFirstTime(
BlockFrequency BestCost = CSRCost; // Don't modify CSRCost.
unsigned BestCand = calculateRegionSplitCost(VirtReg, Order, BestCost,
NumCands, true /*IgnoreCSR*/);
- if (BestCand == NoCand)
+ if (BestCand == NoCand) {
+ if (shouldAvoidCSRForRemat(VirtReg, Order)) {
+ CostPerUseLimit = 1;
+ return MCRegister();
+ }
// Use the CSR if we can't find a region split below CSRCost.
return PhysReg;
+ }
// Perform the actual pre-splitting.
doRegionSplit(VirtReg, BestCand, false/*HasCompact*/, NewVRegs);
return MCRegister();
}
+ if (shouldAvoidCSRForRemat(VirtReg, Order)) {
+ CostPerUseLimit = 1;
+ return MCRegister();
+ }
return PhysReg;
}
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.h b/llvm/lib/CodeGen/RegAllocGreedy.h
index 465be0d76809e..8ee452e7e10a2 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.h
+++ b/llvm/lib/CodeGen/RegAllocGreedy.h
@@ -360,6 +360,9 @@ class LLVM_LIBRARY_VISIBILITY RAGreedy : public RegAllocBase,
AllocationOrder &Order, MCRegister PhysReg,
uint8_t &CostPerUseLimit,
SmallVectorImpl<Register> &NewVRegs);
+ /// Check if rematerialization is cheaper than using a CSR for the first time.
+ bool shouldAvoidCSRForRemat(const LiveInterval &VirtReg,
+ AllocationOrder &Order) const;
BlockFrequency calcSpillCost(const LiveInterval &LI);
void initializeCSRCost();
MCRegister tryBlockSplit(const LiveInterval &, AllocationOrder &,
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc_immo.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc_immo.ll
index f29ae86b73842..001160866dfaa 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc_immo.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc_immo.ll
@@ -918,7 +918,7 @@ define i8 @load_atomic_i8_from_gep() {
;
; SDAG-AVOIDLDAPUR-LABEL: load_atomic_i8_from_gep:
; SDAG-AVOIDLDAPUR: bl init
-; SDAG-AVOIDLDAPUR: orr x8, x19, #0x1
+; SDAG-AVOIDLDAPUR: orr x8, x8, #0x1
; SDAG-AVOIDLDAPUR: ldaprb w0, [x8]
;
; SDAG-NOAVOIDLDAPUR-LABEL: load_atomic_i8_from_gep:
@@ -938,7 +938,7 @@ define i16 @load_atomic_i16_from_gep() {
;
; SDAG-AVOIDLDAPUR-LABEL: load_atomic_i16_from_gep:
; SDAG-AVOIDLDAPUR: bl init
-; SDAG-AVOIDLDAPUR: orr x8, x19, #0x2
+; SDAG-AVOIDLDAPUR: orr x8, x8, #0x2
; SDAG-AVOIDLDAPUR: ldaprh w0, [x8]
;
; SDAG-NOAVOIDLDAPUR-LABEL: load_atomic_i16_from_gep:
@@ -958,7 +958,7 @@ define i32 @load_atomic_i32_from_gep() {
;
; SDAG-AVOIDLDAPUR-LABEL: load_atomic_i32_from_gep:
; SDAG-AVOIDLDAPUR: bl init
-; SDAG-AVOIDLDAPUR: add x8, x19, #4
+; SDAG-AVOIDLDAPUR: add x8, x8, #4
; SDAG-AVOIDLDAPUR: ldapr w0, [x8]
;
; SDAG-NOAVOIDLDAPUR-LABEL: load_atomic_i32_from_gep:
@@ -978,7 +978,7 @@ define i64 @load_atomic_i64_from_gep() {
;
; SDAG-AVOIDLDAPUR-LABEL: load_atomic_i64_from_gep:
; SDAG-AVOIDLDAPUR: bl init
-; SDAG-AVOIDLDAPUR: add x8, x19, #8
+; SDAG-AVOIDLDAPUR: add x8, x8, #8
; SDAG-AVOIDLDAPUR: ldapr x0, [x8]
;
; SDAG-NOAVOIDLDAPUR-LABEL: load_atomic_i64_from_gep:
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
index 6a0b689b16888..372151989adc5 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
@@ -247,7 +247,7 @@ define dso_local bfloat @atomicrmw_fadd_bfloat_unaligned_monotonic(ptr %ptr, bfl
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fadd_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fadd ptr %ptr, bfloat %value monotonic, align 1
@@ -264,7 +264,7 @@ define dso_local bfloat @atomicrmw_fadd_bfloat_unaligned_acquire(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fadd_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fadd ptr %ptr, bfloat %value acquire, align 1
@@ -281,7 +281,7 @@ define dso_local bfloat @atomicrmw_fadd_bfloat_unaligned_release(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fadd_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fadd ptr %ptr, bfloat %value release, align 1
@@ -298,7 +298,7 @@ define dso_local bfloat @atomicrmw_fadd_bfloat_unaligned_acq_rel(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fadd_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fadd ptr %ptr, bfloat %value acq_rel, align 1
@@ -315,7 +315,7 @@ define dso_local bfloat @atomicrmw_fadd_bfloat_unaligned_seq_cst(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fadd_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fadd ptr %ptr, bfloat %value seq_cst, align 1
@@ -752,7 +752,7 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_unaligned_monotonic(ptr %ptr, bfl
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fsub_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fsub ptr %ptr, bfloat %value monotonic, align 1
@@ -769,7 +769,7 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_unaligned_acquire(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fsub_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fsub ptr %ptr, bfloat %value acquire, align 1
@@ -786,7 +786,7 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_unaligned_release(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fsub_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fsub ptr %ptr, bfloat %value release, align 1
@@ -803,7 +803,7 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_unaligned_acq_rel(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fsub_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fsub ptr %ptr, bfloat %value acq_rel, align 1
@@ -820,7 +820,7 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_unaligned_seq_cst(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fsub_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fsub ptr %ptr, bfloat %value seq_cst, align 1
@@ -1138,7 +1138,7 @@ define dso_local bfloat @atomicrmw_fmax_bfloat_unaligned_monotonic(ptr %ptr, bfl
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmax_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmax ptr %ptr, bfloat %value monotonic, align 1
@@ -1155,7 +1155,7 @@ define dso_local bfloat @atomicrmw_fmax_bfloat_unaligned_acquire(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmax_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmax ptr %ptr, bfloat %value acquire, align 1
@@ -1172,7 +1172,7 @@ define dso_local bfloat @atomicrmw_fmax_bfloat_unaligned_release(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmax_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmax ptr %ptr, bfloat %value release, align 1
@@ -1189,7 +1189,7 @@ define dso_local bfloat @atomicrmw_fmax_bfloat_unaligned_acq_rel(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmax_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmax ptr %ptr, bfloat %value acq_rel, align 1
@@ -1206,7 +1206,7 @@ define dso_local bfloat @atomicrmw_fmax_bfloat_unaligned_seq_cst(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmax_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmax ptr %ptr, bfloat %value seq_cst, align 1
@@ -1524,7 +1524,7 @@ define dso_local bfloat @atomicrmw_fmin_bfloat_unaligned_monotonic(ptr %ptr, bfl
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmin_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmin ptr %ptr, bfloat %value monotonic, align 1
@@ -1541,7 +1541,7 @@ define dso_local bfloat @atomicrmw_fmin_bfloat_unaligned_acquire(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmin_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmin ptr %ptr, bfloat %value acquire, align 1
@@ -1558,7 +1558,7 @@ define dso_local bfloat @atomicrmw_fmin_bfloat_unaligned_release(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmin_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmin ptr %ptr, bfloat %value release, align 1
@@ -1575,7 +1575,7 @@ define dso_local bfloat @atomicrmw_fmin_bfloat_unaligned_acq_rel(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmin_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmin ptr %ptr, bfloat %value acq_rel, align 1
@@ -1592,7 +1592,7 @@ define dso_local bfloat @atomicrmw_fmin_bfloat_unaligned_seq_cst(ptr %ptr, bfloa
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmin_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmin ptr %ptr, bfloat %value seq_cst, align 1
@@ -1910,7 +1910,7 @@ define dso_local bfloat @atomicrmw_fmaximum_bfloat_unaligned_monotonic(ptr %ptr,
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmaximum_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmaximum ptr %ptr, bfloat %value monotonic, align 1
@@ -1927,7 +1927,7 @@ define dso_local bfloat @atomicrmw_fmaximum_bfloat_unaligned_acquire(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmaximum_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmaximum ptr %ptr, bfloat %value acquire, align 1
@@ -1944,7 +1944,7 @@ define dso_local bfloat @atomicrmw_fmaximum_bfloat_unaligned_release(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmaximum_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmaximum ptr %ptr, bfloat %value release, align 1
@@ -1961,7 +1961,7 @@ define dso_local bfloat @atomicrmw_fmaximum_bfloat_unaligned_acq_rel(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmaximum_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmaximum ptr %ptr, bfloat %value acq_rel, align 1
@@ -1978,7 +1978,7 @@ define dso_local bfloat @atomicrmw_fmaximum_bfloat_unaligned_seq_cst(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fmaximum_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fmaximum ptr %ptr, bfloat %value seq_cst, align 1
@@ -2296,7 +2296,7 @@ define dso_local bfloat @atomicrmw_fminimum_bfloat_unaligned_monotonic(ptr %ptr,
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fminimum_bfloat_unaligned_monotonic:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fminimum ptr %ptr, bfloat %value monotonic, align 1
@@ -2313,7 +2313,7 @@ define dso_local bfloat @atomicrmw_fminimum_bfloat_unaligned_acquire(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fminimum_bfloat_unaligned_acquire:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fminimum ptr %ptr, bfloat %value acquire, align 1
@@ -2330,7 +2330,7 @@ define dso_local bfloat @atomicrmw_fminimum_bfloat_unaligned_release(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fminimum_bfloat_unaligned_release:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fminimum ptr %ptr, bfloat %value release, align 1
@@ -2347,7 +2347,7 @@ define dso_local bfloat @atomicrmw_fminimum_bfloat_unaligned_acq_rel(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fminimum_bfloat_unaligned_acq_rel:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fminimum ptr %ptr, bfloat %value acq_rel, align 1
@@ -2364,7 +2364,7 @@ define dso_local bfloat @atomicrmw_fminimum_bfloat_unaligned_seq_cst(ptr %ptr, b
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_fminimum_bfloat_unaligned_seq_cst:
-; -O1: add w8, w8, w20
+; -O1: add w8, w8, w10
; -O1: add w8, w9, w8
; -O1: bl __atomic_compare_exchange
%r = atomicrmw fminimum ptr %ptr, bfloat %value seq_cst, align 1
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a_fp.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a_fp.ll
index d71231059c3b3..32e382af71a46 100644
--- a/llvm/test/CodeGen/AArch64/Atomic...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/206756
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