[llvm] [SelectionDAG] Fold VECREDUCE_MUL of a constant BUILD_VECTOR (PR #210126)

[Simon Pilgrim via llvm-commits]

https://github.com/RKSimon requested changes to this pull request.

OK, so it looks like we need to test this on a different target to RISCV which does expand mul reductions - ARM/AArch64 maybe?

https://github.com/llvm/llvm-project/pull/210126