[llvm] [NFC][AMDGPU] Use SIInstrFlags predicates in SIMemoryLegalizer and AMDGPUBaseInfo. (PR #209821)
Valery Pykhtin via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 20 01:53:24 PDT 2026
https://github.com/vpykhtin updated https://github.com/llvm/llvm-project/pull/209821
>From 431dfe43fd7ea706e5258a976a09b2905b5cff44 Mon Sep 17 00:00:00 2001
From: Valery Pykhtin <valery.pykhtin at amd.com>
Date: Thu, 11 Jun 2026 12:14:34 +0000
Subject: [PATCH] [NFC][AMDGPU] Use SIInstrFlags predicates in
SIMemoryLegalizer and AMDGPUBaseInfo
Replace raw TSFlags accesses with SIInstrFlags predicate calls in
SIMemoryLegalizer and AMDGPUBaseInfo.
Part of a series following the introduction of SIInstrFlags predicates.
---
llvm/lib/Target/AMDGPU/SIDefines.h | 3 ++
llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp | 12 +++----
.../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 36 +++++++++----------
3 files changed, 25 insertions(+), 26 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h
index 61e3a095750d1..a7dd7b5f8dd10 100644
--- a/llvm/lib/Target/AMDGPU/SIDefines.h
+++ b/llvm/lib/Target/AMDGPU/SIDefines.h
@@ -375,6 +375,9 @@ template <typename... T> constexpr bool isGWS(const T &...O) {
template <typename... T> constexpr bool isSWMMAC(const T &...O) {
return getTSFlags(O...) & IsSWMMAC;
}
+template <typename... T> constexpr bool isVOPD3(const T &...O) {
+ return getTSFlags(O...) & VOPD3;
+}
template <typename... T> constexpr bool usesVM_CNT(const T &...O) {
return getTSFlags(O...) & VM_CNT;
}
diff --git a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
index 12f73d8caf630..217c1714ef9a4 100644
--- a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
@@ -904,7 +904,7 @@ std::optional<SIMemOpInfo> SIMemOpAccess::constructFromMIWithMMO(
std::optional<SIMemOpInfo>
SIMemOpAccess::getLoadInfo(const MachineBasicBlock::iterator &MI) const {
- assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic);
+ assert(SIInstrFlags::isMaybeAtomic(*MI));
if (!(MI->mayLoad() && !MI->mayStore()))
return std::nullopt;
@@ -918,7 +918,7 @@ SIMemOpAccess::getLoadInfo(const MachineBasicBlock::iterator &MI) const {
std::optional<SIMemOpInfo>
SIMemOpAccess::getStoreInfo(const MachineBasicBlock::iterator &MI) const {
- assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic);
+ assert(SIInstrFlags::isMaybeAtomic(*MI));
if (!(!MI->mayLoad() && MI->mayStore()))
return std::nullopt;
@@ -932,7 +932,7 @@ SIMemOpAccess::getStoreInfo(const MachineBasicBlock::iterator &MI) const {
std::optional<SIMemOpInfo>
SIMemOpAccess::getAtomicFenceInfo(const MachineBasicBlock::iterator &MI) const {
- assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic);
+ assert(SIInstrFlags::isMaybeAtomic(*MI));
if (MI->getOpcode() != AMDGPU::ATOMIC_FENCE)
return std::nullopt;
@@ -974,7 +974,7 @@ SIMemOpAccess::getAtomicFenceInfo(const MachineBasicBlock::iterator &MI) const {
std::optional<SIMemOpInfo> SIMemOpAccess::getAtomicCmpxchgOrRmwInfo(
const MachineBasicBlock::iterator &MI) const {
- assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic);
+ assert(SIInstrFlags::isMaybeAtomic(*MI));
if (!(MI->mayLoad() && MI->mayStore()))
return std::nullopt;
@@ -988,7 +988,7 @@ std::optional<SIMemOpInfo> SIMemOpAccess::getAtomicCmpxchgOrRmwInfo(
std::optional<SIMemOpInfo>
SIMemOpAccess::getLDSDMAInfo(const MachineBasicBlock::iterator &MI) const {
- assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic);
+ assert(SIInstrFlags::isMaybeAtomic(*MI));
if (!SIInstrInfo::isLDSDMA(*MI))
return std::nullopt;
@@ -2608,7 +2608,7 @@ bool SIMemoryLegalizer::run(MachineFunction &MF) {
MI = MI->eraseFromParent();
}
- if (MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic) {
+ if (SIInstrFlags::isMaybeAtomic(*MI)) {
if (const auto &MOI = MOA.getLoadInfo(MI))
Changed |= expandLoad(*MOI, MI);
else if (const auto &MOI = MOA.getStoreInfo(MI))
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 71d95a23e30d3..323c49c151ca3 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -816,7 +816,7 @@ bool isTensorStore(unsigned Opc) {
}
unsigned getTemporalHintType(const MCInstrDesc TID) {
- if (TID.TSFlags & (SIInstrFlags::IsAtomicNoRet | SIInstrFlags::IsAtomicRet))
+ if (SIInstrFlags::isAtomic(TID))
return CPol::TH_TYPE_ATOMIC;
unsigned Opc = TID.getOpcode();
// Async and Tensor store should have the temporal hint type of TH_TYPE_STORE
@@ -914,7 +914,7 @@ ComponentProps::ComponentProps(const MCInstrDesc &OpDesc, bool VOP3Layout) {
HasSrc2Acc = TiedIdx != -1;
Opcode = OpDesc.getOpcode();
- IsVOP3 = VOP3Layout || (OpDesc.TSFlags & SIInstrFlags::VOP3);
+ IsVOP3 = VOP3Layout || SIInstrFlags::isVOP3(OpDesc);
SrcOperandsNum = AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2) ? 3
: AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::imm) ? 3
: AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src1) ? 2
@@ -937,7 +937,7 @@ ComponentProps::ComponentProps(const MCInstrDesc &OpDesc, bool VOP3Layout) {
--NumVOPD3Mods;
}
- if (OpDesc.TSFlags & SIInstrFlags::VOP3)
+ if (SIInstrFlags::isVOP3(OpDesc))
return;
auto OperandsNum = OpDesc.getNumOperands();
@@ -1072,7 +1072,7 @@ VOPD::InstInfo getVOPDInstInfo(unsigned VOPDOpcode,
auto [OpX, OpY] = getVOPDComponents(VOPDOpcode);
const auto &OpXDesc = InstrInfo->get(OpX);
const auto &OpYDesc = InstrInfo->get(OpY);
- bool VOPD3 = InstrInfo->get(VOPDOpcode).TSFlags & SIInstrFlags::VOPD3;
+ bool VOPD3 = SIInstrFlags::isVOPD3(*InstrInfo, VOPDOpcode);
VOPD::ComponentInfo OpXInfo(OpXDesc, VOPD::ComponentKind::COMPONENT_X, VOPD3);
VOPD::ComponentInfo OpYInfo(OpYDesc, OpXInfo, VOPD3);
return VOPD::InstInfo(OpXInfo, OpYInfo);
@@ -3618,11 +3618,9 @@ getVGPRLoweringOperandTables(const MCInstrDesc &Desc) {
AMDGPU::OpName::src0Y, AMDGPU::OpName::NUM_OPERAND_NAMES,
AMDGPU::OpName::vsrc1Y, AMDGPU::OpName::vdstY};
- unsigned TSFlags = Desc.TSFlags;
-
- if (TSFlags &
- (SIInstrFlags::VOP1 | SIInstrFlags::VOP2 | SIInstrFlags::VOP3 |
- SIInstrFlags::VOP3P | SIInstrFlags::VOPC | SIInstrFlags::DPP)) {
+ if (SIInstrFlags::isVOP1(Desc) || SIInstrFlags::isVOP2(Desc) ||
+ SIInstrFlags::isVOP3Like(Desc) || SIInstrFlags::isVOPC(Desc) ||
+ SIInstrFlags::isDPP(Desc)) {
switch (Desc.getOpcode()) {
// LD_SCALE operands ignore MSB.
case AMDGPU::V_WMMA_LD_SCALE_PAIRED_B32:
@@ -3646,16 +3644,16 @@ getVGPRLoweringOperandTables(const MCInstrDesc &Desc) {
return {VOPOps, nullptr};
}
- if (TSFlags & SIInstrFlags::DS)
+ if (SIInstrFlags::isDS(Desc))
return {VDSOps, nullptr};
- if (TSFlags & SIInstrFlags::FLAT)
+ if (SIInstrFlags::isFLAT(Desc))
return {FLATOps, nullptr};
- if (TSFlags & (SIInstrFlags::MUBUF | SIInstrFlags::MTBUF))
+ if (SIInstrFlags::isBuffer(Desc))
return {BUFOps, nullptr};
- if (TSFlags & SIInstrFlags::VIMAGE)
+ if (SIInstrFlags::isVIMAGE(Desc))
return {VIMGOps, nullptr};
if (AMDGPU::isVOPD(Desc.getOpcode())) {
@@ -3664,9 +3662,9 @@ getVGPRLoweringOperandTables(const MCInstrDesc &Desc) {
(OpY == AMDGPU::V_FMAMK_F32) ? VOPDFMAMKOpsY : VOPDOpsY};
}
- assert(!(TSFlags & SIInstrFlags::MIMG));
+ assert(!SIInstrFlags::isMIMG(Desc));
- if (TSFlags & (SIInstrFlags::VSAMPLE | SIInstrFlags::EXP))
+ if (SIInstrFlags::isVSAMPLE(Desc) || SIInstrFlags::isEXP(Desc))
llvm_unreachable("Sample and export VGPR lowering is not implemented and"
" these instructions are not expected on gfx1250");
@@ -3675,15 +3673,13 @@ getVGPRLoweringOperandTables(const MCInstrDesc &Desc) {
bool supportsScaleOffset(const MCInstrInfo &MII, unsigned Opcode) {
const MCInstrDesc &Desc = MII.get(Opcode);
- uint64_t TSFlags = Desc.TSFlags;
-
- if (TSFlags & SIInstrFlags::SMRD)
+ if (SIInstrFlags::isSMRD(Desc))
return Desc.mayLoad() && !Desc.mayStore() && !getSMEMIsBuffer(Opcode);
- if (!(TSFlags & SIInstrFlags::FLAT))
+ if (!SIInstrFlags::isFLAT(Desc))
return false;
// Only SV and SVS modes are supported.
- if (TSFlags & SIInstrFlags::FlatScratch)
+ if (SIInstrFlags::isFlatScratch(MII, Opcode))
return hasNamedOperand(Opcode, OpName::vaddr);
// Only GVS mode is supported.
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