[llvm] [AArch64][GlobalISel] Add legalisation to G_EXRACT_SUBVECTOR (PR #207956)

[David Green via llvm-commits]

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davemgreen wrote:

Good stuff. Can you add these in too
```
define <2 x i32> @extract_v2i32_v10i32_2(<10 x i32> %a) {
; CHECK-LABEL: extract_v2i32_v10i32_2:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    fmov s0, w2
; CHECK-NEXT:    mov v0.s[1], w3
; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT:    ret
entry:
  %vector = call <2 x i32> @llvm.vector.extract.subvector.v2i32.v10i32(<10 x i32> %a, i64 2)
  ret <2 x i32> %vector
}

define <1 x i64> @extract_v1i64_v2i64_1(<2 x i64> %a) {
; CHECK-LABEL: extract_v1i64_v2i64_1:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    mov d0, v0.d[1]
; CHECK-NEXT:    ret
entry:
  %vector = call <1 x i64> @llvm.vector.extract.subvector.v1i64.v2i64(<2 x i64> %a, i64 1)
  ret <1 x i64> %vector
}

define <1 x i64> @extract_v1i64_v4i64_4(<4 x i64> %a) {
; CHECK-LABEL: extract_v1i64_v4i64_4:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    mov d0, v1.d[1]
; CHECK-NEXT:    ret
entry:
  %vector = call <1 x i64> @llvm.vector.extract.subvector.v1i64.v4i64(<4 x i64> %a, i64 3)
  ret <1 x i64> %vector
}
```

https://github.com/llvm/llvm-project/pull/207956