[llvm] [RISCV][SMT] add x100 vector sched info (PR #210597)
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llvm-commits at lists.llvm.org
Sun Jul 19 07:11:45 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: LiqinWeng (LiqinWeng)
<details>
<summary>Changes</summary>
---
Patch is 3.76 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/210597.diff
28 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoV.td (+12-11)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td (+12-9)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td (+2-2)
- (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+1-1)
- (modified) llvm/lib/Target/RISCV/RISCVSchedAndes45.td (+6-3)
- (modified) llvm/lib/Target/RISCV/RISCVSchedSiFive7.td (+6-3)
- (modified) llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td (+6-3)
- (modified) llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td (+8-4)
- (modified) llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td (+6-3)
- (modified) llvm/lib/Target/RISCV/RISCVSchedSpacemitX100.td (+1081-5)
- (modified) llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td (+6-3)
- (modified) llvm/lib/Target/RISCV/RISCVSchedTTAscalonX.td (+6-3)
- (modified) llvm/lib/Target/RISCV/RISCVScheduleV.td (+12-6)
- (added) llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/arithmetic.test (+4539)
- (added) llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/bitwise.test (+2891)
- (added) llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/comparison.test (+1802)
- (added) llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/conversion.test (+1166)
- (added) llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/fma.test (+1454)
- (added) llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/fp.test (+3719)
- (added) llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/mask.test (+1246)
- (added) llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/minmax.test (+746)
- (added) llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/mul-div.test (+1986)
- (added) llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/permutation.test (+2330)
- (added) llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/reduction.test (+1218)
- (added) llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/vle-vse-vlm.test (+362)
- (added) llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/vlse-vsse.test (+218)
- (added) llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/vlseg-vsseg.test (+3122)
- (added) llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/vlxe-vsxe.test (+394)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index a60d11c8172b8..63bc4eecfbe37 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -1052,23 +1052,24 @@ multiclass VNCLP_IV_V_X_I<string opcodestr, bits<6> funct6> {
}
multiclass VSLD_IV_X_I<string opcodestr, bits<6> funct6, bit slidesUp> {
- // Note: In the future, if VISlideI is also split into VSlideUpI and
- // VSlideDownI, it'll probably better to use two separate multiclasses.
defvar WriteSlideX = !if(slidesUp, "WriteVSlideUpX", "WriteVSlideDownX");
+ defvar WriteSlideI = !if(slidesUp, "WriteVSlideUpI", "WriteVSlideDownI");
def X : VALUVX<funct6, OPIVX, opcodestr # ".vx">,
SchedBinaryMC<WriteSlideX, "ReadVISlideV", "ReadVISlideX">;
def I : VALUVI<funct6, opcodestr # ".vi", uimm5>,
- SchedUnaryMC<"WriteVSlideI", "ReadVISlideV">;
+ SchedUnaryMC<WriteSlideI, "ReadVISlideV">;
}
-multiclass VSLD1_MV_X<string opcodestr, bits<6> funct6> {
+multiclass VSLD1_MV_X<string opcodestr, bits<6> funct6, bit slidesUp> {
+ defvar WriteSlide1X = !if(slidesUp, "WriteVISlide1Up", "WriteVISlide1Down");
def X : VALUVX<funct6, OPMVX, opcodestr # ".vx">,
- SchedBinaryMC<"WriteVISlide1X", "ReadVISlideV", "ReadVISlideX">;
+ SchedBinaryMC<WriteSlide1X, "ReadVISlideV", "ReadVISlideX">;
}
-multiclass VSLD1_FV_F<string opcodestr, bits<6> funct6> {
+multiclass VSLD1_FV_F<string opcodestr, bits<6> funct6, bit slidesUp> {
+ defvar WriteSlide1F = !if(slidesUp, "WriteVFSlide1Up", "WriteVFSlide1Down");
def F : VALUVF<funct6, OPFVF, opcodestr # ".vf">,
- SchedBinaryMC<"WriteVFSlide1F", "ReadVFSlideV", "ReadVFSlideF">;
+ SchedBinaryMC<WriteSlide1F, "ReadVFSlideV", "ReadVFSlideF">;
}
multiclass VGTR_IV_V_X_I<string opcodestr, bits<6> funct6> {
@@ -1765,21 +1766,21 @@ let Predicates = [HasVInstructions] in {
let Constraints = "@earlyclobber $vd", VS1VS2Constraint = SlideUp,
ElementsDependOn = EltDepsNone in {
defm VSLIDEUP_V : VSLD_IV_X_I<"vslideup", 0b001110, /*slidesUp=*/true>;
-defm VSLIDE1UP_V : VSLD1_MV_X<"vslide1up", 0b001110>;
+defm VSLIDE1UP_V : VSLD1_MV_X<"vslide1up", 0b001110, /*slidesUp=*/true>;
} // Constraints = "@earlyclobber $vd", VS1VS2Constraint = SlideUp, ElementsDependOn = EltDepsNone
let ElementsDependOn = EltDepsNone, ReadsPastVL = 1 in
defm VSLIDEDOWN_V : VSLD_IV_X_I<"vslidedown", 0b001111, /*slidesUp=*/false>;
let ElementsDependOn = EltDepsVL, ReadsPastVL = 1 in
-defm VSLIDE1DOWN_V : VSLD1_MV_X<"vslide1down", 0b001111>;
+defm VSLIDE1DOWN_V : VSLD1_MV_X<"vslide1down", 0b001111, /*slidesUp=*/false>;
} // Predicates = [HasVInstructions]
let Predicates = [HasVInstructionsAnyF] in {
let Constraints = "@earlyclobber $vd", VS1VS2Constraint = SlideUp,
ElementsDependOn = EltDepsNone in {
-defm VFSLIDE1UP_V : VSLD1_FV_F<"vfslide1up", 0b001110>;
+defm VFSLIDE1UP_V : VSLD1_FV_F<"vfslide1up", 0b001110, /*slidesUp=*/true>;
} // Constraints = "@earlyclobber $vd", VS1VS2Constraint = SlideUp
let ElementsDependOn = EltDepsVL, ReadsPastVL = 1 in
-defm VFSLIDE1DOWN_V : VSLD1_FV_F<"vfslide1down", 0b001111>;
+defm VFSLIDE1DOWN_V : VSLD1_FV_F<"vfslide1down", 0b001111, /*slidesUp=*/false>;
} // Predicates = [HasVInstructionsAnyF]
let Predicates = [HasVInstructions] in {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 077b8f8058932..31fe0ef3bf5dc 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -2222,10 +2222,11 @@ multiclass VPseudoBinaryV_VX_RM<LMULInfo m, string Constraint = ""> {
defm "_VX" : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, GPR, m, Constraint>;
}
-multiclass VPseudoVSLD1_VX<string Constraint = ""> {
+multiclass VPseudoVSLD1_VX<bit slidesUp = false, string Constraint = ""> {
+ defvar WriteSlide1X = !if(slidesUp, "WriteVISlide1Up", "WriteVISlide1Down");
foreach m = MxList in {
defm "_VX" : VPseudoBinary<m.vrclass, m.vrclass, GPR, m, Constraint>,
- SchedBinary<"WriteVISlide1X", "ReadVISlideV", "ReadVISlideX",
+ SchedBinary<WriteSlide1X, "ReadVISlideV", "ReadVISlideX",
m.MX, forcePassthruRead=true>;
}
}
@@ -2241,12 +2242,13 @@ multiclass VPseudoBinaryV_VF_RM<LMULInfo m, FPR_Info f, int sew> {
UsesVXRM=0>;
}
-multiclass VPseudoVSLD1_VF<string Constraint = ""> {
+multiclass VPseudoVSLD1_VF<bit slidesUp = false, string Constraint = ""> {
+ defvar WriteSlide1F = !if(slidesUp, "WriteVFSlide1Up", "WriteVFSlide1Down");
foreach f = FPList in {
foreach m = f.MxList in {
defm "_V" #f.FX
: VPseudoBinary<m.vrclass, m.vrclass, f.fprclass, m, Constraint>,
- SchedBinary<"WriteVFSlide1F", "ReadVFSlideV", "ReadVFSlideF", m.MX,
+ SchedBinary<WriteSlide1F, "ReadVFSlideV", "ReadVFSlideF", m.MX,
forcePassthruRead=true>;
}
}
@@ -3317,13 +3319,14 @@ multiclass VPseudoVMAC_VV_VF_AAXA_RM {
multiclass VPseudoVSLD_VX_VI<bit slidesUp = false, string Constraint = ""> {
defvar WriteSlideX = !if(slidesUp, "WriteVSlideUpX", "WriteVSlideDownX");
+ defvar WriteSlideI = !if(slidesUp, "WriteVSlideUpI", "WriteVSlideDownI");
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoVSLDV_VX<m, Constraint>,
SchedTernary<WriteSlideX, "ReadVISlideV", "ReadVISlideV",
"ReadVISlideX", mx>;
defm "" : VPseudoVSLDV_VI<m, Constraint>,
- SchedBinary<"WriteVSlideI", "ReadVISlideV", "ReadVISlideV", mx>;
+ SchedBinary<WriteSlideI, "ReadVISlideV", "ReadVISlideV", mx>;
}
}
@@ -6746,13 +6749,13 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
let Predicates = [HasVInstructions] in {
defm PseudoVSLIDEUP : VPseudoVSLD_VX_VI</*slidesUp=*/true, "@earlyclobber $rd">;
defm PseudoVSLIDEDOWN : VPseudoVSLD_VX_VI</*slidesUp=*/false>;
- defm PseudoVSLIDE1UP : VPseudoVSLD1_VX<"@earlyclobber $rd">;
- defm PseudoVSLIDE1DOWN : VPseudoVSLD1_VX;
+ defm PseudoVSLIDE1UP : VPseudoVSLD1_VX</*slidesUp=*/true, "@earlyclobber $rd">;
+ defm PseudoVSLIDE1DOWN : VPseudoVSLD1_VX</*slidesUp=*/false>;
} // Predicates = [HasVInstructions]
let Predicates = [HasVInstructionsAnyF], AltFmtType = IS_NOT_ALTFMT in {
- defm PseudoVFSLIDE1UP : VPseudoVSLD1_VF<"@earlyclobber $rd">;
- defm PseudoVFSLIDE1DOWN : VPseudoVSLD1_VF;
+ defm PseudoVFSLIDE1UP : VPseudoVSLD1_VF</*slidesUp=*/true, "@earlyclobber $rd">;
+ defm PseudoVFSLIDE1DOWN : VPseudoVSLD1_VF</*slidesUp=*/false>;
} // Predicates = [HasVInstructionsAnyF], AltFmtType = IS_NOT_ALTFMT
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
index f6489c8a273fb..ccf4a85c80824 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
@@ -373,8 +373,8 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
Sched<[WriteVMovSF, ReadVMovSF_V, ReadVMovSF_F]>;
}
-defm PseudoVFSLIDE1UP_ALT : VPseudoVSLD1_VF<"@earlyclobber $rd">;
-defm PseudoVFSLIDE1DOWN_ALT : VPseudoVSLD1_VF;
+defm PseudoVFSLIDE1UP_ALT : VPseudoVSLD1_VF</*slidesUp=*/true, "@earlyclobber $rd">;
+defm PseudoVFSLIDE1DOWN_ALT : VPseudoVSLD1_VF</*slidesUp=*/false>;
} // Predicates = [HasVInstructionsBF16], AltFmtType = IS_ALTFMT
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 6adbbe0af3782..e9704782f04da 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -853,7 +853,7 @@ def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
TuneShiftedZExtWFusion]>;
def SPACEMIT_A100 : RISCVProcessorModel<"spacemit-a100",
- SpacemitX60Model,
+ SpacemitX100Model,
!listconcat(
!listremove(RVA23S64Features,
[FeatureStdExtSha]),
diff --git a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
index 21663207cf792..867c1f2d24ad1 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
@@ -1133,10 +1133,13 @@ foreach mx = SchedMxList in {
defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = Cycles, ReleaseAtCycles = [Cycles] in {
- defm "" : LMULWriteResMX<"WriteVSlideI", [Andes45VPERMUT], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideUpI", [Andes45VPERMUT], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideDownI", [Andes45VPERMUT], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVISlide1X", [Andes45VPERMUT], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVFSlide1F", [Andes45VPERMUT], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Up", [Andes45VPERMUT], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Down", [Andes45VPERMUT], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Up", [Andes45VPERMUT], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Down", [Andes45VPERMUT], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSlideUpX", [Andes45VPERMUT], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSlideDownX", [Andes45VPERMUT], mx, IsWorstCase>;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index c2dcdaa5cd828..d163a9e73fe26 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -1141,9 +1141,12 @@ multiclass SiFive7WriteResBase<int VLEN,
let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
defm : LMULWriteResMX<"WriteVSlideUpX", [VCQ, VA1], mx, IsWorstCase>;
defm : LMULWriteResMX<"WriteVSlideDownX", [VCQ, VA1], mx, IsWorstCase>;
- defm : LMULWriteResMX<"WriteVSlideI", [VCQ, VA1], mx, IsWorstCase>;
- defm : LMULWriteResMX<"WriteVISlide1X", [VCQ, VA1], mx, IsWorstCase>;
- defm : LMULWriteResMX<"WriteVFSlide1F", [VCQ, VA1], mx, IsWorstCase>;
+ defm : LMULWriteResMX<"WriteVSlideUpI", [VCQ, VA1], mx, IsWorstCase>;
+ defm : LMULWriteResMX<"WriteVSlideDownI", [VCQ, VA1], mx, IsWorstCase>;
+ defm : LMULWriteResMX<"WriteVISlide1Up", [VCQ, VA1], mx, IsWorstCase>;
+ defm : LMULWriteResMX<"WriteVISlide1Down", [VCQ, VA1], mx, IsWorstCase>;
+ defm : LMULWriteResMX<"WriteVFSlide1Up", [VCQ, VA1], mx, IsWorstCase>;
+ defm : LMULWriteResMX<"WriteVFSlide1Down", [VCQ, VA1], mx, IsWorstCase>;
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
index 5b999c98fbc7c..1323e694dbe36 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
@@ -370,11 +370,14 @@ foreach mx = SchedMxList in {
defvar LMulLat = SiFive8VecGetLMulCycles<mx>.c;
defvar IsWorstCase = SiFive8VecIsWorstCaseMX<mx, SchedMxList>.c;
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
- defm "" : LMULWriteResMX<"WriteVSlideI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideUpI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideDownI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
}
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
- defm "" : LMULWriteResMX<"WriteVISlide1X", [SiFiveP400VEXQ0], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVFSlide1F", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Up", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Down", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Up", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Down", [SiFiveP400VEXQ0], mx, IsWorstCase>;
}
}
foreach mx = ["MF8", "MF4", "MF2", "M1"] in {
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
index db9b17f193a56..eef45b4a74fc8 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
@@ -981,12 +981,16 @@ foreach mx = SchedMxList in {
defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
let ReleaseAtCycles = [LMulLat] in {
- let Latency = SiFiveP600VSlideI<mx>.c in
- defm "" : LMULWriteResMX<"WriteVSlideI", [SiFiveP600VEXQ0], mx, IsWorstCase>;
+ let Latency = SiFiveP600VSlideI<mx>.c in {
+ defm "" : LMULWriteResMX<"WriteVSlideUpI", [SiFiveP600VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideDownI", [SiFiveP600VEXQ0], mx, IsWorstCase>;
+ }
let Latency = SiFiveP600VSlide1<mx>.c in {
- defm "" : LMULWriteResMX<"WriteVISlide1X", [SiFiveP600VEXQ0], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVFSlide1F", [SiFiveP600VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Up", [SiFiveP600VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Down", [SiFiveP600VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Up", [SiFiveP600VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Down", [SiFiveP600VEXQ0], mx, IsWorstCase>;
}
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
index b0e1c7056c34d..bda3bc8f1c3c9 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
@@ -698,11 +698,14 @@ foreach mx = SchedMxList in {
defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
- defm "" : LMULWriteResMX<"WriteVSlideI", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideUpI", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideDownI", [SiFiveP800VEXQ0], mx, IsWorstCase>;
}
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
- defm "" : LMULWriteResMX<"WriteVISlide1X", [SiFiveP800VEXQ0], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVFSlide1F", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Up", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Down", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Up", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Down", [SiFiveP800VEXQ0], mx, IsWorstCase>;
}
}
foreach mx = ["MF8", "MF4", "MF2", "M1"] in {
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX100.td b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX100.td
index 141fcb617ae7a..235c80a3c190e 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX100.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX100.td
@@ -11,6 +11,80 @@
// Scheduler model for the SpacemiT-X100 processor.
//
//===----------------------------------------------------------------------===//
+// Latency helper classes
+
+// Used for: arithmetic (min/max/vmerge/vmv),
+// saturating/averaging, FP add/sub/min/max
+class Get2348Latency<string mx> {
+ int c = GetLMULValue<[/*MF8=*/2, /*MF4=*/2, /*MF2=*/2, /*M1=*/2, /*M2=*/3, /*M4=*/4, /*M8=*/8], mx>.c;
+}
+
+//===----------------------------------------------------------------------===//
+
+class SMTX100IsWorstCaseMX<string mx, list<string> MxList> {
+ string LLMUL = LargestLMUL<MxList>.r;
+ bit c = !eq(mx, LLMUL);
+}
+
+class SMTX100IsWorstCaseMXSEW<string mx, int sew, list<string> MxList, bit isF = 0> {
+ string LLMUL = LargestLMUL<MxList>.r;
+ int SSEW = SmallestSEW<mx, isF>.r;
+ bit c = !and(!eq(mx, LLMUL), !eq(sew, SSEW));
+}
+
+defvar SMTX100VLEN = 256;
+defvar SMTX100DLEN = !div(SMTX100VLEN, 2);
+
+class SMTX100GetLMulCycles<string mx> {
+ int c = !cond(
+ !eq(mx, "M1") : 1,
+ !eq(mx, "M2") : 2,
+ !eq(mx, "M4") : 4,
+ !eq(mx, "M8") : 8,
+ !eq(mx, "MF2") : 1,
+ !eq(mx, "MF4") : 1,
+ !eq(mx, "MF8") : 1
+ );
+}
+
+class SMTX100GetVLMAX<string mx, int sew> {
+ defvar LMUL = SMTX100GetLMulCycles<mx>.c;
+ int val = !cond(
+ !eq(mx, "MF2") : !div(!div(SMTX100VLEN, 2), sew),
+ !eq(mx, "MF4") : !div(!div(SMTX100VLEN, 4), sew),
+ !eq(mx, "MF8") : !div(!div(SMTX100VLEN, 8), sew),
+ true: !div(!mul(SMTX100VLEN, LMUL), sew)
+ );
+}
+
+// Latency for segmented loads and stores are calculated as vl * nf.
+class SMTX100SegmentedLdStCycles<string mx, int sew, int nf> {
+ int c = !mul(SMTX100GetVLMAX<mx, sew>.val, nf);
+}
+
+// Measured vlse latency: a single base curve indexed by LMUL, shifted right
+// by one slot per SEW doubling (since doubling SEW is equivalent to
+// dropping one LMUL step). Combinations below MF8 for a given SEW don't
+// exist and return a dummy 0.
+class SMTX100GetVLDSLat<string mx, int sew> {
+ defvar Base = [4, 5, 9, 22, 50, 114, 242];
+ defvar Index = !cond(
+ !eq(mx, "MF8"): 0,
+ !eq(mx, "MF4"): 1,
+ !eq(mx, "MF2"): 2,
+ !eq(mx, "M1"): 3,
+ !eq(mx, "M2"): 4,
+ !eq(mx, "M4"): 5,
+ !eq(mx, "M8"): 6,
+ );
+ defvar Shift = !cond(
+ !eq(sew, 8): 0,
+ !eq(sew, 16): 1,
+ !eq(sew, 32): 2,
+ !eq(sew, 64): 3,
+ );
+ int val = !if(!lt(Index, Shift), 0, Base[!sub(Index, Shift)]);
+}
def SpacemitX100Model : SchedMachineModel {
let IssueWidth = 4; // 4 micro-ops are dispatched per cycle.
@@ -22,8 +96,7 @@ def SpacemitX100Model : SchedMachineModel {
let CompleteModel = 0;
let UnsupportedFeatures = [HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
- HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
- HasVInstructions];
+ HasStdExtZksed, HasStdExtZksh, HasStdExtZkr];
}
let SchedModel = SpacemitX100Model in {
@@ -51,6 +124,17 @@ let BufferSize = 4 in {
def SMTX100_IQ : ProcResGroup<[SMTX100_IQ0, SMTX100_IQ1]>;
def SMTX100_FQ : ProcResGroup<[SMTX100_FQ0, SMTX100_FQ1]>;
+// all vector computre inst in VEU0/VEU1
+def SMTX100_VEU0 : ProcResource<1>;
+def SMTX100_VEU1 : ProcResource<1>;
+// all vector memory inst in VEU2/VEU3
+def SMTX100_VEU2 : ProcResource<1>;
+def SMTX100_VEU3 : ProcResource<1>;
+
+def SMTX100_VIEU : ProcResGroup<[SMTX100_VEU0, SMTX100_VEU1]>;
+def SMTX100_VFPU : ProcResGroup<[SMTX100_VEU0, SMTX100_VEU1]>;
+def SMTX100_VLSU : ProcResGroup<[SMTX100_VEU2, SMTX100_VEU3]>;
+
//===----------------------------------------------------------------------===//
// Branching
@@ -245,6 +329,790 @@ let Latency = 3 in {
// Others
def : WriteRes<WriteCSR, [SMTX100_IQ0]>;
def : WriteRes<WriteNop, [SMTX100_IQ]>;
+def : WriteRes<WriteRdVLENB, [SMTX100_IQ0]>;
+
+// 6. Configuration-Setting Instructions
+def : WriteRes<WriteVSETVLI, [SMTX100_IQ0]>;
+def : WriteRes<WriteVSETIVLI, [SMTX100_IQ0]>;
+def : WriteRes<WriteVSETVL, [SMTX100_IQ0]>;
+
+// 7. Vector Loads and Stores
+foreach mx = SchedMxList in {
+ defvar IsWorstCase = SMTX100IsWorstCaseMX<mx, SchedMxList>.c;
+
+ // Unit-stride loads and stores
+ defvar VLDELat = ConstValueUntilLMULThenDoubleBase<"M4", 4, 6, mx>.c;
+ defvar VLDEOcc = ConstValueUntilLMULThenDoubleBase<"M2", 2, 3, mx>.c;
+ let Latency = VLDELat, ReleaseAtCycles = [VLDEOcc] in
+ defm "" : LMULWriteResMX<"WriteVLDE", [SMTX100_VLSU], mx, IsWorstCase>;
+
+ defvar VSTELatAndOcc = GetLMULValue<[2, 2, 2, 3, 5, 10, 18], mx>.c;
+ let Latency = VSTELatAndOcc, ReleaseAtCycles = [VSTELatAndOcc] in
+ defm "" : LMULWriteResMX<"WriteVSTE", [SMTX100_VLSU], mx, IsWorstCase>;
+
+ defvar VLDFFLat = ConstValueUntilLMULThenDoubleBase<"M4", 4, 6, mx>.c;
+ defvar VLDFFOcc = ConstValueUntilLMULThenDoubleBase<"M2", 2, 3, mx>.c;
+ let Latency = VLDFFLat, ReleaseAtCycles = [VLDFFOcc] in
+ defm "" : LMULWriteResMX<"WriteVLDFF", [SMTX100_VLSU]...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/210597
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