[llvm] [GlobalISel] Encode root operand indices in match opcodes (PR #210562)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Jul 19 04:26:51 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: David Zbarsky (dzbarsky)
<details>
<summary>Changes</summary>
GlobalISel instruction selectors and combiners frequently check or copy operands from the root instruction using a separate ULEB128 operand index. Emit operand indices 0 through 8 directly in the match opcode from `LLTOperandMatcher`, `RegisterBankOperandMatcher`, and `CopyRenderer`, retain the ULEB128 encoding for larger indices and variadic copies, and assert that GlobalISel opcodes continue to fit in one match-table byte.
An arm64 Release build with AArch64, AMDGPU, ARM, RISCV, WebAssembly, and X86 saves 445,832 B in both fully stripped `llc` (0.448%) and the upstream `llvm-driver` multicall binary (0.484%), reduces 20 generated GlobalISel tables by exactly 439,700 B (RISCV 299,662 B; AMDGPU 78,146 B), reduces `__TEXT,__const` by 438,656 B/438,608 B, and leaves `__DATA_CONST,__const` and linked fixups unchanged.
All 71 affected GlobalISel TableGen tests, all 16 TableGen unit tests, and all 1,574 supported RISCV/AMDGPU GlobalISel codegen tests pass (nine unsupported), including focused operand-index-8 and operand-index-9 fallback coverage for all three opcode families.
Work towards #<!-- -->202616
AI tool disclosure: Co-authored with OpenAI Codex.
---
Patch is 246.18 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/210562.diff
49 Files Affected:
- (modified) llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h (+32)
- (modified) llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h (+46-10)
- (modified) llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td (+1-1)
- (modified) llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-hoisting.td (+37-37)
- (modified) llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td (+5-5)
- (modified) llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td (+2-2)
- (modified) llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-miflags.td (+3-3)
- (modified) llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td (+7-7)
- (modified) llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td (+3-3)
- (modified) llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-temp-defs.td (+7-7)
- (modified) llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-variadics.td (+3-3)
- (modified) llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td (+4-4)
- (modified) llvm/test/TableGen/GlobalISelEmitter/ContextlessPredicates.td (+14-14)
- (modified) llvm/test/TableGen/GlobalISelEmitter/CustomPredicate.td (+33-33)
- (modified) llvm/test/TableGen/GlobalISelEmitter/DefaultOpsGlobalISel.td (+58-58)
- (modified) llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td (+203-203)
- (modified) llvm/test/TableGen/GlobalISelEmitter/HwModes.td (+12-12)
- (modified) llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizer.td (+6-6)
- (modified) llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizerRecursion.td (+143-143)
- (modified) llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizerSameOperand-invalid.td (+21-21)
- (modified) llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizerSameOperand.td (+1-1)
- (modified) llvm/test/TableGen/GlobalISelEmitter/OverloadedPtr.td (+6-6)
- (modified) llvm/test/TableGen/GlobalISelEmitter/RegSequence.td (+5-5)
- (modified) llvm/test/TableGen/GlobalISelEmitter/Subreg.td (+9-9)
- (modified) llvm/test/TableGen/GlobalISelEmitter/Variadic.td (+10-10)
- (modified) llvm/test/TableGen/GlobalISelEmitter/atomic-store.td (+1-1)
- (modified) llvm/test/TableGen/GlobalISelEmitter/dead-def.td (+1-1)
- (modified) llvm/test/TableGen/GlobalISelEmitter/frameindex.td (+7-7)
- (modified) llvm/test/TableGen/GlobalISelEmitter/gisel-physreg-input.td (+22-22)
- (modified) llvm/test/TableGen/GlobalISelEmitter/immAllZeroOne.td (+4-4)
- (modified) llvm/test/TableGen/GlobalISelEmitter/immarg-literal-pattern.td (+2-2)
- (modified) llvm/test/TableGen/GlobalISelEmitter/immarg-predicated.td (+1-1)
- (modified) llvm/test/TableGen/GlobalISelEmitter/immarg.td (+1-1)
- (modified) llvm/test/TableGen/GlobalISelEmitter/input-discard.td (+6-6)
- (modified) llvm/test/TableGen/GlobalISelEmitter/int64min.td (+8-8)
- (modified) llvm/test/TableGen/GlobalISelEmitter/metadata-operand.td (+2-2)
- (modified) llvm/test/TableGen/GlobalISelEmitter/multiple-output-discard.td (+9-9)
- (modified) llvm/test/TableGen/GlobalISelEmitter/multiple-output.td (+64-28)
- (modified) llvm/test/TableGen/GlobalISelEmitter/nested-subregs.td (+4-4)
- (modified) llvm/test/TableGen/GlobalISelEmitter/optional-def.td (+4-4)
- (modified) llvm/test/TableGen/GlobalISelEmitter/output-discard.td (+7-7)
- (modified) llvm/test/TableGen/GlobalISelEmitter/predicated-pattern-order.td (+11-11)
- (modified) llvm/test/TableGen/GlobalISelEmitter/undef-tied-input.td (+2-2)
- (modified) llvm/test/TableGen/GlobalISelEmitter/zero-reg.td (+5-5)
- (modified) llvm/test/TableGen/HasNoUse.td (+4-4)
- (modified) llvm/test/TableGen/RegClassByHwMode.td (+11-11)
- (modified) llvm/test/TableGen/address-space-patfrags.td (+1-1)
- (modified) llvm/test/TableGen/multiple-type-casts-patfrags.td (+4-4)
- (modified) llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.cpp (+36-21)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h
index 6e3ccf1923c40..64478eeca8465 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h
@@ -250,6 +250,16 @@ enum {
GIM_CheckType,
/// GIM_CheckType but InsnID is omitted and defaults to zero.
GIM_RootCheckType,
+ /// GIM_RootCheckType with OpIdx encoded in the opcode.
+ GIM_RootCheckType0,
+ GIM_RootCheckType1,
+ GIM_RootCheckType2,
+ GIM_RootCheckType3,
+ GIM_RootCheckType4,
+ GIM_RootCheckType5,
+ GIM_RootCheckType6,
+ GIM_RootCheckType7,
+ GIM_RootCheckType8,
/// Check the type of a pointer to any address space.
/// - InsnID(ULEB128) - Instruction ID
@@ -264,6 +274,16 @@ enum {
GIM_CheckRegBankForClass,
/// GIM_CheckRegBankForClass but InsnID is omitted and defaults to zero.
GIM_RootCheckRegBankForClass,
+ /// GIM_RootCheckRegBankForClass with OpIdx encoded in the opcode.
+ GIM_RootCheckRegBankForClass0,
+ GIM_RootCheckRegBankForClass1,
+ GIM_RootCheckRegBankForClass2,
+ GIM_RootCheckRegBankForClass3,
+ GIM_RootCheckRegBankForClass4,
+ GIM_RootCheckRegBankForClass5,
+ GIM_RootCheckRegBankForClass6,
+ GIM_RootCheckRegBankForClass7,
+ GIM_RootCheckRegBankForClass8,
/// Check the operand matches a complex predicate
/// - InsnID(ULEB128) - Instruction ID
@@ -391,6 +411,16 @@ enum {
GIR_Copy,
/// GIR_Copy but with both New/OldInsnIDs omitted and defaulting to zero.
GIR_RootToRootCopy,
+ /// GIR_RootToRootCopy with OpIdx encoded in the opcode.
+ GIR_RootToRootCopy0,
+ GIR_RootToRootCopy1,
+ GIR_RootToRootCopy2,
+ GIR_RootToRootCopy3,
+ GIR_RootToRootCopy4,
+ GIR_RootToRootCopy5,
+ GIR_RootToRootCopy6,
+ GIR_RootToRootCopy7,
+ GIR_RootToRootCopy8,
/// Copies all operand starting from OpIdx in OldInsnID into the new
/// instruction NewInsnID.
@@ -597,6 +627,8 @@ enum {
/// Keeping track of the number of the GI opcodes. Must be the last entry.
GIU_NumOpcodes,
};
+static_assert(GIU_NumOpcodes <= 256,
+ "GlobalISel opcodes must fit in a match table byte");
/// Provides the logic to execute GlobalISel match tables, which are used by the
/// instruction selector and instruction combiners as their engine to match and
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
index e0720928c6526..ccacc6f653339 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
@@ -741,10 +741,23 @@ bool GIMatchTableExecutor::executeMatchTable(
break;
}
+ case GIM_RootCheckType0:
+ case GIM_RootCheckType1:
+ case GIM_RootCheckType2:
+ case GIM_RootCheckType3:
+ case GIM_RootCheckType4:
+ case GIM_RootCheckType5:
+ case GIM_RootCheckType6:
+ case GIM_RootCheckType7:
+ case GIM_RootCheckType8:
case GIM_RootCheckType:
case GIM_CheckType: {
- uint64_t InsnID = (MatcherOpcode == GIM_RootCheckType) ? 0 : readULEB();
- uint64_t OpIdx = readULEB();
+ bool IsRoot = MatcherOpcode >= GIM_RootCheckType &&
+ MatcherOpcode <= GIM_RootCheckType8;
+ uint64_t InsnID = IsRoot ? 0 : readULEB();
+ uint64_t OpIdx = MatcherOpcode >= GIM_RootCheckType0
+ ? MatcherOpcode - GIM_RootCheckType0
+ : readULEB();
int TypeID = readS8();
DEBUG_WITH_TYPE(TgtExecutor::getName(),
dbgs() << CurrentIdx << ": GIM_CheckType(MIs[" << InsnID
@@ -823,11 +836,23 @@ bool GIMatchTableExecutor::executeMatchTable(
break;
}
+ case GIM_RootCheckRegBankForClass0:
+ case GIM_RootCheckRegBankForClass1:
+ case GIM_RootCheckRegBankForClass2:
+ case GIM_RootCheckRegBankForClass3:
+ case GIM_RootCheckRegBankForClass4:
+ case GIM_RootCheckRegBankForClass5:
+ case GIM_RootCheckRegBankForClass6:
+ case GIM_RootCheckRegBankForClass7:
+ case GIM_RootCheckRegBankForClass8:
case GIM_RootCheckRegBankForClass:
case GIM_CheckRegBankForClass: {
- uint64_t InsnID =
- (MatcherOpcode == GIM_RootCheckRegBankForClass) ? 0 : readULEB();
- uint64_t OpIdx = readULEB();
+ bool IsRoot = MatcherOpcode >= GIM_RootCheckRegBankForClass &&
+ MatcherOpcode <= GIM_RootCheckRegBankForClass8;
+ uint64_t InsnID = IsRoot ? 0 : readULEB();
+ uint64_t OpIdx = MatcherOpcode >= GIM_RootCheckRegBankForClass0
+ ? MatcherOpcode - GIM_RootCheckRegBankForClass0
+ : readULEB();
uint16_t RCEnum = readU16();
DEBUG_WITH_TYPE(TgtExecutor::getName(),
dbgs() << CurrentIdx << ": GIM_CheckRegBankForClass(MIs["
@@ -1123,13 +1148,24 @@ bool GIMatchTableExecutor::executeMatchTable(
break;
}
+ case GIR_RootToRootCopy0:
+ case GIR_RootToRootCopy1:
+ case GIR_RootToRootCopy2:
+ case GIR_RootToRootCopy3:
+ case GIR_RootToRootCopy4:
+ case GIR_RootToRootCopy5:
+ case GIR_RootToRootCopy6:
+ case GIR_RootToRootCopy7:
+ case GIR_RootToRootCopy8:
case GIR_RootToRootCopy:
case GIR_Copy: {
- uint64_t NewInsnID =
- (MatcherOpcode == GIR_RootToRootCopy) ? 0 : readULEB();
- uint64_t OldInsnID =
- (MatcherOpcode == GIR_RootToRootCopy) ? 0 : readULEB();
- uint64_t OpIdx = readULEB();
+ bool IsRoot = MatcherOpcode >= GIR_RootToRootCopy &&
+ MatcherOpcode <= GIR_RootToRootCopy8;
+ uint64_t NewInsnID = IsRoot ? 0 : readULEB();
+ uint64_t OldInsnID = IsRoot ? 0 : readULEB();
+ uint64_t OpIdx = MatcherOpcode >= GIR_RootToRootCopy0
+ ? MatcherOpcode - GIR_RootToRootCopy0
+ : readULEB();
assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
OutMIs[NewInsnID].add(State.MIs[OldInsnID]->getOperand(OpIdx));
DEBUG_WITH_TYPE(TgtExecutor::getName(),
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td
index 850c04130b865..c693ce9fc6f1c 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td
@@ -51,7 +51,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
// CHECK-NEXT: // Combiner Rule #1: ReplaceTemp
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_UNMERGE_VALUES),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // a
+// CHECK-NEXT: GIR_RootToRootCopy0, // a
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y
// CHECK-NEXT: GIR_ReplaceRegWithTempReg, /*OldInsnID*/0, /*OldOpIdx*/1, /*TempRegID*/0,
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-hoisting.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-hoisting.td
index ebad6f7ac86bf..381f69ef2d9a7 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-hoisting.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-hoisting.td
@@ -35,9 +35,9 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK: const uint8_t *GenMyCombiner::getMatchTable() const {
// CHECK-NEXT: constexpr static uint8_t MatchTable0[] = {
-// CHECK-NEXT: /* 0 */ GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(100),
+// CHECK-NEXT: /* 0 */ GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(98),
// CHECK-NEXT: /* 5 */ GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SUB),
-// CHECK-NEXT: /* 9 */ GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(54), // Rule ID 1 //
+// CHECK-NEXT: /* 9 */ GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(53), // Rule ID 1 //
// CHECK-NEXT: /* 14 */ GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule1Enabled),
// CHECK-NEXT: /* 17 */ // MIs[0] root
// CHECK-NEXT: /* 17 */ // No operand predicates
@@ -58,40 +58,40 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: /* 38 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
// CHECK-NEXT: /* 40 */ // Combiner Rule #1: SharedPreds1
// CHECK-NEXT: /* 40 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_ADD),
-// CHECK-NEXT: /* 43 */ GIR_RootToRootCopy, /*OpIdx*/0, // root
-// CHECK-NEXT: /* 45 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // A
-// CHECK-NEXT: /* 49 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // C
-// CHECK-NEXT: /* 53 */ GIR_EraseRootFromParent_Done,
-// CHECK-NEXT: /* 54 */ // Label 1: @54
-// CHECK-NEXT: /* 54 */ GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(99), // Rule ID 0 //
-// CHECK-NEXT: /* 59 */ GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled),
-// CHECK-NEXT: /* 62 */ // MIs[0] root
-// CHECK-NEXT: /* 62 */ // No operand predicates
-// CHECK-NEXT: /* 62 */ // MIs[0] add1
-// CHECK-NEXT: /* 62 */ GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
-// CHECK-NEXT: /* 66 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
-// CHECK-NEXT: /* 70 */ // MIs[1] A
-// CHECK-NEXT: /* 70 */ // No operand predicates
-// CHECK-NEXT: /* 70 */ // MIs[1] sub1
-// CHECK-NEXT: /* 70 */ GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
-// CHECK-NEXT: /* 74 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SUB),
-// CHECK-NEXT: /* 78 */ // MIs[2] B
-// CHECK-NEXT: /* 78 */ // No operand predicates
-// CHECK-NEXT: /* 78 */ // MIs[2] C
-// CHECK-NEXT: /* 78 */ // No operand predicates
-// CHECK-NEXT: /* 78 */ // MIs[0] B
-// CHECK-NEXT: /* 78 */ GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
-// CHECK-NEXT: /* 83 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
-// CHECK-NEXT: /* 85 */ // Combiner Rule #0: SharedPreds0
-// CHECK-NEXT: /* 85 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_SUB),
-// CHECK-NEXT: /* 88 */ GIR_RootToRootCopy, /*OpIdx*/0, // root
-// CHECK-NEXT: /* 90 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // A
-// CHECK-NEXT: /* 94 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // C
-// CHECK-NEXT: /* 98 */ GIR_EraseRootFromParent_Done,
-// CHECK-NEXT: /* 99 */ // Label 2: @99
-// CHECK-NEXT: /* 99 */ GIM_Reject,
-// CHECK-NEXT: /* 100 */ // Label 0: @100
-// CHECK-NEXT: /* 100 */ GIM_Reject,
-// CHECK-NEXT: /* 101 */ }; // Size: 101 bytes
+// CHECK-NEXT: /* 43 */ GIR_RootToRootCopy0, // root
+// CHECK-NEXT: /* 44 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // A
+// CHECK-NEXT: /* 48 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // C
+// CHECK-NEXT: /* 52 */ GIR_EraseRootFromParent_Done,
+// CHECK-NEXT: /* 53 */ // Label 1: @53
+// CHECK-NEXT: /* 53 */ GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(97), // Rule ID 0 //
+// CHECK-NEXT: /* 58 */ GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled),
+// CHECK-NEXT: /* 61 */ // MIs[0] root
+// CHECK-NEXT: /* 61 */ // No operand predicates
+// CHECK-NEXT: /* 61 */ // MIs[0] add1
+// CHECK-NEXT: /* 61 */ GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+// CHECK-NEXT: /* 65 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
+// CHECK-NEXT: /* 69 */ // MIs[1] A
+// CHECK-NEXT: /* 69 */ // No operand predicates
+// CHECK-NEXT: /* 69 */ // MIs[1] sub1
+// CHECK-NEXT: /* 69 */ GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+// CHECK-NEXT: /* 73 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SUB),
+// CHECK-NEXT: /* 77 */ // MIs[2] B
+// CHECK-NEXT: /* 77 */ // No operand predicates
+// CHECK-NEXT: /* 77 */ // MIs[2] C
+// CHECK-NEXT: /* 77 */ // No operand predicates
+// CHECK-NEXT: /* 77 */ // MIs[0] B
+// CHECK-NEXT: /* 77 */ GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
+// CHECK-NEXT: /* 82 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
+// CHECK-NEXT: /* 84 */ // Combiner Rule #0: SharedPreds0
+// CHECK-NEXT: /* 84 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_SUB),
+// CHECK-NEXT: /* 87 */ GIR_RootToRootCopy0, // root
+// CHECK-NEXT: /* 88 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // A
+// CHECK-NEXT: /* 92 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // C
+// CHECK-NEXT: /* 96 */ GIR_EraseRootFromParent_Done,
+// CHECK-NEXT: /* 97 */ // Label 2: @97
+// CHECK-NEXT: /* 97 */ GIM_Reject,
+// CHECK-NEXT: /* 98 */ // Label 0: @98
+// CHECK-NEXT: /* 98 */ GIM_Reject,
+// CHECK-NEXT: /* 99 */ }; // Size: 99 bytes
// CHECK-NEXT: return MatchTable0;
// CHECK-NEXT: }
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td
index e0b802447ea2a..65e7944294368 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td
@@ -41,13 +41,13 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: // Label 0: @[[L462]]
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4([[L492:[0-9]+]]), // Rule ID 0 //
// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled),
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
// CHECK-NEXT: // MIs[0] a
// CHECK-NEXT: // No operand predicates
// CHECK-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
// CHECK-NEXT: // Combiner Rule #0: InstTest0
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // a
+// CHECK-NEXT: GIR_RootToRootCopy0, // a
// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
// CHECK-NEXT: // Label 4: @[[L492]]
@@ -55,13 +55,13 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: // Label 1: @[[L493]]
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4([[L538:[0-9]+]]), // Rule ID 2 //
// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule2Enabled),
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
// CHECK-NEXT: // MIs[0] a
// CHECK-NEXT: // No operand predicates
// CHECK-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, GIMT_Encode8(0),
// CHECK-NEXT: // Combiner Rule #2: CImmInstTest1
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_CONSTANT),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // a
+// CHECK-NEXT: GIR_RootToRootCopy0, // a
// CHECK-NEXT: GIR_AddCImm, /*InsnID*/0, /*Type*/GILLT_s32, /*Imm*/GIMT_Encode8(42),
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
// CHECK-NEXT: // Label 5: @[[L538]]
@@ -77,7 +77,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0),
// CHECK-NEXT: // Combiner Rule #1: InstTest1
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // a
+// CHECK-NEXT: GIR_RootToRootCopy0, // a
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
// CHECK-NEXT: // Label 6: @[[L578]]
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td
index 22cb105355ab1..2c27217260163 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td
@@ -67,7 +67,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_INTRINSIC_CONVERGENT),
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_AddIntrinsicID, /*MI*/0, GIMT_Encode2(Intrinsic::convergent_1in_1out),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // b
+// CHECK-NEXT: GIR_RootToRootCopy2, // b
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // a
// CHECK-NEXT: GIR_AddIntrinsicID, /*MI*/1, GIMT_Encode2(Intrinsic::convergent_sideeffects_1in_1out),
@@ -78,6 +78,6 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIM_Reject,
// CHECK-NEXT: // Label 2: @[[L132]]
// CHECK-NEXT: GIM_Reject,
-// CHECK-NEXT: }; // Size: 125 bytes
+// CHECK-NEXT: }; // Size: 124 bytes
// CHECK-NEXT: return MatchTable0;
// CHECK-NEXT: }
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-miflags.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-miflags.td
index 24864e8aef456..37f723156531a 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-miflags.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-miflags.td
@@ -17,7 +17,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [MIFlagsTest]>;
// CHECK: const uint8_t *GenMyCombiner::getMatchTable() const {
// CHECK-NEXT: constexpr static uint8_t MatchTable0[] = {
-// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(63), // Rule ID 0 //
+// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(62), // Rule ID 0 //
// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled),
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SEXT),
// CHECK-NEXT: // MIs[0] dst
@@ -32,14 +32,14 @@ def MyCombiner: GICombiner<"GenMyCombiner", [MIFlagsTest]>;
// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1,
// CHECK-NEXT: // Combiner Rule #0: MIFlagsTest
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_MUL),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // dst
+// CHECK-NEXT: GIR_RootToRootCopy0, // dst
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
// CHECK-NEXT: GIR_CopyMIFlags, /*InsnID*/0, /*OldInsnID*/1,
// CHECK-NEXT: GIR_SetMIFlags, /*InsnID*/0, GIMT_Encode4(MachineInstr::FmReassoc),
// CHECK-NEXT: GIR_UnsetMIFlags, /*InsnID*/0, GIMT_Encode4(MachineInstr::FmNsz | MachineInstr::FmArcp),
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
-// CHECK-NEXT: // Label 0: @63
+// CHECK-NEXT: // Label 0: @62
// CHECK-NEXT: GIM_Reject,
// CHECK-NEXT: };
// CHECK-NEXT: return MatchTable0;
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td
index e359ddf73cd8a..0f6203fb79ce2 100644
--- a/llvm/test/TableGe...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/210562
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