[llvm] [X86] combineShiftRightLogical - fold srl(vecreduce_umax(x),bw-1) as MOVMSK signbit reduction (PR #210281)

[Simon Pilgrim via llvm-commits]

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@@ -50917,6 +50910,33 @@ static SDValue combineShiftRightLogical(SDNode *N, SelectionDAG &DAG,
     }
   }
 
+  // VectorCombine may have folded:
+  // icmp_eq(vecreduce_or(splatsign(x)),0) --> icmp_sgt(vecreduce_umax(x),-1)
+  // which DAG folds to: srl(vecreduce_umax(x),bw-1).
+  // This attempts to reconstruct the signbit reduction.
+  if (sd_match(N1, m_SpecificInt(EltSizeInBits - 1))) {
+    SDValue X = N0;
+    ISD::CondCode CC = ISD::SETNE;
+    if (sd_match(N0, m_Not(m_Value(X))))
+      CC = ISD::SETEQ;
+    if (X.getOpcode() == ISD::VECREDUCE_UMAX) {
+      SDValue V = X.getOperand(0);
+      EVT VecVT = V.getValueType();
+      if (DAG.getTargetLoweringInfo().isTypeLegal(VecVT) &&
+          (VecVT.is128BitVector() || VecVT.is256BitVector())) {
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RKSimon wrote:

I'll add test coverage to check how bad 512-bit cases look like

https://github.com/llvm/llvm-project/pull/210281