[llvm] [GlobalISel] Encode root operand indices in match opcodes (PR #210562)
David Zbarsky via llvm-commits
llvm-commits at lists.llvm.org
Sat Jul 18 18:36:25 PDT 2026
https://github.com/dzbarsky created https://github.com/llvm/llvm-project/pull/210562
GlobalISel instruction selectors and combiners frequently check or copy operands from the root instruction using a separate ULEB128 operand index. Emit operand indices 0 through 8 directly in the match opcode from `LLTOperandMatcher`, `RegisterBankOperandMatcher`, and `CopyRenderer`, retain the ULEB128 encoding for larger indices and variadic copies, and assert that GlobalISel opcodes continue to fit in one match-table byte.
An arm64 Release build with AArch64, AMDGPU, ARM, RISCV, WebAssembly, and X86 saves 445,832 B in both fully stripped `llc` (0.448%) and the upstream `llvm-driver` multicall binary (0.484%), reduces 20 generated GlobalISel tables by exactly 439,700 B (RISCV 299,662 B; AMDGPU 78,146 B), reduces `__TEXT,__const` by 438,656 B/438,608 B, and leaves `__DATA_CONST,__const` and linked fixups unchanged.
All 71 affected GlobalISel TableGen tests, all 16 TableGen unit tests, and all 1,574 supported RISCV/AMDGPU GlobalISel codegen tests pass (nine unsupported), including focused operand-index-8 and operand-index-9 fallback coverage for all three opcode families.
Work towards #202616
AI tool disclosure: Co-authored with OpenAI Codex.
>From 3d3685c6ad4eb8fbba14ea50b8d28a0f9e15a686 Mon Sep 17 00:00:00 2001
From: David Zbarsky <dzbarsky at gmail.com>
Date: Sat, 18 Jul 2026 20:51:00 -0400
Subject: [PATCH] [GlobalISel] Encode root operand indices in match opcodes
GlobalISel instruction selectors and combiners frequently check or copy operands from the root instruction. The existing match opcodes store each root operand index as a separate ULEB128 value.
Emit root operand indices 0 through 8 directly in GlobalISel match opcodes from LLTOperandMatcher, RegisterBankOperandMatcher, and CopyRenderer. Keep the existing ULEB128 encoding for larger indices and variadic copies, and assert that GlobalISel opcodes continue to fit in one match-table byte.
An arm64 Release build with AArch64, AMDGPU, ARM, RISCV, WebAssembly, and X86 reduces fully stripped llc from 99,455,024 to 99,009,192 bytes, saving 445,832 bytes (0.448%), and the upstream llvm-driver multicall binary from 92,133,720 to 91,687,888 bytes, saving 445,832 bytes (0.484%). The 20 generated GlobalISel match tables shrink by exactly 439,700 bytes, one byte for each compact root opcode, including 299,662 bytes for RISCV and 78,146 bytes for AMDGPU. The linked __TEXT,__const sections shrink by 438,656 bytes in llc and 438,608 bytes in llvm-driver; __DATA_CONST,__const and linked fixup counts are unchanged.
All 71 affected GlobalISel TableGen tests, all 16 TableGen unit tests, and all 1,574 supported RISCV and AMDGPU GlobalISel codegen tests pass, with nine unsupported tests. The focused TableGen test covers compact operand index 8 and the ULEB128 operand-index-9 fallback for all three opcode families.
---
.../CodeGen/GlobalISel/GIMatchTableExecutor.h | 32 ++
.../GlobalISel/GIMatchTableExecutorImpl.h | 56 ++-
.../builtins/match-table-replacerreg.td | 2 +-
.../match-table-hoisting.td | 74 ++--
.../match-table-imms.td | 10 +-
.../match-table-intrinsics.td | 4 +-
.../match-table-miflags.td | 6 +-
.../match-table-operand-types.td | 14 +-
.../match-table-patfrag-root.td | 6 +-
.../match-table-temp-defs.td | 14 +-
.../match-table-variadics.td | 6 +-
.../GlobalISelCombinerEmitter/match-table.td | 8 +-
.../ContextlessPredicates.td | 28 +-
.../GlobalISelEmitter/CustomPredicate.td | 66 +--
.../GlobalISelEmitter/DefaultOpsGlobalISel.td | 116 ++---
.../GlobalISelEmitter/GlobalISelEmitter.td | 406 +++++++++---------
.../TableGen/GlobalISelEmitter/HwModes.td | 24 +-
.../GlobalISelEmitter/MatchTableOptimizer.td | 12 +-
.../MatchTableOptimizerRecursion.td | 286 ++++++------
.../MatchTableOptimizerSameOperand-invalid.td | 42 +-
.../MatchTableOptimizerSameOperand.td | 2 +-
.../GlobalISelEmitter/OverloadedPtr.td | 12 +-
.../TableGen/GlobalISelEmitter/RegSequence.td | 10 +-
.../test/TableGen/GlobalISelEmitter/Subreg.td | 18 +-
.../TableGen/GlobalISelEmitter/Variadic.td | 20 +-
.../GlobalISelEmitter/atomic-store.td | 2 +-
.../TableGen/GlobalISelEmitter/dead-def.td | 2 +-
.../TableGen/GlobalISelEmitter/frameindex.td | 14 +-
.../GlobalISelEmitter/gisel-physreg-input.td | 44 +-
.../GlobalISelEmitter/immAllZeroOne.td | 8 +-
.../immarg-literal-pattern.td | 4 +-
.../GlobalISelEmitter/immarg-predicated.td | 2 +-
.../test/TableGen/GlobalISelEmitter/immarg.td | 2 +-
.../GlobalISelEmitter/input-discard.td | 12 +-
.../TableGen/GlobalISelEmitter/int64min.td | 16 +-
.../GlobalISelEmitter/metadata-operand.td | 4 +-
.../multiple-output-discard.td | 18 +-
.../GlobalISelEmitter/multiple-output.td | 92 ++--
.../GlobalISelEmitter/nested-subregs.td | 8 +-
.../GlobalISelEmitter/optional-def.td | 8 +-
.../GlobalISelEmitter/output-discard.td | 14 +-
.../predicated-pattern-order.td | 22 +-
.../GlobalISelEmitter/undef-tied-input.td | 4 +-
.../TableGen/GlobalISelEmitter/zero-reg.td | 10 +-
llvm/test/TableGen/HasNoUse.td | 8 +-
llvm/test/TableGen/RegClassByHwMode.td | 22 +-
llvm/test/TableGen/address-space-patfrags.td | 2 +-
.../TableGen/multiple-type-casts-patfrags.td | 8 +-
.../Common/GlobalISel/MatchTable/Matchers.cpp | 57 ++-
49 files changed, 888 insertions(+), 769 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h
index 6e3ccf1923c40..64478eeca8465 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h
@@ -250,6 +250,16 @@ enum {
GIM_CheckType,
/// GIM_CheckType but InsnID is omitted and defaults to zero.
GIM_RootCheckType,
+ /// GIM_RootCheckType with OpIdx encoded in the opcode.
+ GIM_RootCheckType0,
+ GIM_RootCheckType1,
+ GIM_RootCheckType2,
+ GIM_RootCheckType3,
+ GIM_RootCheckType4,
+ GIM_RootCheckType5,
+ GIM_RootCheckType6,
+ GIM_RootCheckType7,
+ GIM_RootCheckType8,
/// Check the type of a pointer to any address space.
/// - InsnID(ULEB128) - Instruction ID
@@ -264,6 +274,16 @@ enum {
GIM_CheckRegBankForClass,
/// GIM_CheckRegBankForClass but InsnID is omitted and defaults to zero.
GIM_RootCheckRegBankForClass,
+ /// GIM_RootCheckRegBankForClass with OpIdx encoded in the opcode.
+ GIM_RootCheckRegBankForClass0,
+ GIM_RootCheckRegBankForClass1,
+ GIM_RootCheckRegBankForClass2,
+ GIM_RootCheckRegBankForClass3,
+ GIM_RootCheckRegBankForClass4,
+ GIM_RootCheckRegBankForClass5,
+ GIM_RootCheckRegBankForClass6,
+ GIM_RootCheckRegBankForClass7,
+ GIM_RootCheckRegBankForClass8,
/// Check the operand matches a complex predicate
/// - InsnID(ULEB128) - Instruction ID
@@ -391,6 +411,16 @@ enum {
GIR_Copy,
/// GIR_Copy but with both New/OldInsnIDs omitted and defaulting to zero.
GIR_RootToRootCopy,
+ /// GIR_RootToRootCopy with OpIdx encoded in the opcode.
+ GIR_RootToRootCopy0,
+ GIR_RootToRootCopy1,
+ GIR_RootToRootCopy2,
+ GIR_RootToRootCopy3,
+ GIR_RootToRootCopy4,
+ GIR_RootToRootCopy5,
+ GIR_RootToRootCopy6,
+ GIR_RootToRootCopy7,
+ GIR_RootToRootCopy8,
/// Copies all operand starting from OpIdx in OldInsnID into the new
/// instruction NewInsnID.
@@ -597,6 +627,8 @@ enum {
/// Keeping track of the number of the GI opcodes. Must be the last entry.
GIU_NumOpcodes,
};
+static_assert(GIU_NumOpcodes <= 256,
+ "GlobalISel opcodes must fit in a match table byte");
/// Provides the logic to execute GlobalISel match tables, which are used by the
/// instruction selector and instruction combiners as their engine to match and
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
index e0720928c6526..ccacc6f653339 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
@@ -741,10 +741,23 @@ bool GIMatchTableExecutor::executeMatchTable(
break;
}
+ case GIM_RootCheckType0:
+ case GIM_RootCheckType1:
+ case GIM_RootCheckType2:
+ case GIM_RootCheckType3:
+ case GIM_RootCheckType4:
+ case GIM_RootCheckType5:
+ case GIM_RootCheckType6:
+ case GIM_RootCheckType7:
+ case GIM_RootCheckType8:
case GIM_RootCheckType:
case GIM_CheckType: {
- uint64_t InsnID = (MatcherOpcode == GIM_RootCheckType) ? 0 : readULEB();
- uint64_t OpIdx = readULEB();
+ bool IsRoot = MatcherOpcode >= GIM_RootCheckType &&
+ MatcherOpcode <= GIM_RootCheckType8;
+ uint64_t InsnID = IsRoot ? 0 : readULEB();
+ uint64_t OpIdx = MatcherOpcode >= GIM_RootCheckType0
+ ? MatcherOpcode - GIM_RootCheckType0
+ : readULEB();
int TypeID = readS8();
DEBUG_WITH_TYPE(TgtExecutor::getName(),
dbgs() << CurrentIdx << ": GIM_CheckType(MIs[" << InsnID
@@ -823,11 +836,23 @@ bool GIMatchTableExecutor::executeMatchTable(
break;
}
+ case GIM_RootCheckRegBankForClass0:
+ case GIM_RootCheckRegBankForClass1:
+ case GIM_RootCheckRegBankForClass2:
+ case GIM_RootCheckRegBankForClass3:
+ case GIM_RootCheckRegBankForClass4:
+ case GIM_RootCheckRegBankForClass5:
+ case GIM_RootCheckRegBankForClass6:
+ case GIM_RootCheckRegBankForClass7:
+ case GIM_RootCheckRegBankForClass8:
case GIM_RootCheckRegBankForClass:
case GIM_CheckRegBankForClass: {
- uint64_t InsnID =
- (MatcherOpcode == GIM_RootCheckRegBankForClass) ? 0 : readULEB();
- uint64_t OpIdx = readULEB();
+ bool IsRoot = MatcherOpcode >= GIM_RootCheckRegBankForClass &&
+ MatcherOpcode <= GIM_RootCheckRegBankForClass8;
+ uint64_t InsnID = IsRoot ? 0 : readULEB();
+ uint64_t OpIdx = MatcherOpcode >= GIM_RootCheckRegBankForClass0
+ ? MatcherOpcode - GIM_RootCheckRegBankForClass0
+ : readULEB();
uint16_t RCEnum = readU16();
DEBUG_WITH_TYPE(TgtExecutor::getName(),
dbgs() << CurrentIdx << ": GIM_CheckRegBankForClass(MIs["
@@ -1123,13 +1148,24 @@ bool GIMatchTableExecutor::executeMatchTable(
break;
}
+ case GIR_RootToRootCopy0:
+ case GIR_RootToRootCopy1:
+ case GIR_RootToRootCopy2:
+ case GIR_RootToRootCopy3:
+ case GIR_RootToRootCopy4:
+ case GIR_RootToRootCopy5:
+ case GIR_RootToRootCopy6:
+ case GIR_RootToRootCopy7:
+ case GIR_RootToRootCopy8:
case GIR_RootToRootCopy:
case GIR_Copy: {
- uint64_t NewInsnID =
- (MatcherOpcode == GIR_RootToRootCopy) ? 0 : readULEB();
- uint64_t OldInsnID =
- (MatcherOpcode == GIR_RootToRootCopy) ? 0 : readULEB();
- uint64_t OpIdx = readULEB();
+ bool IsRoot = MatcherOpcode >= GIR_RootToRootCopy &&
+ MatcherOpcode <= GIR_RootToRootCopy8;
+ uint64_t NewInsnID = IsRoot ? 0 : readULEB();
+ uint64_t OldInsnID = IsRoot ? 0 : readULEB();
+ uint64_t OpIdx = MatcherOpcode >= GIR_RootToRootCopy0
+ ? MatcherOpcode - GIR_RootToRootCopy0
+ : readULEB();
assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
OutMIs[NewInsnID].add(State.MIs[OldInsnID]->getOperand(OpIdx));
DEBUG_WITH_TYPE(TgtExecutor::getName(),
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td
index 850c04130b865..c693ce9fc6f1c 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td
@@ -51,7 +51,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
// CHECK-NEXT: // Combiner Rule #1: ReplaceTemp
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_UNMERGE_VALUES),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // a
+// CHECK-NEXT: GIR_RootToRootCopy0, // a
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y
// CHECK-NEXT: GIR_ReplaceRegWithTempReg, /*OldInsnID*/0, /*OldOpIdx*/1, /*TempRegID*/0,
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-hoisting.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-hoisting.td
index ebad6f7ac86bf..381f69ef2d9a7 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-hoisting.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-hoisting.td
@@ -35,9 +35,9 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK: const uint8_t *GenMyCombiner::getMatchTable() const {
// CHECK-NEXT: constexpr static uint8_t MatchTable0[] = {
-// CHECK-NEXT: /* 0 */ GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(100),
+// CHECK-NEXT: /* 0 */ GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(98),
// CHECK-NEXT: /* 5 */ GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SUB),
-// CHECK-NEXT: /* 9 */ GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(54), // Rule ID 1 //
+// CHECK-NEXT: /* 9 */ GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(53), // Rule ID 1 //
// CHECK-NEXT: /* 14 */ GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule1Enabled),
// CHECK-NEXT: /* 17 */ // MIs[0] root
// CHECK-NEXT: /* 17 */ // No operand predicates
@@ -58,40 +58,40 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: /* 38 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
// CHECK-NEXT: /* 40 */ // Combiner Rule #1: SharedPreds1
// CHECK-NEXT: /* 40 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_ADD),
-// CHECK-NEXT: /* 43 */ GIR_RootToRootCopy, /*OpIdx*/0, // root
-// CHECK-NEXT: /* 45 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // A
-// CHECK-NEXT: /* 49 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // C
-// CHECK-NEXT: /* 53 */ GIR_EraseRootFromParent_Done,
-// CHECK-NEXT: /* 54 */ // Label 1: @54
-// CHECK-NEXT: /* 54 */ GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(99), // Rule ID 0 //
-// CHECK-NEXT: /* 59 */ GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled),
-// CHECK-NEXT: /* 62 */ // MIs[0] root
-// CHECK-NEXT: /* 62 */ // No operand predicates
-// CHECK-NEXT: /* 62 */ // MIs[0] add1
-// CHECK-NEXT: /* 62 */ GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
-// CHECK-NEXT: /* 66 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
-// CHECK-NEXT: /* 70 */ // MIs[1] A
-// CHECK-NEXT: /* 70 */ // No operand predicates
-// CHECK-NEXT: /* 70 */ // MIs[1] sub1
-// CHECK-NEXT: /* 70 */ GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
-// CHECK-NEXT: /* 74 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SUB),
-// CHECK-NEXT: /* 78 */ // MIs[2] B
-// CHECK-NEXT: /* 78 */ // No operand predicates
-// CHECK-NEXT: /* 78 */ // MIs[2] C
-// CHECK-NEXT: /* 78 */ // No operand predicates
-// CHECK-NEXT: /* 78 */ // MIs[0] B
-// CHECK-NEXT: /* 78 */ GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
-// CHECK-NEXT: /* 83 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
-// CHECK-NEXT: /* 85 */ // Combiner Rule #0: SharedPreds0
-// CHECK-NEXT: /* 85 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_SUB),
-// CHECK-NEXT: /* 88 */ GIR_RootToRootCopy, /*OpIdx*/0, // root
-// CHECK-NEXT: /* 90 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // A
-// CHECK-NEXT: /* 94 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // C
-// CHECK-NEXT: /* 98 */ GIR_EraseRootFromParent_Done,
-// CHECK-NEXT: /* 99 */ // Label 2: @99
-// CHECK-NEXT: /* 99 */ GIM_Reject,
-// CHECK-NEXT: /* 100 */ // Label 0: @100
-// CHECK-NEXT: /* 100 */ GIM_Reject,
-// CHECK-NEXT: /* 101 */ }; // Size: 101 bytes
+// CHECK-NEXT: /* 43 */ GIR_RootToRootCopy0, // root
+// CHECK-NEXT: /* 44 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // A
+// CHECK-NEXT: /* 48 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // C
+// CHECK-NEXT: /* 52 */ GIR_EraseRootFromParent_Done,
+// CHECK-NEXT: /* 53 */ // Label 1: @53
+// CHECK-NEXT: /* 53 */ GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(97), // Rule ID 0 //
+// CHECK-NEXT: /* 58 */ GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled),
+// CHECK-NEXT: /* 61 */ // MIs[0] root
+// CHECK-NEXT: /* 61 */ // No operand predicates
+// CHECK-NEXT: /* 61 */ // MIs[0] add1
+// CHECK-NEXT: /* 61 */ GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+// CHECK-NEXT: /* 65 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
+// CHECK-NEXT: /* 69 */ // MIs[1] A
+// CHECK-NEXT: /* 69 */ // No operand predicates
+// CHECK-NEXT: /* 69 */ // MIs[1] sub1
+// CHECK-NEXT: /* 69 */ GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+// CHECK-NEXT: /* 73 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SUB),
+// CHECK-NEXT: /* 77 */ // MIs[2] B
+// CHECK-NEXT: /* 77 */ // No operand predicates
+// CHECK-NEXT: /* 77 */ // MIs[2] C
+// CHECK-NEXT: /* 77 */ // No operand predicates
+// CHECK-NEXT: /* 77 */ // MIs[0] B
+// CHECK-NEXT: /* 77 */ GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
+// CHECK-NEXT: /* 82 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
+// CHECK-NEXT: /* 84 */ // Combiner Rule #0: SharedPreds0
+// CHECK-NEXT: /* 84 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_SUB),
+// CHECK-NEXT: /* 87 */ GIR_RootToRootCopy0, // root
+// CHECK-NEXT: /* 88 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // A
+// CHECK-NEXT: /* 92 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // C
+// CHECK-NEXT: /* 96 */ GIR_EraseRootFromParent_Done,
+// CHECK-NEXT: /* 97 */ // Label 2: @97
+// CHECK-NEXT: /* 97 */ GIM_Reject,
+// CHECK-NEXT: /* 98 */ // Label 0: @98
+// CHECK-NEXT: /* 98 */ GIM_Reject,
+// CHECK-NEXT: /* 99 */ }; // Size: 99 bytes
// CHECK-NEXT: return MatchTable0;
// CHECK-NEXT: }
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td
index e0b802447ea2a..65e7944294368 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td
@@ -41,13 +41,13 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: // Label 0: @[[L462]]
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4([[L492:[0-9]+]]), // Rule ID 0 //
// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled),
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
// CHECK-NEXT: // MIs[0] a
// CHECK-NEXT: // No operand predicates
// CHECK-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
// CHECK-NEXT: // Combiner Rule #0: InstTest0
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // a
+// CHECK-NEXT: GIR_RootToRootCopy0, // a
// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
// CHECK-NEXT: // Label 4: @[[L492]]
@@ -55,13 +55,13 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: // Label 1: @[[L493]]
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4([[L538:[0-9]+]]), // Rule ID 2 //
// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule2Enabled),
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
// CHECK-NEXT: // MIs[0] a
// CHECK-NEXT: // No operand predicates
// CHECK-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, GIMT_Encode8(0),
// CHECK-NEXT: // Combiner Rule #2: CImmInstTest1
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_CONSTANT),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // a
+// CHECK-NEXT: GIR_RootToRootCopy0, // a
// CHECK-NEXT: GIR_AddCImm, /*InsnID*/0, /*Type*/GILLT_s32, /*Imm*/GIMT_Encode8(42),
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
// CHECK-NEXT: // Label 5: @[[L538]]
@@ -77,7 +77,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0),
// CHECK-NEXT: // Combiner Rule #1: InstTest1
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // a
+// CHECK-NEXT: GIR_RootToRootCopy0, // a
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
// CHECK-NEXT: // Label 6: @[[L578]]
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td
index 22cb105355ab1..2c27217260163 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td
@@ -67,7 +67,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_INTRINSIC_CONVERGENT),
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_AddIntrinsicID, /*MI*/0, GIMT_Encode2(Intrinsic::convergent_1in_1out),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // b
+// CHECK-NEXT: GIR_RootToRootCopy2, // b
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // a
// CHECK-NEXT: GIR_AddIntrinsicID, /*MI*/1, GIMT_Encode2(Intrinsic::convergent_sideeffects_1in_1out),
@@ -78,6 +78,6 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIM_Reject,
// CHECK-NEXT: // Label 2: @[[L132]]
// CHECK-NEXT: GIM_Reject,
-// CHECK-NEXT: }; // Size: 125 bytes
+// CHECK-NEXT: }; // Size: 124 bytes
// CHECK-NEXT: return MatchTable0;
// CHECK-NEXT: }
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-miflags.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-miflags.td
index 24864e8aef456..37f723156531a 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-miflags.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-miflags.td
@@ -17,7 +17,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [MIFlagsTest]>;
// CHECK: const uint8_t *GenMyCombiner::getMatchTable() const {
// CHECK-NEXT: constexpr static uint8_t MatchTable0[] = {
-// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(63), // Rule ID 0 //
+// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(62), // Rule ID 0 //
// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled),
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SEXT),
// CHECK-NEXT: // MIs[0] dst
@@ -32,14 +32,14 @@ def MyCombiner: GICombiner<"GenMyCombiner", [MIFlagsTest]>;
// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1,
// CHECK-NEXT: // Combiner Rule #0: MIFlagsTest
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_MUL),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // dst
+// CHECK-NEXT: GIR_RootToRootCopy0, // dst
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
// CHECK-NEXT: GIR_CopyMIFlags, /*InsnID*/0, /*OldInsnID*/1,
// CHECK-NEXT: GIR_SetMIFlags, /*InsnID*/0, GIMT_Encode4(MachineInstr::FmReassoc),
// CHECK-NEXT: GIR_UnsetMIFlags, /*InsnID*/0, GIMT_Encode4(MachineInstr::FmNsz | MachineInstr::FmArcp),
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
-// CHECK-NEXT: // Label 0: @63
+// CHECK-NEXT: // Label 0: @62
// CHECK-NEXT: GIM_Reject,
// CHECK-NEXT: };
// CHECK-NEXT: return MatchTable0;
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td
index e359ddf73cd8a..0f6203fb79ce2 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td
@@ -21,12 +21,12 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK: const uint8_t *GenMyCombiner::getMatchTable() const {
// CHECK-NEXT: constexpr static uint8_t MatchTable0[] = {
-// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(73), // Rule ID 0 //
+// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(69), // Rule ID 0 //
// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled),
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL),
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s8,
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
// CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
@@ -37,15 +37,15 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: // Combiner Rule #0: InstTest0
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_ADD),
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // b
+// CHECK-NEXT: GIR_RootToRootCopy1, // b
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // c
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_ADD),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // a
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // b
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
-// CHECK-NEXT: // Label 0: @73
+// CHECK-NEXT: // Label 0: @69
// CHECK-NEXT: GIM_Reject,
-// CHECK-NEXT: }; // Size: 74 bytes
+// CHECK-NEXT: }; // Size: 70 bytes
// CHECK-NEXT: return MatchTable0;
// CHECK-NEXT: }
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td
index 5a8b51dfc8324..d118e22038b70 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td
@@ -43,7 +43,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0),
// CHECK-NEXT: // Combiner Rule #0: Test0 @ [__Test0_match_0[1]]
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // root
+// CHECK-NEXT: GIR_RootToRootCopy0, // root
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
// CHECK-NEXT: // Label 4: @[[L297]]
@@ -63,7 +63,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0),
// CHECK-NEXT: // Combiner Rule #0: Test0 @ [__Test0_match_0[0]]
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // root
+// CHECK-NEXT: GIR_RootToRootCopy0, // root
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
// CHECK-NEXT: // Label 5: @[[L343]]
@@ -79,7 +79,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0),
// CHECK-NEXT: // Combiner Rule #0: Test0 @ [__Test0_match_0[2]]
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // root
+// CHECK-NEXT: GIR_RootToRootCopy0, // root
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
// CHECK-NEXT: // Label 6: @[[L379]]
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-temp-defs.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-temp-defs.td
index 23794fbc510ad..04954d0be90a5 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-temp-defs.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-temp-defs.td
@@ -38,19 +38,19 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK: // Combiner Rule #0: Test0
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_UDIVREM),
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // dst
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // lhs
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // rhs
+// CHECK-NEXT: GIR_RootToRootCopy0, // dst
+// CHECK-NEXT: GIR_RootToRootCopy1, // lhs
+// CHECK-NEXT: GIR_RootToRootCopy2, // rhs
// CHECK: // Combiner Rule #1: Test1
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_UDIVREM),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // dst
+// CHECK-NEXT: GIR_RootToRootCopy0, // dst
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // lhs
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // rhs
+// CHECK-NEXT: GIR_RootToRootCopy1, // lhs
+// CHECK-NEXT: GIR_RootToRootCopy2, // rhs
// CHECK: // Combiner Rule #2: Test2
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_ADD),
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // lhs
+// CHECK-NEXT: GIR_RootToRootCopy1, // lhs
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-variadics.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-variadics.td
index 98456983c085b..cf7e95a1ba447 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-variadics.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-variadics.td
@@ -129,9 +129,9 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: // No operand predicates
// CHECK-NEXT: // Combiner Rule #5: VariadicTypeTestReuse
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_MERGE_VALUES),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // a
+// CHECK-NEXT: GIR_RootToRootCopy0, // a
// CHECK-NEXT: GIR_CopyRemaining, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // c
+// CHECK-NEXT: GIR_RootToRootCopy1, // c
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
// CHECK-NEXT: // Label 7: @{{[0-9]+}}
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4({{[0-9]+}}), // Rule ID 0 //
@@ -151,6 +151,6 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIM_Reject,
// CHECK-NEXT: // Label 2: @{{[0-9]+}}
// CHECK-NEXT: GIM_Reject,
-// CHECK-NEXT: }; // Size: 128 bytes
+// CHECK-NEXT: }; // Size: 126 bytes
// CHECK-NEXT: return MatchTable0;
// CHECK-NEXT: }
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td
index 58c25ab925b85..3bd4ebb9661f7 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td
@@ -186,7 +186,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: // Label 1: @[[L1]]
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 9*/ GIMT_Encode4([[L9:[0-9]+]]), // Rule ID 6 //
// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule5Enabled),
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
// CHECK-NEXT: // MIs[0] dst
// CHECK-NEXT: // No operand predicates
// CHECK-NEXT: // MIs[0] x
@@ -198,7 +198,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1,
// CHECK-NEXT: // Combiner Rule #5: InOutInstTest1
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_TRUNC),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // dst
+// CHECK-NEXT: GIR_RootToRootCopy0, // dst
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // z
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
// CHECK-NEXT: // Label 9: @[[L9]]
@@ -217,7 +217,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: // Combiner Rule #4: InOutInstTest0
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_STORE),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ext
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // ptr
+// CHECK-NEXT: GIR_RootToRootCopy1, // ptr
// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
// CHECK-NEXT: // Label 10: @[[L10]]
@@ -253,7 +253,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0),
// CHECK-NEXT: // Combiner Rule #6: PatFragTest0 @ [__PatFragTest0_match_1[0]]
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // dst
+// CHECK-NEXT: GIR_RootToRootCopy0, // dst
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
// CHECK-NEXT: // Label 14: @[[L14]]
diff --git a/llvm/test/TableGen/GlobalISelEmitter/ContextlessPredicates.td b/llvm/test/TableGen/GlobalISelEmitter/ContextlessPredicates.td
index 93525f751fa79..8e5d6bd3eb3e2 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/ContextlessPredicates.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/ContextlessPredicates.td
@@ -22,26 +22,26 @@ def : Pat<(test_atomic_op_frag GPR32:$ptr, GPR32:$val) ,
// CHECK_NOPT-LABEL: const uint8_t *MyTargetInstructionSelector::getMatchTable() const {
// CHECK_NOPT-NEXT: constexpr static uint8_t MatchTable0[] = {
-// CHECK_NOPT-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(52), // Rule ID 0 //
+// CHECK_NOPT-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(47), // Rule ID 0 //
// CHECK_NOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
// CHECK_NOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ATOMICRMW_XCHG),
// CHECK_NOPT-NEXT: GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
// CHECK_NOPT-NEXT: // MIs[0] DstI[dst]
-// CHECK_NOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK_NOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK_NOPT-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK_NOPT-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK_NOPT-NEXT: // MIs[0] ptr
// CHECK_NOPT-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
-// CHECK_NOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK_NOPT-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK_NOPT-NEXT: // MIs[0] val
-// CHECK_NOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
-// CHECK_NOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK_NOPT-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
+// CHECK_NOPT-NEXT: GIM_RootCheckRegBankForClass2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK_NOPT-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_test_atomic_op_frag),
// CHECK_NOPT-NEXT: // (atomic_swap:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val)<<P:Predicate_test_atomic_op_frag>> => (INSN:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val)
// CHECK_NOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::INSN),
// CHECK_NOPT-NEXT: GIR_RootConstrainSelectedInstOperands,
// CHECK_NOPT-NEXT: // GIR_Coverage, 0,
// CHECK_NOPT-NEXT: GIR_Done,
-// CHECK_NOPT-NEXT: // Label 0: @52
+// CHECK_NOPT-NEXT: // Label 0: @47
// CHECK_NOPT-NEXT: GIM_Reject,
// CHECK_NOPT-NEXT: };
// CHECK_NOPT-NEXT: return MatchTable0;
@@ -49,23 +49,23 @@ def : Pat<(test_atomic_op_frag GPR32:$ptr, GPR32:$val) ,
// CHECK_OPT-LABEL: const uint8_t *MyTargetInstructionSelector::getMatchTable() const {
// CHECK_OPT-NEXT: constexpr static uint8_t MatchTable0[] = {
-// CHECK_OPT-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(49), // Rule ID 0 //
+// CHECK_OPT-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(44), // Rule ID 0 //
// CHECK_OPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ATOMICRMW_XCHG),
-// CHECK_OPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK_OPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
+// CHECK_OPT-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK_OPT-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
// CHECK_OPT-NEXT: GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
-// CHECK_OPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK_OPT-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK_OPT-NEXT: // MIs[0] ptr
// CHECK_OPT-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
-// CHECK_OPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
-// CHECK_OPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK_OPT-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK_OPT-NEXT: GIM_RootCheckRegBankForClass2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK_OPT-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_test_atomic_op_frag),
// CHECK_OPT-NEXT: // (atomic_swap:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val)<<P:Predicate_test_atomic_op_frag>> => (INSN:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val)
// CHECK_OPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::INSN),
// CHECK_OPT-NEXT: GIR_RootConstrainSelectedInstOperands,
// CHECK_OPT-NEXT: // GIR_Coverage, 0,
// CHECK_OPT-NEXT: GIR_Done,
-// CHECK_OPT-NEXT: // Label 0: @49
+// CHECK_OPT-NEXT: // Label 0: @44
// CHECK_OPT-NEXT: GIM_Reject,
// CHECK_OPT-NEXT: };
// CHECK_OPT-NEXT: return MatchTable0;
diff --git a/llvm/test/TableGen/GlobalISelEmitter/CustomPredicate.td b/llvm/test/TableGen/GlobalISelEmitter/CustomPredicate.td
index 41e4c63036298..1ce0dfa6e4d5d 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/CustomPredicate.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/CustomPredicate.td
@@ -77,18 +77,18 @@ def and_or_pat : PatFrag<
let PredicateCodeUsesOperands = 1;
}
-// CHECK: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(97), // Rule ID 7 //
+// CHECK: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(90), // Rule ID 7 //
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_AND),
// CHECK-NEXT: // MIs[0] DstI[dst]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID),
// CHECK-NEXT: // MIs[0] src2
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:3:z
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Test::DRegsRegClassID),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(Test::DRegsRegClassID),
// CHECK-NEXT: // MIs[0] Operand 2
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
@@ -107,14 +107,14 @@ def and_or_pat : PatFrag<
// CHECK-NEXT: // (and:{ *:[i32] } DOP:{ *:[i32] }:$src2:$pred:3:z, (or:{ *:[i32] } DOP:{ *:[i32] }:$src0:$pred:3:x, DOP:{ *:[i32] }:$src1:$pred:3:y))<<P:3:Predicate_and_or_pat>> => (AND_OR:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1, DOP:{ *:[i32] }:$src2)
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::AND_OR),
-// CHECK: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(194), // Rule ID 3 //
+// CHECK: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(180), // Rule ID 3 //
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_AND),
// CHECK-NEXT: // MIs[0] DstI[dst]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID),
// CHECK-NEXT: // MIs[0] Operand 1
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
@@ -129,9 +129,9 @@ def and_or_pat : PatFrag<
// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:3:y
// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Test::DRegsRegClassID),
// CHECK-NEXT: // MIs[0] src2
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:3:z
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Test::DRegsRegClassID),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass2, /*RC*/GIMT_Encode2(Test::DRegsRegClassID),
// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_and_or_pat),
// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1,
// CHECK-NEXT: // (and:{ *:[i32] } (or:{ *:[i32] } DOP:{ *:[i32] }:$src0:$pred:3:x, DOP:{ *:[i32] }:$src1:$pred:3:y), DOP:{ *:[i32] }:$src2:$pred:3:z)<<P:3:Predicate_and_or_pat>> => (AND_OR:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1, DOP:{ *:[i32] }:$src2)
@@ -152,14 +152,14 @@ def mul_pat : PatFrag<
let PredicateCodeUsesOperands = 1;
}
-// CHECK: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(287), // Rule ID 4 //
+// CHECK: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(266), // Rule ID 4 //
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL),
// CHECK-NEXT: // MIs[0] DstI[dst]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID),
// CHECK-NEXT: // MIs[0] Operand 1
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:4:x
// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
@@ -173,26 +173,26 @@ def mul_pat : PatFrag<
// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Test::DRegsRegClassID),
// CHECK-NEXT: // MIs[0] src2
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:4:y
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Test::DRegsRegClassID),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass2, /*RC*/GIMT_Encode2(Test::DRegsRegClassID),
// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_mul_pat),
// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1,
// CHECK-NEXT: // (mul:{ *:[i32] } (or:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1):$pred:4:x, DOP:{ *:[i32] }:$src2:$pred:4:y)<<P:4:Predicate_mul_pat>> => (MUL_OR:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1, DOP:{ *:[i32] }:$src2)
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MUL_OR),
-// CHECK: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(380), // Rule ID 8 //
+// CHECK: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(352), // Rule ID 8 //
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL),
// CHECK-NEXT: // MIs[0] DstI[dst]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID),
// CHECK-NEXT: // MIs[0] src2
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:4:y
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Test::DRegsRegClassID),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(Test::DRegsRegClassID),
// CHECK-NEXT: // MIs[0] Operand 2
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:4:x
// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
@@ -227,14 +227,14 @@ def sub3_pat : PatFrag<
let PredicateCodeUsesOperands = 1;
}
-// CHECK: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(463), // Rule ID 0 //
+// CHECK: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(429), // Rule ID 0 //
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SUB),
// CHECK-NEXT: // MIs[0] DstI[dst]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID),
// CHECK-NEXT: // MIs[0] Operand 1
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
@@ -247,7 +247,7 @@ def sub3_pat : PatFrag<
// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:1:y
// CHECK-NEXT: // MIs[0] src2
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:1:z
// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_sub3_pat),
// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1,
@@ -273,16 +273,16 @@ def patfrags_test_pat : PatFrags<
let PredicateCodeUsesOperands = 1;
}
-// CHECK: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(546), // Rule ID 1 //
+// CHECK: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(506), // Rule ID 1 //
// CHECK: // (xor:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:2:x, i32:{ *:[i32] }:$src1:$pred:2:y), i32:{ *:[i32] }:$src2:$pred:2:z)<<P:2:Predicate_patfrags_test_pat>> => (PATFRAGS:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
-// CHECK: GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(629), // Rule ID 2 //
+// CHECK: GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(583), // Rule ID 2 //
// CHECK: // (xor:{ *:[i32] } (sub:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:2:x, i32:{ *:[i32] }:$src1:$pred:2:y), i32:{ *:[i32] }:$src2:$pred:2:z)<<P:2:Predicate_patfrags_test_pat>> => (PATFRAGS:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
-// CHECK: GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(712), // Rule ID 5 //
+// CHECK: GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(660), // Rule ID 5 //
// CHECK: // (xor:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:2:z, (add:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:2:x, i32:{ *:[i32] }:$src1:$pred:2:y))<<P:2:Predicate_patfrags_test_pat>> => (PATFRAGS:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
-// CHECK: GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(795), // Rule ID 6 //
+// CHECK: GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(737), // Rule ID 6 //
// CHECK: // (xor:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:2:z, (sub:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:2:x, i32:{ *:[i32] }:$src1:$pred:2:y))<<P:2:Predicate_patfrags_test_pat>> => (PATFRAGS:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
diff --git a/llvm/test/TableGen/GlobalISelEmitter/DefaultOpsGlobalISel.td b/llvm/test/TableGen/GlobalISelEmitter/DefaultOpsGlobalISel.td
index 3bb1379b0ec27..3a59202a24ed3 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/DefaultOpsGlobalISel.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/DefaultOpsGlobalISel.td
@@ -33,21 +33,21 @@ def clamp : OperandWithDefaultOps <i1, (ops (i1 0))>;
// CHECK: const uint8_t *MyTargetInstructionSelector::getMatchTable() const {
// CHECK-NEXT: constexpr static uint8_t MatchTable0[] = {
-// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(69), // Rule ID 3 //
+// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(64), // Rule ID 3 //
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
// CHECK-NEXT: // MIs[0] DstI[dst]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
// CHECK-NEXT: // MIs[0] SelectSrcMods:src0:mods0
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
// CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectSrcMods),
// CHECK-NEXT: // MIs[0] SelectSrcMods:src1:mods1
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
// CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_SelectSrcMods),
// CHECK-NEXT: // (fmaxnum:{ *:[f32] } (SelectSrcMods:{ *:[f32] } f32:{ *:[f32] }:$src0, src_mods:{ *:[i32] }:$mods0), (SelectSrcMods:{ *:[f32] } f32:{ *:[f32] }:$src1, src_mods:{ *:[i32] }:$mods1)) => (FMAX:{ *:[f32] } src_mods:{ *:[i32] }:$mods0, f32:{ *:[f32] }:$src0, src_mods:{ *:[i32] }:$mods1, f32:{ *:[f32] }:$src1)
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FMAX),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // mods0
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // mods1
@@ -56,38 +56,38 @@ def clamp : OperandWithDefaultOps <i1, (ops (i1 0))>;
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
// CHECK-NEXT: // GIR_Coverage, 3,
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
-// CHECK-NEXT: // Label 0: @69
-// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(120), // Rule ID 2 //
+// CHECK-NEXT: // Label 0: @64
+// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(111), // Rule ID 2 //
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FFLOOR),
// CHECK-NEXT: // MIs[0] DstI[dst]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
// CHECK-NEXT: // MIs[0] SelectClampOMod:src0:omod:clamp
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
// CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectClampOMod),
// CHECK-NEXT: // (ffloor:{ *:[f32] } (SelectClampOMod:{ *:[f32] } f32:{ *:[f32] }:$src0, omod:{ *:[i32] }:$omod, i1:{ *:[i1] }:$clamp)) => (FLOMP:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, omod:{ *:[i32] }:$omod)
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FLOMP),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // omod
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
// CHECK-NEXT: // GIR_Coverage, 2,
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
-// CHECK-NEXT: // Label 1: @120
-// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(179), // Rule ID 8 //
+// CHECK-NEXT: // Label 1: @111
+// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(166), // Rule ID 8 //
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE),
// CHECK-NEXT: // MIs[0] DstI[dst]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
// CHECK-NEXT: // MIs[0] SelectSrcMods:src:mods
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
// CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectSrcMods),
// CHECK-NEXT: // (fcanonicalize:{ *:[f32] } (SelectSrcMods:{ *:[f32] } f32:{ *:[f32] }:$src, i32:{ *:[i32] }:$mods)) => (FMAX:{ *:[f32] } ?:{ *:[i32] }:$mods, ?:{ *:[f32] }:$src, ?:{ *:[i32] }:$mods, ?:{ *:[f32] }:$src, 0:{ *:[i1] })
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FMAX),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // mods
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // mods
@@ -96,34 +96,34 @@ def clamp : OperandWithDefaultOps <i1, (ops (i1 0))>;
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
// CHECK-NEXT: // GIR_Coverage, 8,
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
-// CHECK-NEXT: // Label 2: @179
-// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(228), // Rule ID 5 //
+// CHECK-NEXT: // Label 2: @166
+// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(211), // Rule ID 5 //
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FCOS),
// CHECK-NEXT: // MIs[0] DstI[dst]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
// CHECK-NEXT: // MIs[0] SelectOMod:src0:omod
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
// CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectOMod),
// CHECK-NEXT: // (fcos:{ *:[f32] } (SelectOMod:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$omod)) => (FLAMP:{ *:[f32] } FPR32:{ *:[f32] }:$src0, omod:{ *:[i32] }:$omod)
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FLAMP),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // omod
// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
// CHECK-NEXT: // GIR_Coverage, 5,
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
-// CHECK-NEXT: // Label 3: @228
-// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(299), // Rule ID 7 //
+// CHECK-NEXT: // Label 3: @211
+// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(278), // Rule ID 7 //
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FEXP2),
// CHECK-NEXT: // MIs[0] DstI[dst]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
// CHECK-NEXT: // MIs[0] SelectClamp:src0:clamp
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
// CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectClamp),
// CHECK-NEXT: // (fexp2:{ *:[f32] } (SelectClamp:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp)) => (FEEPLE:{ *:[f32] } FPR32:{ *:[f32] }:$src0, (FFOO:{ *:[f32] } FPR32:{ *:[f32] }:$src0), clamp:{ *:[i1] }:$clamp)
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
@@ -133,87 +133,87 @@ def clamp : OperandWithDefaultOps <i1, (ops (i1 0))>;
// CHECK-NEXT: GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FEEPLE),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
// CHECK-NEXT: // GIR_Coverage, 7,
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
-// CHECK-NEXT: // Label 4: @299
-// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(345), // Rule ID 0 //
+// CHECK-NEXT: // Label 4: @278
+// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(320), // Rule ID 0 //
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FSIN),
// CHECK-NEXT: // MIs[0] DstI[dst]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
// CHECK-NEXT: // MIs[0] SelectClamp:src0:clamp
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
// CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectClamp),
// CHECK-NEXT: // (fsin:{ *:[f32] } (SelectClamp:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp)) => (FFOO:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp)
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FFOO),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
// CHECK-NEXT: // GIR_Coverage, 0,
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
-// CHECK-NEXT: // Label 5: @345
-// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(394), // Rule ID 6 //
+// CHECK-NEXT: // Label 5: @320
+// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(365), // Rule ID 6 //
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FSQRT),
// CHECK-NEXT: // MIs[0] DstI[dst]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
// CHECK-NEXT: // MIs[0] SelectClamp:src0:clamp
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
// CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectClamp),
// CHECK-NEXT: // (fsqrt:{ *:[f32] } (SelectClamp:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp)) => (FLAMP:{ *:[f32] } FPR32:{ *:[f32] }:$src0, 93:{ *:[i32] }, clamp:{ *:[i1] }:$clamp)
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FLAMP),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/93,
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
// CHECK-NEXT: // GIR_Coverage, 6,
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
-// CHECK-NEXT: // Label 6: @394
-// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(428), // Rule ID 1 //
+// CHECK-NEXT: // Label 6: @365
+// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(394), // Rule ID 1 //
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
// CHECK-NEXT: // MIs[0] DstI[dst]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
// CHECK-NEXT: // MIs[0] src0
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
// CHECK-NEXT: // (fround:{ *:[f32] } f32:{ *:[f32] }:$src0) => (FBAR:{ *:[f32] } f32:{ *:[f32] }:$src0)
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FBAR),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src0
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[dst]
+// CHECK-NEXT: GIR_RootToRootCopy1, // src0
// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
// CHECK-NEXT: // GIR_Coverage, 1,
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
-// CHECK-NEXT: // Label 7: @428
-// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(462), // Rule ID 4 //
+// CHECK-NEXT: // Label 7: @394
+// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(423), // Rule ID 4 //
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
// CHECK-NEXT: // MIs[0] DstI[dst]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
// CHECK-NEXT: // MIs[0] src0
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
// CHECK-NEXT: // (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$src0) => (FFOO:{ *:[f32] } FPR32:{ *:[f32] }:$src0)
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FFOO),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src0
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[dst]
+// CHECK-NEXT: GIR_RootToRootCopy1, // src0
// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
// CHECK-NEXT: // GIR_Coverage, 4,
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
-// CHECK-NEXT: // Label 8: @462
+// CHECK-NEXT: // Label 8: @423
// CHECK-NEXT: GIM_Reject,
-// CHECK-NEXT: }; // Size: 463 bytes
+// CHECK-NEXT: }; // Size: 424 bytes
// CHECK-NEXT: return MatchTable0;
// CHECK-NEXT: }
diff --git a/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td b/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
index d51bb87bb5896..1adf8f6af09cb 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
@@ -283,29 +283,29 @@ def HasC : Predicate<"Subtarget->hasC()"> { let RecomputePerFunction = 1; }
// R19O: // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]]
// R19O: // Label [[CASE_SELECT_NUM]]: @[[CASE_SELECT]]
// R19O-NEXT: GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ GIMT_Encode4([[GROUP:[0-9]+]]),
-// R19O-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// R19O-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// R19O-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
-// R19O-NEXT: GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
+// R19O-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// R19O-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
+// R19O-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
+// R19O-NEXT: GIM_RootCheckType3, /*Type*/GILLT_s32,
//
// R19C-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]),
//
-// R19O-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
-// R19O-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// R19O-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// R19O-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// R19N-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
// R19N-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SELECT),
// R19N-NEXT: // MIs[0] DstI[dst]
-// R19N-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// R19N-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// R19N-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// R19N-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// R19N-NEXT: // MIs[0] src1
-// R19N-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// R19N-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// R19N-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
+// R19N-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// R19N-NEXT: // MIs[0] complex_rr:src2a:src2b
-// R19N-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
+// R19N-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
//
// R19N-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_complex_rr),
// R19N-NEXT: // MIs[0] Operand 3
-// R19N-NEXT: GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
+// R19N-NEXT: GIM_RootCheckType3, /*Type*/GILLT_s32,
// R19C-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
// R19N-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
// R19C-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SELECT),
@@ -337,8 +337,8 @@ def HasC : Predicate<"Subtarget->hasC()"> { let RecomputePerFunction = 1; }
// R19C-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src5b
// R19C-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
// R19C-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::INSN3),
-// R19C-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
-// R19C-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src1
+// R19C-NEXT: GIR_RootToRootCopy0, // DstI[dst]
+// R19C-NEXT: GIR_RootToRootCopy1, // src1
// R19C-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2b
// R19C-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2a
// R19C-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
@@ -359,10 +359,10 @@ def HasC : Predicate<"Subtarget->hasC()"> { let RecomputePerFunction = 1; }
// EXTENDED: // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]]
// EXTENDED: // Label [[CASE_SELECT_NUM]]: @[[CASE_SELECT]]
// EXTENDED-NEXT: GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ GIMT_Encode4([[GROUP:[0-9]+]]),
-// EXTENDED-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_i32,
-// EXTENDED-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_i32,
-// EXTENDED-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_i32,
-// EXTENDED-NEXT: GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_i32,
+// EXTENDED-NEXT: GIM_RootCheckType0, /*Type*/GILLT_i32,
+// EXTENDED-NEXT: GIM_RootCheckType1, /*Type*/GILLT_i32,
+// EXTENDED-NEXT: GIM_RootCheckType2, /*Type*/GILLT_i32,
+// EXTENDED-NEXT: GIM_RootCheckType3, /*Type*/GILLT_i32,
def INSN3 : I<(outs GPR32:$dst),
(ins GPR32Op:$src1, GPR32:$src2a, GPR32:$src2b, GPR32:$scr), []>;
@@ -382,10 +382,10 @@ def : Pat<(select GPR32:$src1, (complex_rr GPR32:$src2a, GPR32:$src2b),
// R21O: // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]]
// R21O: // Label [[CASE_SELECT_NUM]]: @[[CASE_SELECT]]
// R21O-NEXT: GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ GIMT_Encode4([[GROUP:[0-9]+]]),
-// R21O-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// R21O-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// R21O-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
-// R21O-NEXT: GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
+// R21O-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// R21O-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
+// R21O-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
+// R21O-NEXT: GIM_RootCheckType3, /*Type*/GILLT_s32,
//
// R21C-NEXT: GIM_Try, /*On fail goto*//*Label [[PREV_NUM:[0-9]+]]*/ GIMT_Encode4([[PREV:[0-9]+]]), // Rule ID 20 //
// R21C-NOT: GIR_EraseRootFromParent_Done,
@@ -394,30 +394,30 @@ def : Pat<(select GPR32:$src1, (complex_rr GPR32:$src2a, GPR32:$src2b),
// R21C-NEXT: // Label [[PREV_NUM]]: @[[PREV]]
// R21C-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // Rule ID 22 //
//
-// R21O-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
-// R21O-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// R21O-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// R21O-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// R21N-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
// R21N-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SELECT),
// R21N-NEXT: // MIs[0] DstI[dst]
-// R21N-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// R21N-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// R21N-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// R21N-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// R21N-NEXT: // MIs[0] src1
-// R21N-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// R21N-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// R21N-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
+// R21N-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// R21N-NEXT: // MIs[0] src2
-// R21N-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
+// R21N-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
//
// R21O-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_frag),
// R21C-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_complex),
// R21N-NEXT: // MIs[0] src3
-// R21N-NEXT: GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
+// R21N-NEXT: GIM_RootCheckType3, /*Type*/GILLT_s32,
// R21C-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_complex),
// R21N-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_frag),
// R21C-NEXT: // (select:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src2, complex:{ *:[i32] }:$src3)<<P:Predicate_frag>> => (INSN2:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src3, complex:{ *:[i32] }:$src2)
// R21C-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::INSN2),
-// R21C-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
-// R21C-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src1
+// R21C-NEXT: GIR_RootToRootCopy0, // DstI[dst]
+// R21C-NEXT: GIR_RootToRootCopy1, // src1
// R21C-NEXT: GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1),
// R21C-NEXT: GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0),
// R21C-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0
@@ -441,10 +441,10 @@ def : Pat<(select GPR32:$src1, (complex_rr GPR32:$src2a, GPR32:$src2b),
// R20O: // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]]
// R20O: // Label [[CASE_SUB_NUM]]: @[[CASE_SUB]]
// R20O-NEXT: GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ GIMT_Encode4([[GROUP:[0-9]+]]),
-// R20O-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// R20O-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// R20O-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
-// R20O-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// R20O-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// R20O-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
+// R20O-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
+// R20O-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
//
// R20N: GIM_Try, /*On fail goto*//*Label [[PREV_NUM:[0-9]+]]*/ GIMT_Encode4([[PREV:[0-9]+]]), // Rule ID 22 //
// R20N: // Label [[PREV_NUM]]: @[[PREV]]
@@ -454,20 +454,20 @@ def : Pat<(select GPR32:$src1, (complex_rr GPR32:$src2a, GPR32:$src2b),
// R20N-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
// R20N-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SUB),
// R20N-NEXT: // MIs[0] DstI[dst]
-// R20N-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// R20N-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// R20N-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// R20N-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// R20N-NEXT: // MIs[0] src1
-// R20N-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
+// R20N-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
//
-// R20N-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// R20N-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// R20N-NEXT: // MIs[0] src2
-// R20N-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
-// R20O-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// R20N-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
+// R20O-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// R20C-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_complex),
// R20C-NEXT: // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src2) => (INSN1:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src2)
// R20C-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::INSN1),
-// R20C-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
-// R20C-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src1
+// R20C-NEXT: GIR_RootToRootCopy0, // DstI[dst]
+// R20C-NEXT: GIR_RootToRootCopy1, // src1
// R20C-NEXT: GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0),
// R20C-NEXT: GIR_RootConstrainSelectedInstOperands,
// R20C-NEXT: // GIR_Coverage, 21,
@@ -505,10 +505,10 @@ def : Pat<(frag GPR32:$src1, complex:$src2, complex:$src3),
// R00O: // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]]
// R00O: // Label [[CASE_SUB_NUM]]: @[[CASE_SUB]]
// R00O-NEXT: GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ GIMT_Encode4([[GROUP:[0-9]+]]),
-// R00O-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// R00O-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// R00O-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
-// R00O-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// R00O-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// R00O-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
+// R00O-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
+// R00O-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
//
// R00C: GIM_Try, /*On fail goto*//*Label [[PREV_NUM:[0-9]+]]*/ GIMT_Encode4([[PREV:[0-9]+]]), // Rule ID 21 //
// R00C: // Label [[PREV_NUM]]: @[[PREV]]
@@ -517,10 +517,10 @@ def : Pat<(frag GPR32:$src1, complex:$src2, complex:$src3),
// R00N-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
// R00N-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SUB),
// R00N-NEXT: // MIs[0] DstI[dst]
-// R00N-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// R00N-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// R00N-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// R00N-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// R00N-NEXT: // MIs[0] Operand 1
-// R00N-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
+// R00N-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
// R00C-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
// R00N-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
// R00C-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
@@ -534,7 +534,7 @@ def : Pat<(frag GPR32:$src1, complex:$src2, complex:$src3),
// R00N-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
// R00N-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// R00N-NEXT: // MIs[0] Operand 2
-// R00N-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
+// R00N-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
// R00O-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// R00O-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// R00C-NEXT: GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
@@ -554,7 +554,7 @@ def : Pat<(frag GPR32:$src1, complex:$src2, complex:$src3),
// R00C-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/2,
// R00C-NEXT: // (sub:{ *:[i32] } (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2), (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src3, GPR32:{ *:[i32] }:$src4)) => (INSNBOB:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src3, GPR32:{ *:[i32] }:$src4)
// R00C-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::INSNBOB),
-// R00C-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// R00C-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// R00C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
// R00C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
// R00C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src3
@@ -569,7 +569,7 @@ def : Pat<(frag GPR32:$src1, complex:$src2, complex:$src3),
// R00O-NEXT: GIM_Reject,
// R00O: // Label [[DEFAULT_NUM]]: @[[DEFAULT]]
// R00O-NEXT: GIM_Reject,
-// R00O-NEXT: }; // Size: 1930 bytes
+// R00O-NEXT: }; // Size: 1836 bytes
def INSNBOB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3, GPR32:$src4),
[(set GPR32:$dst,
@@ -591,24 +591,24 @@ def INSNBOB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3, G
// R01C-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
//
// R01O-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mytarget_nop),
-// R01O-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// R01O-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
-// R01O-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// R01O-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// R01O-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
+// R01O-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
//
// R01N-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
// R01N-NEXT: // MIs[0] DstI[dst]
-// R01N-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// R01N-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// R01N-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// R01N-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// R01N-NEXT: // MIs[0] Operand 1
// R01N-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mytarget_nop),
// R01N-NEXT: // MIs[0] src1
-// R01N-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
+// R01N-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
//
-// R01C-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// R01C-NEXT: GIM_RootCheckRegBankForClass2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// R01C-NEXT: // (intrinsic_wo_chain:{ *:[i32] } [[ID:[0-9]+]]:{ *:[iPTR] }, GPR32:{ *:[i32] }:$src1) => (MOV:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
// R01C-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MOV),
-// R01C-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
-// R01C-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // src1
+// R01C-NEXT: GIR_RootToRootCopy0, // DstI[dst]
+// R01C-NEXT: GIR_RootToRootCopy2, // src1
// R01C-NEXT: GIR_RootConstrainSelectedInstOperands,
// R01C-NEXT: // GIR_Coverage, 1,
// R01C-NEXT: GIR_EraseRootFromParent_Done,
@@ -629,11 +629,11 @@ def MOV : I<(outs GPR32:$dst), (ins GPR32:$src1),
// R02O: // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]]
// R02O: // Label [[CASE_XOR_NUM]]: @[[CASE_XOR]]
// R02O-NEXT: GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ GIMT_Encode4([[GROUP:[0-9]+]]),
-// R02O-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// R02O-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// R02O-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
-// R02O-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
-// R02O-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// R02O-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// R02O-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
+// R02O-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
+// R02O-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// R02O-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
//
// R02N: GIM_Try, /*On fail goto*//*Label [[PREV_NUM:[0-9]+]]*/ GIMT_Encode4([[PREV:[0-9]+]]), // Rule ID 1 //
// R02N: // Label [[PREV_NUM]]: @[[PREV]]
@@ -643,20 +643,20 @@ def MOV : I<(outs GPR32:$dst), (ins GPR32:$src1),
// R02N-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
// R02N-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_XOR),
// R02N-NEXT: // MIs[0] DstI[dst]
-// R02N-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// R02N-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// R02N-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// R02N-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// R02N-NEXT: // MIs[0] src1
-// R02N-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// R02N-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// R02N-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
+// R02N-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// R02N-NEXT: // MIs[0] Operand 2
-// R02N-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
+// R02N-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
//
// R02C-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 254,
// R02C-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -2:{ *:[i32] }) => (XORI:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
// R02C-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::XORI),
-// R02C-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// R02C-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// R02C-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
-// R02C-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src1
+// R02C-NEXT: GIR_RootToRootCopy1, // src1
// R02C-NEXT: GIR_RootConstrainSelectedInstOperands,
// R02C-NEXT: // GIR_Coverage, 2,
// R02C-NEXT: GIR_EraseRootFromParent_Done,
@@ -675,19 +675,19 @@ def XORI : I<(outs GPR32:$dst), (ins m1:$src2, GPR32:$src1),
// NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_XOR),
// NOOPT-NEXT: // MIs[0] DstI[dst]
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] src1
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] Operand 2
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
// NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 253,
// NOOPT-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -3:{ *:[i32] }) => (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::XOR),
-// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// NOOPT-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::R0),
-// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src1
+// NOOPT-NEXT: GIR_RootToRootCopy1, // src1
// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands,
// NOOPT-NEXT: // GIR_Coverage, 3,
// NOOPT-NEXT: GIR_EraseRootFromParent_Done,
@@ -703,20 +703,20 @@ def XOR : I<(outs GPR32:$dst), (ins Z:$src2, GPR32:$src1),
// NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_XOR),
// NOOPT-NEXT: // MIs[0] DstI[dst]
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] src1
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] Operand 2
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
// NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 252,
// NOOPT-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -4:{ *:[i32] }) => (XORlike:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::XORlike),
-// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// NOOPT-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// NOOPT-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
// NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::R0),
-// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src1
+// NOOPT-NEXT: GIR_RootToRootCopy1, // src1
// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands,
// NOOPT-NEXT: // GIR_Coverage, 4,
// NOOPT-NEXT: GIR_EraseRootFromParent_Done,
@@ -732,21 +732,21 @@ def XORlike : I<(outs GPR32:$dst), (ins m1Z:$src2, GPR32:$src1),
// NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_XOR),
// NOOPT-NEXT: // MIs[0] DstI[dst]
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] src1
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] Operand 2
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
// NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 251,
// NOOPT-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -5:{ *:[i32] }) => (XORManyDefaults:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::XORManyDefaults),
-// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// NOOPT-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// NOOPT-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
// NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::R0),
// NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::R0),
-// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src1
+// NOOPT-NEXT: GIR_RootToRootCopy1, // src1
// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands,
// NOOPT-NEXT: // GIR_Coverage, 5,
// NOOPT-NEXT: GIR_EraseRootFromParent_Done,
@@ -762,19 +762,19 @@ def XORManyDefaults : I<(outs GPR32:$dst), (ins m1Z:$src3, Z:$src2, GPR32:$src1)
// NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_XOR),
// NOOPT-NEXT: // MIs[0] DstI[dst]
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] src1
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] Operand 2
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
// NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 250,
// NOOPT-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -6:{ *:[i32] }) => (XORIb:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::XORIb),
-// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// NOOPT-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// NOOPT-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/13,
-// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src1
+// NOOPT-NEXT: GIR_RootToRootCopy1, // src1
// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands,
// NOOPT-NEXT: // GIR_Coverage, 6,
// NOOPT-NEXT: GIR_EraseRootFromParent_Done,
@@ -793,19 +793,19 @@ def XORIb : I<(outs GPR32:$dst), (ins mb:$src2, GPR32:$src1),
// NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_XOR),
// NOOPT-NEXT: // MIs[0] DstI[dst]
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] Wm
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] Operand 2
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
// NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
// NOOPT-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Wm, -1:{ *:[i32] }) => (ORN:{ *:[i32] } R0:{ *:[i32] }, GPR32:{ *:[i32] }:$Wm)
// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::ORN),
-// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// NOOPT-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::R0),
-// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // Wm
+// NOOPT-NEXT: GIR_RootToRootCopy1, // Wm
// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands,
// NOOPT-NEXT: // GIR_Coverage, 23,
// NOOPT-NEXT: GIR_EraseRootFromParent_Done,
@@ -820,10 +820,10 @@ def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>;
// NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL),
// NOOPT-NEXT: // MIs[0] DstI[dst]
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] Operand 1
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
// NOOPT-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
// NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
@@ -836,15 +836,15 @@ def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>;
// NOOPT-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] src3
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1,
// NOOPT-NEXT: // (mul:{ *:[i32] } (add:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2), GPR32:{ *:[i32] }:$src3) => (MULADD:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src3)
// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MULADD),
-// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// NOOPT-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
-// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // src3
+// NOOPT-NEXT: GIR_RootToRootCopy2, // src3
// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands,
// NOOPT-NEXT: // GIR_Coverage, 7,
// NOOPT-NEXT: GIR_EraseRootFromParent_Done,
@@ -856,13 +856,13 @@ def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>;
// NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL),
// NOOPT-NEXT: // MIs[0] DstI[dst]
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] src3
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] Operand 2
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
// NOOPT-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2,
// NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
@@ -877,10 +877,10 @@ def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>;
// NOOPT-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1,
// NOOPT-NEXT: // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src3, (add:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2)) => (MULADD:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src3)
// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MULADD),
-// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// NOOPT-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
-// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src3
+// NOOPT-NEXT: GIR_RootToRootCopy1, // src3
// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands,
// NOOPT-NEXT: // GIR_Coverage, 29,
// NOOPT-NEXT: GIR_EraseRootFromParent_Done,
@@ -893,24 +893,24 @@ def MULADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3),
//===- Test a simple pattern with a PatLeaf and a predicate. ---------===//
//
-// NOOPT-NEXT: /* 879 */ GIM_Try, /*On fail goto*//*Label 13*/ GIMT_Encode4(921), // Rule ID 24 //
-// NOOPT-NEXT: /* 884 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
-// NOOPT-NEXT: /* 887 */ GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SUB),
-// NOOPT-NEXT: /* 891 */ // MIs[0] DstI[dst]
-// NOOPT-NEXT: /* 891 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// NOOPT-NEXT: /* 894 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
-// NOOPT-NEXT: /* 898 */ // MIs[0] src1
-// NOOPT-NEXT: /* 898 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// NOOPT-NEXT: /* 901 */ GIM_CheckLeafOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_leaf),
-// NOOPT-NEXT: /* 906 */ // MIs[0] src2
-// NOOPT-NEXT: /* 906 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
-// NOOPT-NEXT: /* 909 */ GIM_CheckLeafOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_leaf),
-// NOOPT-NEXT: /* 914 */ // (sub:{ *:[i32] } GPR32:{ *:[i32] }<<P:Predicate_leaf>>:$src1, GPR32:{ *:[i32] }<<P:Predicate_leaf>>:$src2) => (INSN5:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2)
-// NOOPT-NEXT: /* 914 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::INSN5),
-// NOOPT-NEXT: /* 919 */ GIR_RootConstrainSelectedInstOperands,
-// NOOPT-NEXT: /* 920 */ // GIR_Coverage, 24,
-// NOOPT-NEXT: /* 920 */ GIR_Done,
-// NOOPT-NEXT: /* 921 */ // Label 13: @921
+// NOOPT-NEXT: /* 789 */ GIM_Try, /*On fail goto*//*Label 13*/ GIMT_Encode4(827), // Rule ID 24 //
+// NOOPT-NEXT: /* 794 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
+// NOOPT-NEXT: /* 797 */ GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SUB),
+// NOOPT-NEXT: /* 801 */ // MIs[0] DstI[dst]
+// NOOPT-NEXT: /* 801 */ GIM_RootCheckType0, /*Type*/GILLT_s32,
+// NOOPT-NEXT: /* 803 */ GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: /* 806 */ // MIs[0] src1
+// NOOPT-NEXT: /* 806 */ GIM_RootCheckType1, /*Type*/GILLT_s32,
+// NOOPT-NEXT: /* 808 */ GIM_CheckLeafOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_leaf),
+// NOOPT-NEXT: /* 813 */ // MIs[0] src2
+// NOOPT-NEXT: /* 813 */ GIM_RootCheckType2, /*Type*/GILLT_s32,
+// NOOPT-NEXT: /* 815 */ GIM_CheckLeafOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_leaf),
+// NOOPT-NEXT: /* 820 */ // (sub:{ *:[i32] } GPR32:{ *:[i32] }<<P:Predicate_leaf>>:$src1, GPR32:{ *:[i32] }<<P:Predicate_leaf>>:$src2) => (INSN5:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2)
+// NOOPT-NEXT: /* 820 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::INSN5),
+// NOOPT-NEXT: /* 825 */ GIR_RootConstrainSelectedInstOperands,
+// NOOPT-NEXT: /* 826 */ // GIR_Coverage, 24,
+// NOOPT-NEXT: /* 826 */ GIR_Done,
+// NOOPT-NEXT: /* 827 */ // Label 13: @827
def leaf: PatLeaf<(i32 GPR32:$src), [{ return true; // C++ code }]> {
let GISelLeafPredicateCode = [{ return true; }];
@@ -926,13 +926,13 @@ def : Pat<(sub leaf:$src1, leaf:$src2), (INSN5 GPR32:$src1, GPR32:$src2)>;
// NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_CONSTANT),
// NOOPT-NEXT: // MIs[0] DstI[dst]
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] Operand 1
// NOOPT-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, GIMT_Encode8(1),
// NOOPT-NEXT: // 1:{ *:[i32] } => (MOV1:{ *:[i32] })
// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MOV1),
-// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// NOOPT-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands,
// NOOPT-NEXT: // GIR_Coverage, 8,
// NOOPT-NEXT: GIR_EraseRootFromParent_Done,
@@ -947,13 +947,13 @@ def MOV1 : I<(outs GPR32:$dst), (ins), [(set GPR32:$dst, 1)]>;
// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_CONSTANT),
// NOOPT-NEXT: GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm8),
// NOOPT-NEXT: // MIs[0] DstI[dst]
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] Operand 1
// NOOPT-NEXT: // No operand predicates
// NOOPT-NEXT: // (imm:{ *:[i32] })<<P:Predicate_simm8>>:$imm => (MOVimm8:{ *:[i32] } (imm:{ *:[i32] }):$imm)
// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MOVimm8),
-// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// NOOPT-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// NOOPT-NEXT: GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands,
// NOOPT-NEXT: // GIR_Coverage, 9,
@@ -970,13 +970,13 @@ def MOVimm8 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, simm8:$i
// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_CONSTANT),
// NOOPT-NEXT: GIM_CheckAPIntImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_simm9),
// NOOPT-NEXT: // MIs[0] DstI[dst]
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] Operand 1
// NOOPT-NEXT: // No operand predicates
// NOOPT-NEXT: // (imm:{ *:[i32] })<<P:Predicate_simm9>>:$imm => (MOVimm9:{ *:[i32] } (imm:{ *:[i32] }):$imm)
// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MOVimm9),
-// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// NOOPT-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// NOOPT-NEXT: GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands,
// NOOPT-NEXT: // GIR_Coverage, 10,
@@ -993,13 +993,13 @@ def MOVimm9 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, simm9:$i
// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_CONSTANT),
// NOOPT-NEXT: GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_cimm8),
// NOOPT-NEXT: // MIs[0] DstI[dst]
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] Operand 1
// NOOPT-NEXT: // No operand predicates
// NOOPT-NEXT: // (imm:{ *:[i32] })<<P:Predicate_cimm8>><<X:cimm8_xform>>:$imm => (MOVcimm8:{ *:[i32] } (cimm8_xform:{ *:[i32] } (imm:{ *:[i32] }):$imm))
// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MOVcimm8),
-// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// NOOPT-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// NOOPT-NEXT: GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderImm), // imm
// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands,
// NOOPT-NEXT: // GIR_Coverage, 11,
@@ -1015,13 +1015,13 @@ def MOVcimm8 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, cimm8:$
// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
// NOOPT-NEXT: GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimmz),
// NOOPT-NEXT: // MIs[0] DstI[dst]
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
// NOOPT-NEXT: // MIs[0] Operand 1
// NOOPT-NEXT: // No operand predicates
// NOOPT-NEXT: // (fpimm:{ *:[f32] })<<P:Predicate_fpimmz>>:$imm => (MOVfpimmz:{ *:[f32] } (fpimm:{ *:[f32] }):$imm)
// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MOVfpimmz),
-// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// NOOPT-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// NOOPT-NEXT: GIR_CopyFConstantAsFPImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands,
// NOOPT-NEXT: // GIR_Coverage, 18,
@@ -1036,11 +1036,11 @@ def MOVcimm8 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, cimm8:$
// NOOPT-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
// NOOPT-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
// NOOPT-NEXT: // MIs[0] DstI[dst]
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] src1
// NOOPT-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // (ld:{ *:[i32] } GPR32:{ *:[i32] }:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD),
// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands,
@@ -1059,11 +1059,11 @@ def LOAD : I<(outs GPR32:$dst), (ins GPR32:$src1),
// NOOPT-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
// NOOPT-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
// NOOPT-NEXT: // MIs[0] DstI[dst]
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p0s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType0, /*Type*/GILLT_p0s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] src
// NOOPT-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // (ld:{ *:[i32] } GPR32:{ *:[i32] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD:{ *:[i32] } GPR32:{ *:[i32] }:$src)
// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD),
// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands,
@@ -1082,11 +1082,11 @@ def : Pat<(load GPR32:$src),
// NOOPT-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
// NOOPT-NEXT: GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
// NOOPT-NEXT: // MIs[0] DstI[dst]
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] src1
// NOOPT-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // (ld:{ *:[i32] } GPR32:{ *:[i32] }:$src1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (SEXTLOAD:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::SEXTLOAD),
// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands,
@@ -1103,14 +1103,14 @@ def SEXTLOAD : I<(outs GPR32:$dst), (ins GPR32:$src1),
// NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ADD),
// NOOPT-NEXT: // MIs[0] DstI[dst]
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] src1
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID)
+// NOOPT-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID)
// NOOPT-NEXT: // MIs[0] src2
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) => (ADD:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2)
// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ADD),
// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands,
@@ -1127,17 +1127,17 @@ def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2),
// NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ADD),
// NOOPT-NEXT: // MIs[0] DstI[dst]
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] src{{$}}
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] src{{$}}
// NOOPT-NEXT: GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
// NOOPT-NEXT: // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src) => (DOUBLE:{ *:[i32] } GPR32:{ *:[i32] }:$src)
// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::DOUBLE),
-// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
-// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src
+// NOOPT-NEXT: GIR_RootToRootCopy0, // DstI[dst]
+// NOOPT-NEXT: GIR_RootToRootCopy1, // src
// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands,
// NOOPT-NEXT: // GIR_Coverage, 15,
// NOOPT-NEXT: GIR_EraseRootFromParent_Done,
@@ -1157,12 +1157,12 @@ def DOUBLE : I<(outs GPR32:$dst), (ins GPR32:$src), [(set GPR32:$dst, (add GPR32
// NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ADD),
// NOOPT-NEXT: // MIs[0] DstI[samename]
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] samename
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
// NOOPT-NEXT: // MIs[0] othername
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
// NOOPT-NEXT: // (add:{ *:[i32] } i32:{ *:[i32] }:$samename, i32:{ *:[i32] }:$othername) => (InsnWithSpeciallyNamedDef:{ *:[i32] } i32:{ *:[i32] }:$samename, i32:{ *:[i32] }:$othername)
// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::InsnWithSpeciallyNamedDef),
// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands,
@@ -1180,12 +1180,12 @@ def : Pat<(add i32:$samename, i32:$othername),
// NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ADD),
// NOOPT-NEXT: // MIs[0] DstI[dst]
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] src1
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
// NOOPT-NEXT: // MIs[0] src2
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
// NOOPT-NEXT: // (add:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) => (ADD:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ADD),
// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands,
@@ -1202,19 +1202,19 @@ def : Pat<(add i32:$src1, i32:$src2),
// NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL),
// NOOPT-NEXT: // MIs[0] DstI[dst]
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] src1
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] src2
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) => (MUL:{ *:[i32] } GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src1)
// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MUL),
-// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
-// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // src2
-// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src1
+// NOOPT-NEXT: GIR_RootToRootCopy0, // DstI[dst]
+// NOOPT-NEXT: GIR_RootToRootCopy2, // src2
+// NOOPT-NEXT: GIR_RootToRootCopy1, // src1
// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands,
// NOOPT-NEXT: // GIR_Coverage, 16,
// NOOPT-NEXT: GIR_EraseRootFromParent_Done,
@@ -1231,11 +1231,11 @@ def MUL : I<(outs GPR32:$dst), (ins GPR32:$src2, GPR32:$src1),
// NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_BITCAST),
// NOOPT-NEXT: // MIs[0] DstI[dst]
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] src1
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID),
// NOOPT-NEXT: // (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$src1) => (COPY_TO_REGCLASS:{ *:[i32] } FPR32:{ *:[f32] }:$src1, GPR32:{ *:[i32] })
// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
// NOOPT-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(MyTarget::GPR32RegClassID),
@@ -1252,13 +1252,13 @@ def : Pat<(i32 (bitconvert FPR32:$src1)),
// NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_CONSTANT),
// NOOPT-NEXT: // MIs[0] DstI[dst]
-// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// NOOPT-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// NOOPT-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// NOOPT-NEXT: // MIs[0] Operand 1
// NOOPT-NEXT: // No operand predicates
// NOOPT-NEXT: // (imm:{ *:[i32] }):$imm => (MOVimm:{ *:[i32] } (imm:{ *:[i32] }):$imm)
// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MOVimm),
-// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// NOOPT-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// NOOPT-NEXT: GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands,
// NOOPT-NEXT: // GIR_Coverage, 17,
@@ -1288,5 +1288,5 @@ def BR : I<(outs), (ins unknown:$target),
[(br bb:$target)]>;
// NOOPT-NEXT: GIM_Reject,
-// NOOPT-NEXT: }; // Size: 1497 bytes
+// NOOPT-NEXT: }; // Size: 1343 bytes
// NOOPT-NEXT: return MatchTable0;
diff --git a/llvm/test/TableGen/GlobalISelEmitter/HwModes.td b/llvm/test/TableGen/GlobalISelEmitter/HwModes.td
index c671335557970..38b9eba1e99e7 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/HwModes.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/HwModes.td
@@ -138,11 +138,11 @@ class I<dag OOps, dag IOps, list<dag> Pat>
// CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
// CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
// CHECK-NEXT: // MIs[0] DstI[dst]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s64,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID),
// CHECK-NEXT: // MIs[0] src1
// CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID),
// CHECK-NEXT: // (ld:{ *:[i64] } GPR:{ *:[i64] }:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD:{ *:[i64] } GPR:{ *:[i64] }:$src1)
// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD),
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
@@ -155,11 +155,11 @@ class I<dag OOps, dag IOps, list<dag> Pat>
// CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
// CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
// CHECK-NEXT: // MIs[0] DstI[dst]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID),
// CHECK-NEXT: // MIs[0] src1
// CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID),
// CHECK-NEXT: // (ld:{ *:[i32] } GPR:{ *:[i32] }:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD:{ *:[i32] } GPR:{ *:[i32] }:$src1)
// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD),
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
@@ -178,11 +178,11 @@ def LOAD : I<(outs GPR:$dst), (ins GPR:$src1),
// CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
// CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
// CHECK-NEXT: // MIs[0] DstI[dst]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p0s64,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_p0s64,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID),
// CHECK-NEXT: // MIs[0] src
// CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID),
// CHECK-NEXT: // (ld:{ *:[i64] } GPR:{ *:[i64] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD:{ *:[i64] } GPR:{ *:[i64] }:$src)
// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD),
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
@@ -195,11 +195,11 @@ def LOAD : I<(outs GPR:$dst), (ins GPR:$src1),
// CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
// CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
// CHECK-NEXT: // MIs[0] DstI[dst]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p0s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_p0s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID),
// CHECK-NEXT: // MIs[0] src
// CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID),
// CHECK-NEXT: // (ld:{ *:[i32] } GPR:{ *:[i32] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD:{ *:[i32] } GPR:{ *:[i32] }:$src)
// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD),
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
diff --git a/llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizer.td b/llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizer.td
index 6ac6703991c2d..83674a3ab6043 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizer.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizer.td
@@ -11,11 +11,11 @@ def LOAD32 : I<(outs GPR8:$dst), (ins GPR32:$src), []>;
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[L1_ID:[0-9]+]]*/ GIMT_Encode4([[L1_AT:[0-9]+]]),
// CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
// CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR8RegClassID),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR8RegClassID),
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[L2_ID:[0-9]+]]*/ GIMT_Encode4([[L2_AT:[0-9]+]]),
// CHECK-NEXT: // MIs[0] src
// CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/8,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR8RegClassID),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR8RegClassID),
// CHECK-NEXT: // (ld:{ *:[i8] } GPR8:{ *:[i8] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD8:{ *:[i8] } GPR8:{ *:[i8] }:$src)
// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD8),
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
@@ -25,7 +25,7 @@ def LOAD32 : I<(outs GPR8:$dst), (ins GPR32:$src), []>;
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[L3_ID:[0-9]+]]*/ GIMT_Encode4([[L3_AT:[0-9]+]]),
// CHECK-NEXT: // MIs[0] src
// CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: // (ld:{ *:[i8] } GPR32:{ *:[i32] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD32:{ *:[i8] } GPR32:{ *:[i32] }:$src)
// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD32),
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
@@ -49,7 +49,7 @@ def LOAD16Imm : I<(outs GPR16:$dst), (ins GPR16:$src), []>;
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[L1_ID:[0-9]+]]*/ GIMT_Encode4([[L1_AT:[0-9]+]]),
// CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
// CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR16RegClassID),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR16RegClassID),
// CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/16,
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[L2_ID:[0-9]+]]*/ GIMT_Encode4([[L2_AT:[0-9]+]]),
// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
@@ -61,7 +61,7 @@ def LOAD16Imm : I<(outs GPR16:$dst), (ins GPR16:$src), []>;
// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1,
// CHECK-NEXT: // (ld:{ *:[i16] } (add:{ *:[i16] } GPR16:{ *:[i16] }:$src, 10:{ *:[i16] }))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD16Imm:{ *:[i16] } GPR16:{ *:[i16] }:$src)
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::LOAD16Imm),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
@@ -69,7 +69,7 @@ def LOAD16Imm : I<(outs GPR16:$dst), (ins GPR16:$src), []>;
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
// CHECK-NEXT: // Label [[L2_ID]]: @[[L2_AT]]
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[L3_ID:[0-9]+]]*/ GIMT_Encode4([[L3_AT:[0-9]+]]),
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR16RegClassID),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR16RegClassID),
// CHECK-NEXT: // (ld:{ *:[i16] } GPR16:{ *:[i16] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD16:{ *:[i16] } GPR16:{ *:[i16] }:$src)
// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD16),
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
diff --git a/llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizerRecursion.td b/llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizerRecursion.td
index 0beda69a843c4..a169bdcfed2d3 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizerRecursion.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizerRecursion.td
@@ -52,153 +52,153 @@ def : Pat<(i16 (load (add GPR16_B:$src, 10))),
// CHECK: const uint8_t *MyTargetInstructionSelector::getMatchTable() const {
// CHECK-NEXT: constexpr static uint8_t MatchTable0[] = {
-// CHECK-NEXT: /* 0 */ GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(377),
+// CHECK-NEXT: /* 0 */ GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(361),
// CHECK-NEXT: /* 5 */ GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_LOAD),
-// CHECK-NEXT: /* 9 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 3*/ GIMT_Encode4(376),
+// CHECK-NEXT: /* 9 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 3*/ GIMT_Encode4(360),
// CHECK-NEXT: /* 20 */ /*GILLT_s8*//*Label 1*/ GIMT_Encode4(28),
-// CHECK-NEXT: /* 24 */ /*GILLT_s16*//*Label 2*/ GIMT_Encode4(202),
+// CHECK-NEXT: /* 24 */ /*GILLT_s16*//*Label 2*/ GIMT_Encode4(194),
// CHECK-NEXT: /* 28 */ // Label 1: @28
-// CHECK-NEXT: /* 28 */ GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(201),
+// CHECK-NEXT: /* 28 */ GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(193),
// CHECK-NEXT: /* 33 */ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
// CHECK-NEXT: /* 36 */ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
-// CHECK-NEXT: /* 40 */ GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(96), // Rule ID 2 //
-// CHECK-NEXT: /* 45 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR8_ARegClassID),
-// CHECK-NEXT: /* 49 */ // MIs[0] Operand 1
-// CHECK-NEXT: /* 49 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/8,
-// CHECK-NEXT: /* 53 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
-// CHECK-NEXT: /* 57 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
-// CHECK-NEXT: /* 61 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s8,
-// CHECK-NEXT: /* 65 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8,
-// CHECK-NEXT: /* 69 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR8_ARegClassID),
-// CHECK-NEXT: /* 74 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 10,
-// CHECK-NEXT: /* 78 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
-// CHECK-NEXT: /* 80 */ // (ld:{ *:[i8] } (add:{ *:[i8] } GPR8_A:{ *:[i8] }:$src, 10:{ *:[i8] }))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD8Imm_A:{ *:[i8] } GPR8_A:{ *:[i8] }:$src)
-// CHECK-NEXT: /* 80 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::LOAD8Imm_A),
-// CHECK-NEXT: /* 83 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
-// CHECK-NEXT: /* 85 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
-// CHECK-NEXT: /* 89 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
-// CHECK-NEXT: /* 94 */ GIR_RootConstrainSelectedInstOperands,
-// CHECK-NEXT: /* 95 */ // GIR_Coverage, 2,
-// CHECK-NEXT: /* 95 */ GIR_EraseRootFromParent_Done,
-// CHECK-NEXT: /* 96 */ // Label 5: @96
-// CHECK-NEXT: /* 96 */ GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(152), // Rule ID 3 //
-// CHECK-NEXT: /* 101 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR8_BRegClassID),
-// CHECK-NEXT: /* 105 */ // MIs[0] Operand 1
-// CHECK-NEXT: /* 105 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/8,
-// CHECK-NEXT: /* 109 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
-// CHECK-NEXT: /* 113 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
-// CHECK-NEXT: /* 117 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s8,
-// CHECK-NEXT: /* 121 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8,
-// CHECK-NEXT: /* 125 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR8_BRegClassID),
-// CHECK-NEXT: /* 130 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 10,
-// CHECK-NEXT: /* 134 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
-// CHECK-NEXT: /* 136 */ // (ld:{ *:[i8] } (add:{ *:[i8] } GPR8_B:{ *:[i8] }:$src, 10:{ *:[i8] }))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD8Imm_B:{ *:[i8] } GPR8_B:{ *:[i8] }:$src)
-// CHECK-NEXT: /* 136 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::LOAD8Imm_B),
-// CHECK-NEXT: /* 139 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
-// CHECK-NEXT: /* 141 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
-// CHECK-NEXT: /* 145 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
-// CHECK-NEXT: /* 150 */ GIR_RootConstrainSelectedInstOperands,
-// CHECK-NEXT: /* 151 */ // GIR_Coverage, 3,
-// CHECK-NEXT: /* 151 */ GIR_EraseRootFromParent_Done,
-// CHECK-NEXT: /* 152 */ // Label 6: @152
-// CHECK-NEXT: /* 152 */ GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(176), // Rule ID 0 //
-// CHECK-NEXT: /* 157 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR8_ARegClassID),
-// CHECK-NEXT: /* 161 */ // MIs[0] src
-// CHECK-NEXT: /* 161 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/8,
-// CHECK-NEXT: /* 165 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR8_ARegClassID),
-// CHECK-NEXT: /* 169 */ // (ld:{ *:[i8] } GPR8_A:{ *:[i8] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD8_A:{ *:[i8] } GPR8_A:{ *:[i8] }:$src)
-// CHECK-NEXT: /* 169 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD8_A),
-// CHECK-NEXT: /* 174 */ GIR_RootConstrainSelectedInstOperands,
-// CHECK-NEXT: /* 175 */ // GIR_Coverage, 0,
-// CHECK-NEXT: /* 175 */ GIR_Done,
-// CHECK-NEXT: /* 176 */ // Label 7: @176
-// CHECK-NEXT: /* 176 */ GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(200), // Rule ID 1 //
-// CHECK-NEXT: /* 181 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR8_BRegClassID),
-// CHECK-NEXT: /* 185 */ // MIs[0] src
-// CHECK-NEXT: /* 185 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/8,
-// CHECK-NEXT: /* 189 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR8_BRegClassID),
-// CHECK-NEXT: /* 193 */ // (ld:{ *:[i8] } GPR8_B:{ *:[i8] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD8_B:{ *:[i8] } GPR8_B:{ *:[i8] }:$src)
-// CHECK-NEXT: /* 193 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD8_B),
-// CHECK-NEXT: /* 198 */ GIR_RootConstrainSelectedInstOperands,
-// CHECK-NEXT: /* 199 */ // GIR_Coverage, 1,
-// CHECK-NEXT: /* 199 */ GIR_Done,
-// CHECK-NEXT: /* 200 */ // Label 8: @200
-// CHECK-NEXT: /* 200 */ GIM_Reject,
-// CHECK-NEXT: /* 201 */ // Label 4: @201
-// CHECK-NEXT: /* 201 */ GIM_Reject,
-// CHECK-NEXT: /* 202 */ // Label 2: @202
-// CHECK-NEXT: /* 202 */ GIM_Try, /*On fail goto*//*Label 9*/ GIMT_Encode4(375),
-// CHECK-NEXT: /* 207 */ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
-// CHECK-NEXT: /* 210 */ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
-// CHECK-NEXT: /* 214 */ GIM_Try, /*On fail goto*//*Label 10*/ GIMT_Encode4(270), // Rule ID 6 //
-// CHECK-NEXT: /* 219 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR16_ARegClassID),
-// CHECK-NEXT: /* 223 */ // MIs[0] Operand 1
-// CHECK-NEXT: /* 223 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/16,
-// CHECK-NEXT: /* 227 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
-// CHECK-NEXT: /* 231 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
-// CHECK-NEXT: /* 235 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
-// CHECK-NEXT: /* 239 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
-// CHECK-NEXT: /* 243 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR16_ARegClassID),
-// CHECK-NEXT: /* 248 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 10,
-// CHECK-NEXT: /* 252 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
-// CHECK-NEXT: /* 254 */ // (ld:{ *:[i16] } (add:{ *:[i16] } GPR16_A:{ *:[i16] }:$src, 10:{ *:[i16] }))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD16Imm_A:{ *:[i16] } GPR16_A:{ *:[i16] }:$src)
-// CHECK-NEXT: /* 254 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::LOAD16Imm_A),
-// CHECK-NEXT: /* 257 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
-// CHECK-NEXT: /* 259 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
-// CHECK-NEXT: /* 263 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
-// CHECK-NEXT: /* 268 */ GIR_RootConstrainSelectedInstOperands,
-// CHECK-NEXT: /* 269 */ // GIR_Coverage, 6,
-// CHECK-NEXT: /* 269 */ GIR_EraseRootFromParent_Done,
-// CHECK-NEXT: /* 270 */ // Label 10: @270
-// CHECK-NEXT: /* 270 */ GIM_Try, /*On fail goto*//*Label 11*/ GIMT_Encode4(326), // Rule ID 7 //
-// CHECK-NEXT: /* 275 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR16_BRegClassID),
-// CHECK-NEXT: /* 279 */ // MIs[0] Operand 1
-// CHECK-NEXT: /* 279 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/16,
-// CHECK-NEXT: /* 283 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
-// CHECK-NEXT: /* 287 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
-// CHECK-NEXT: /* 291 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
-// CHECK-NEXT: /* 295 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
-// CHECK-NEXT: /* 299 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR16_BRegClassID),
-// CHECK-NEXT: /* 304 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 10,
-// CHECK-NEXT: /* 308 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
-// CHECK-NEXT: /* 310 */ // (ld:{ *:[i16] } (add:{ *:[i16] } GPR16_B:{ *:[i16] }:$src, 10:{ *:[i16] }))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD16Imm_B:{ *:[i16] } GPR16_B:{ *:[i16] }:$src)
-// CHECK-NEXT: /* 310 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::LOAD16Imm_B),
-// CHECK-NEXT: /* 313 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
-// CHECK-NEXT: /* 315 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
-// CHECK-NEXT: /* 319 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
-// CHECK-NEXT: /* 324 */ GIR_RootConstrainSelectedInstOperands,
-// CHECK-NEXT: /* 325 */ // GIR_Coverage, 7,
-// CHECK-NEXT: /* 325 */ GIR_EraseRootFromParent_Done,
-// CHECK-NEXT: /* 326 */ // Label 11: @326
-// CHECK-NEXT: /* 326 */ GIM_Try, /*On fail goto*//*Label 12*/ GIMT_Encode4(350), // Rule ID 4 //
-// CHECK-NEXT: /* 331 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR16_ARegClassID),
-// CHECK-NEXT: /* 335 */ // MIs[0] src
-// CHECK-NEXT: /* 335 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/16,
-// CHECK-NEXT: /* 339 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR16_ARegClassID),
-// CHECK-NEXT: /* 343 */ // (ld:{ *:[i16] } GPR16_A:{ *:[i16] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD16_A:{ *:[i16] } GPR16_A:{ *:[i16] }:$src)
-// CHECK-NEXT: /* 343 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD16_A),
-// CHECK-NEXT: /* 348 */ GIR_RootConstrainSelectedInstOperands,
-// CHECK-NEXT: /* 349 */ // GIR_Coverage, 4,
-// CHECK-NEXT: /* 349 */ GIR_Done,
-// CHECK-NEXT: /* 350 */ // Label 12: @350
-// CHECK-NEXT: /* 350 */ GIM_Try, /*On fail goto*//*Label 13*/ GIMT_Encode4(374), // Rule ID 5 //
-// CHECK-NEXT: /* 355 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR16_BRegClassID),
-// CHECK-NEXT: /* 359 */ // MIs[0] src
-// CHECK-NEXT: /* 359 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/16,
-// CHECK-NEXT: /* 363 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR16_BRegClassID),
-// CHECK-NEXT: /* 367 */ // (ld:{ *:[i16] } GPR16_B:{ *:[i16] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD16_B:{ *:[i16] } GPR16_B:{ *:[i16] }:$src)
-// CHECK-NEXT: /* 367 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD16_B),
-// CHECK-NEXT: /* 372 */ GIR_RootConstrainSelectedInstOperands,
-// CHECK-NEXT: /* 373 */ // GIR_Coverage, 5,
-// CHECK-NEXT: /* 373 */ GIR_Done,
-// CHECK-NEXT: /* 374 */ // Label 13: @374
-// CHECK-NEXT: /* 374 */ GIM_Reject,
-// CHECK-NEXT: /* 375 */ // Label 9: @375
-// CHECK-NEXT: /* 375 */ GIM_Reject,
-// CHECK-NEXT: /* 376 */ // Label 3: @376
-// CHECK-NEXT: /* 376 */ GIM_Reject,
-// CHECK-NEXT: /* 377 */ // Label 0: @377
-// CHECK-NEXT: /* 377 */ GIM_Reject,
-// CHECK-NEXT: /* 378 */ }; // Size: 378 bytes
+// CHECK-NEXT: /* 40 */ GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(94), // Rule ID 2 //
+// CHECK-NEXT: /* 45 */ GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR8_ARegClassID),
+// CHECK-NEXT: /* 48 */ // MIs[0] Operand 1
+// CHECK-NEXT: /* 48 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/8,
+// CHECK-NEXT: /* 52 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+// CHECK-NEXT: /* 56 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
+// CHECK-NEXT: /* 60 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s8,
+// CHECK-NEXT: /* 64 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8,
+// CHECK-NEXT: /* 68 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR8_ARegClassID),
+// CHECK-NEXT: /* 73 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 10,
+// CHECK-NEXT: /* 77 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
+// CHECK-NEXT: /* 79 */ // (ld:{ *:[i8] } (add:{ *:[i8] } GPR8_A:{ *:[i8] }:$src, 10:{ *:[i8] }))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD8Imm_A:{ *:[i8] } GPR8_A:{ *:[i8] }:$src)
+// CHECK-NEXT: /* 79 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::LOAD8Imm_A),
+// CHECK-NEXT: /* 82 */ GIR_RootToRootCopy0, // DstI[dst]
+// CHECK-NEXT: /* 83 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
+// CHECK-NEXT: /* 87 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
+// CHECK-NEXT: /* 92 */ GIR_RootConstrainSelectedInstOperands,
+// CHECK-NEXT: /* 93 */ // GIR_Coverage, 2,
+// CHECK-NEXT: /* 93 */ GIR_EraseRootFromParent_Done,
+// CHECK-NEXT: /* 94 */ // Label 5: @94
+// CHECK-NEXT: /* 94 */ GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(148), // Rule ID 3 //
+// CHECK-NEXT: /* 99 */ GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR8_BRegClassID),
+// CHECK-NEXT: /* 102 */ // MIs[0] Operand 1
+// CHECK-NEXT: /* 102 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/8,
+// CHECK-NEXT: /* 106 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+// CHECK-NEXT: /* 110 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
+// CHECK-NEXT: /* 114 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s8,
+// CHECK-NEXT: /* 118 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8,
+// CHECK-NEXT: /* 122 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR8_BRegClassID),
+// CHECK-NEXT: /* 127 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 10,
+// CHECK-NEXT: /* 131 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
+// CHECK-NEXT: /* 133 */ // (ld:{ *:[i8] } (add:{ *:[i8] } GPR8_B:{ *:[i8] }:$src, 10:{ *:[i8] }))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD8Imm_B:{ *:[i8] } GPR8_B:{ *:[i8] }:$src)
+// CHECK-NEXT: /* 133 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::LOAD8Imm_B),
+// CHECK-NEXT: /* 136 */ GIR_RootToRootCopy0, // DstI[dst]
+// CHECK-NEXT: /* 137 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
+// CHECK-NEXT: /* 141 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
+// CHECK-NEXT: /* 146 */ GIR_RootConstrainSelectedInstOperands,
+// CHECK-NEXT: /* 147 */ // GIR_Coverage, 3,
+// CHECK-NEXT: /* 147 */ GIR_EraseRootFromParent_Done,
+// CHECK-NEXT: /* 148 */ // Label 6: @148
+// CHECK-NEXT: /* 148 */ GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(170), // Rule ID 0 //
+// CHECK-NEXT: /* 153 */ GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR8_ARegClassID),
+// CHECK-NEXT: /* 156 */ // MIs[0] src
+// CHECK-NEXT: /* 156 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/8,
+// CHECK-NEXT: /* 160 */ GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR8_ARegClassID),
+// CHECK-NEXT: /* 163 */ // (ld:{ *:[i8] } GPR8_A:{ *:[i8] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD8_A:{ *:[i8] } GPR8_A:{ *:[i8] }:$src)
+// CHECK-NEXT: /* 163 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD8_A),
+// CHECK-NEXT: /* 168 */ GIR_RootConstrainSelectedInstOperands,
+// CHECK-NEXT: /* 169 */ // GIR_Coverage, 0,
+// CHECK-NEXT: /* 169 */ GIR_Done,
+// CHECK-NEXT: /* 170 */ // Label 7: @170
+// CHECK-NEXT: /* 170 */ GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(192), // Rule ID 1 //
+// CHECK-NEXT: /* 175 */ GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR8_BRegClassID),
+// CHECK-NEXT: /* 178 */ // MIs[0] src
+// CHECK-NEXT: /* 178 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/8,
+// CHECK-NEXT: /* 182 */ GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR8_BRegClassID),
+// CHECK-NEXT: /* 185 */ // (ld:{ *:[i8] } GPR8_B:{ *:[i8] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD8_B:{ *:[i8] } GPR8_B:{ *:[i8] }:$src)
+// CHECK-NEXT: /* 185 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD8_B),
+// CHECK-NEXT: /* 190 */ GIR_RootConstrainSelectedInstOperands,
+// CHECK-NEXT: /* 191 */ // GIR_Coverage, 1,
+// CHECK-NEXT: /* 191 */ GIR_Done,
+// CHECK-NEXT: /* 192 */ // Label 8: @192
+// CHECK-NEXT: /* 192 */ GIM_Reject,
+// CHECK-NEXT: /* 193 */ // Label 4: @193
+// CHECK-NEXT: /* 193 */ GIM_Reject,
+// CHECK-NEXT: /* 194 */ // Label 2: @194
+// CHECK-NEXT: /* 194 */ GIM_Try, /*On fail goto*//*Label 9*/ GIMT_Encode4(359),
+// CHECK-NEXT: /* 199 */ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
+// CHECK-NEXT: /* 202 */ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+// CHECK-NEXT: /* 206 */ GIM_Try, /*On fail goto*//*Label 10*/ GIMT_Encode4(260), // Rule ID 6 //
+// CHECK-NEXT: /* 211 */ GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR16_ARegClassID),
+// CHECK-NEXT: /* 214 */ // MIs[0] Operand 1
+// CHECK-NEXT: /* 214 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/16,
+// CHECK-NEXT: /* 218 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+// CHECK-NEXT: /* 222 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
+// CHECK-NEXT: /* 226 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
+// CHECK-NEXT: /* 230 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
+// CHECK-NEXT: /* 234 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR16_ARegClassID),
+// CHECK-NEXT: /* 239 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 10,
+// CHECK-NEXT: /* 243 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
+// CHECK-NEXT: /* 245 */ // (ld:{ *:[i16] } (add:{ *:[i16] } GPR16_A:{ *:[i16] }:$src, 10:{ *:[i16] }))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD16Imm_A:{ *:[i16] } GPR16_A:{ *:[i16] }:$src)
+// CHECK-NEXT: /* 245 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::LOAD16Imm_A),
+// CHECK-NEXT: /* 248 */ GIR_RootToRootCopy0, // DstI[dst]
+// CHECK-NEXT: /* 249 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
+// CHECK-NEXT: /* 253 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
+// CHECK-NEXT: /* 258 */ GIR_RootConstrainSelectedInstOperands,
+// CHECK-NEXT: /* 259 */ // GIR_Coverage, 6,
+// CHECK-NEXT: /* 259 */ GIR_EraseRootFromParent_Done,
+// CHECK-NEXT: /* 260 */ // Label 10: @260
+// CHECK-NEXT: /* 260 */ GIM_Try, /*On fail goto*//*Label 11*/ GIMT_Encode4(314), // Rule ID 7 //
+// CHECK-NEXT: /* 265 */ GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR16_BRegClassID),
+// CHECK-NEXT: /* 268 */ // MIs[0] Operand 1
+// CHECK-NEXT: /* 268 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/16,
+// CHECK-NEXT: /* 272 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+// CHECK-NEXT: /* 276 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
+// CHECK-NEXT: /* 280 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
+// CHECK-NEXT: /* 284 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
+// CHECK-NEXT: /* 288 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR16_BRegClassID),
+// CHECK-NEXT: /* 293 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 10,
+// CHECK-NEXT: /* 297 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
+// CHECK-NEXT: /* 299 */ // (ld:{ *:[i16] } (add:{ *:[i16] } GPR16_B:{ *:[i16] }:$src, 10:{ *:[i16] }))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD16Imm_B:{ *:[i16] } GPR16_B:{ *:[i16] }:$src)
+// CHECK-NEXT: /* 299 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::LOAD16Imm_B),
+// CHECK-NEXT: /* 302 */ GIR_RootToRootCopy0, // DstI[dst]
+// CHECK-NEXT: /* 303 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
+// CHECK-NEXT: /* 307 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
+// CHECK-NEXT: /* 312 */ GIR_RootConstrainSelectedInstOperands,
+// CHECK-NEXT: /* 313 */ // GIR_Coverage, 7,
+// CHECK-NEXT: /* 313 */ GIR_EraseRootFromParent_Done,
+// CHECK-NEXT: /* 314 */ // Label 11: @314
+// CHECK-NEXT: /* 314 */ GIM_Try, /*On fail goto*//*Label 12*/ GIMT_Encode4(336), // Rule ID 4 //
+// CHECK-NEXT: /* 319 */ GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR16_ARegClassID),
+// CHECK-NEXT: /* 322 */ // MIs[0] src
+// CHECK-NEXT: /* 322 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/16,
+// CHECK-NEXT: /* 326 */ GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR16_ARegClassID),
+// CHECK-NEXT: /* 329 */ // (ld:{ *:[i16] } GPR16_A:{ *:[i16] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD16_A:{ *:[i16] } GPR16_A:{ *:[i16] }:$src)
+// CHECK-NEXT: /* 329 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD16_A),
+// CHECK-NEXT: /* 334 */ GIR_RootConstrainSelectedInstOperands,
+// CHECK-NEXT: /* 335 */ // GIR_Coverage, 4,
+// CHECK-NEXT: /* 335 */ GIR_Done,
+// CHECK-NEXT: /* 336 */ // Label 12: @336
+// CHECK-NEXT: /* 336 */ GIM_Try, /*On fail goto*//*Label 13*/ GIMT_Encode4(358), // Rule ID 5 //
+// CHECK-NEXT: /* 341 */ GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR16_BRegClassID),
+// CHECK-NEXT: /* 344 */ // MIs[0] src
+// CHECK-NEXT: /* 344 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/16,
+// CHECK-NEXT: /* 348 */ GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR16_BRegClassID),
+// CHECK-NEXT: /* 351 */ // (ld:{ *:[i16] } GPR16_B:{ *:[i16] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD16_B:{ *:[i16] } GPR16_B:{ *:[i16] }:$src)
+// CHECK-NEXT: /* 351 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD16_B),
+// CHECK-NEXT: /* 356 */ GIR_RootConstrainSelectedInstOperands,
+// CHECK-NEXT: /* 357 */ // GIR_Coverage, 5,
+// CHECK-NEXT: /* 357 */ GIR_Done,
+// CHECK-NEXT: /* 358 */ // Label 13: @358
+// CHECK-NEXT: /* 358 */ GIM_Reject,
+// CHECK-NEXT: /* 359 */ // Label 9: @359
+// CHECK-NEXT: /* 359 */ GIM_Reject,
+// CHECK-NEXT: /* 360 */ // Label 3: @360
+// CHECK-NEXT: /* 360 */ GIM_Reject,
+// CHECK-NEXT: /* 361 */ // Label 0: @361
+// CHECK-NEXT: /* 361 */ GIM_Reject,
+// CHECK-NEXT: /* 362 */ }; // Size: 362 bytes
// CHECK-NEXT: return MatchTable0;
// CHECK-NEXT: }
diff --git a/llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizerSameOperand-invalid.td b/llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizerSameOperand-invalid.td
index 1ecee0a4c2d83..354d7dda5ab82 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizerSameOperand-invalid.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizerSameOperand-invalid.td
@@ -5,14 +5,14 @@ include "GlobalISelEmitterCommon.td"
def InstTwoOperands : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32:$src2), []>;
-// CHECK: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(234),
+// CHECK: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(223),
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SELECT),
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(202),
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
-// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(114), // Rule ID 1 //
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(196),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(109), // Rule ID 1 //
// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
@@ -32,15 +32,15 @@ def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32:
// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/2,
// CHECK-NEXT: // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$cond, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2), GPR32:{ *:[i32] }:$src2) => (InstThreeOperands:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2)
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::InstThreeOperands),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // cond
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
// CHECK-NEXT: // GIR_Coverage, 1,
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
-// CHECK-NEXT: // Label 2: @114
-// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(201), // Rule ID 2 //
+// CHECK-NEXT: // Label 2: @109
+// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(195), // Rule ID 2 //
// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
@@ -60,30 +60,30 @@ def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32:
// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/2,
// CHECK-NEXT: // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$cond, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2), GPR32:{ *:[i32] }:$src2) => (InstThreeOperands:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2)
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::InstThreeOperands),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // cond
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
// CHECK-NEXT: // GIR_Coverage, 2,
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
-// CHECK-NEXT: // Label 3: @201
+// CHECK-NEXT: // Label 3: @195
// CHECK-NEXT: GIM_Reject,
-// CHECK-NEXT: // Label 1: @202
-// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(233), // Rule ID 0 //
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: // Label 1: @196
+// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(222), // Rule ID 0 //
+// CHECK-NEXT: GIM_RootCheckType3, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass3, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) => (InstThreeOperands:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2)
// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::InstThreeOperands),
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
// CHECK-NEXT: // GIR_Coverage, 0,
// CHECK-NEXT: GIR_Done,
-// CHECK-NEXT: // Label 4: @233
+// CHECK-NEXT: // Label 4: @222
// CHECK-NEXT: GIM_Reject,
-// CHECK-NEXT: // Label 0: @234
+// CHECK-NEXT: // Label 0: @223
// CHECK-NEXT: GIM_Reject,
def : Pat<(i32 (select GPR32:$cond, GPR32:$src1, GPR32:$src2)),
(InstThreeOperands GPR32:$cond, GPR32:$src1, GPR32:$src2)>;
diff --git a/llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizerSameOperand.td b/llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizerSameOperand.td
index c6ca9b7fbed5d..d6fef27436481 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizerSameOperand.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizerSameOperand.td
@@ -9,7 +9,7 @@ def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32:
// Make sure the GIM_CheckIsSameOperand check is not hoisted into the common header group
// CHECK: GIM_Try, /*On fail goto*//*Label 1*/
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NOT: GIM_CheckIsSameOperand
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/
// CHECK: GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/1,
diff --git a/llvm/test/TableGen/GlobalISelEmitter/OverloadedPtr.td b/llvm/test/TableGen/GlobalISelEmitter/OverloadedPtr.td
index 43a121f94bd6c..ef3f3f689b232 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/OverloadedPtr.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/OverloadedPtr.td
@@ -12,13 +12,13 @@ let TargetPrefix = "mytarget" in {
// Check that iPTR in the destination DAG doesn't prevent the pattern from being imported.
-// CHECK: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
+// CHECK: GIM_RootCheckType0, /*Type*/GILLT_s32,
// CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
// CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: // MIs[0] src1
// CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID),
// CHECK-NEXT: // (ld:{ *:[i32] } GPR:{ *:[iPTR] }:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (ANYLOAD:{ *:[i32] } GPR:{ *:[iPTR] }:$src1)
// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ANYLOAD),
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
@@ -34,11 +34,11 @@ let hasSideEffects = 1 in {
// GIM_CheckPointerToAny rather than a GIM_CheckType.
//
// CHECK: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mytarget_anyptr),
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: // MIs[0] src
// CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_frag_anyptr),
// CHECK-NEXT: // (intrinsic_w_chain:{ *:[i32] } {{[0-9]+}}:{ *:[iPTR] }, GPR32:{ *:[i32] }:$src)<<P:Predicate_frag_anyptr>> => (ANYLOAD:{ *:[i32] } GPR32:{ *:[i32] }:$src)
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::ANYLOAD),
diff --git a/llvm/test/TableGen/GlobalISelEmitter/RegSequence.td b/llvm/test/TableGen/GlobalISelEmitter/RegSequence.td
index 0567c876cfe16..2bb38e392e9c0 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/RegSequence.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/RegSequence.td
@@ -33,11 +33,11 @@ def SUBSOME_INSN : I<(outs SRegs:$dst), (ins SOP:$src), []>;
// CHECK: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SEXT),
// CHECK-NEXT: // MIs[0] DstI[dst]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID),
// CHECK-NEXT: // MIs[0] src
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Test::SRegsRegClassID),
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s16,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(Test::SRegsRegClassID),
// CHECK-NEXT: // (sext:{ *:[i32] } SOP:{ *:[i16] }:$src) => (REG_SEQUENCE:{ *:[i32] } DRegs:{ *:[i32] }, (SUBSOME_INSN:{ *:[i16] } SOP:{ *:[i16] }:$src), sub0:{ *:[i32] }, (SUBSOME_INSN:{ *:[i16] } SOP:{ *:[i16] }:$src), sub1:{ *:[i32] })
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(MyTarget::SUBSOME_INSN),
@@ -50,7 +50,7 @@ def SUBSOME_INSN : I<(outs SRegs:$dst), (ins SOP:$src), []>;
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
diff --git a/llvm/test/TableGen/GlobalISelEmitter/Subreg.td b/llvm/test/TableGen/GlobalISelEmitter/Subreg.td
index 777fabb8fdefb..74959ad67d684 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/Subreg.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/Subreg.td
@@ -72,7 +72,7 @@ def : Pat<(sub (complex DOP:$src1, DOP:$src2), 77),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Test::SRegsRegClassID),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID),
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::SOME_INSN2),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
@@ -88,9 +88,9 @@ def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SOP:$src
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src
+// CHECK-NEXT: GIR_RootToRootCopy1, // src
// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::DRegsRegClassID),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID),
@@ -117,7 +117,7 @@ def : Pat<(i32 (anyext i16:$src)), (SOME_INSN (INSERT_SUBREG (i32 (IMPLICIT_DEF)
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(Test::SRegsRegClassID),
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::SOME_INSN),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
// CHECK-NEXT: // GIR_Coverage, 4,
@@ -148,7 +148,7 @@ def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (IMPLICIT_DEF)), (SUBSOME
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
@@ -186,7 +186,7 @@ def : Pat<(i16 (trunc (bitreverse DOP:$src))),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// CHECK-NEXT: GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(sub0),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::SRegsRegClassID),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID),
@@ -212,7 +212,7 @@ def : Pat<(i16 (trunc (bitreverse DOP:$src))),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Test::SRegsRegClassID),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID),
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::SUBSOME_INSN2),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
// CHECK-NEXT: // GIR_Coverage, 9,
@@ -225,7 +225,7 @@ def : Pat<(i16 (trunc DOP:$src)),
(EXTRACT_SUBREG DOP:$src, sub0)>;
// CHECK-LABEL: // (trunc:{ *:[i16] } DOP:{ *:[i32] }:$src) => (EXTRACT_SUBREG:{ *:[i16] } DOP:{ *:[i32] }:$src, sub0:{ *:[i32] })
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// CHECK-NEXT: GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // src
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::SRegsRegClassID),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID),
@@ -242,7 +242,7 @@ def : Pat<(i32 (zext SOP:$src)),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::DRegsRegClassID),
diff --git a/llvm/test/TableGen/GlobalISelEmitter/Variadic.td b/llvm/test/TableGen/GlobalISelEmitter/Variadic.td
index b3c80526af81f..a73501f4558be 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/Variadic.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/Variadic.td
@@ -26,10 +26,10 @@ def : Pat<(build_vector GPR32:$src1, GPR32:$src2),
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4([[NEXT_NUM_OPERANDS_LABEL_1:[0-9]+]]), // Rule ID 0 //
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: // (build_vector:{ *:[i32] } GPR32:{ *:[i32] }:$src1) => (ONE:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ONE),
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
@@ -38,12 +38,12 @@ def : Pat<(build_vector GPR32:$src1, GPR32:$src2),
// CHECK-NEXT: // Label 1: @[[NEXT_NUM_OPERANDS_LABEL_1]]
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4([[NEXT_NUM_OPERANDS_LABEL_2:[0-9]+]]), // Rule ID 1 //
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: // (build_vector:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) => (TWO:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2)
// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::TWO),
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
diff --git a/llvm/test/TableGen/GlobalISelEmitter/atomic-store.td b/llvm/test/TableGen/GlobalISelEmitter/atomic-store.td
index 99869cc4e8ef0..d9ceb9df0a155 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/atomic-store.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/atomic-store.td
@@ -9,7 +9,7 @@ def ST_ATOM_B32 : I<(outs), (ins GPR32Op:$val, GPR32Op:$ptr), []>;
// GISEL-NEXT: GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
// GISEL-NEXT: GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
// GISEL-NEXT: // MIs[0] val
-// GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
+// GISEL-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
// GISEL-NEXT: // MIs[0] ptr
// GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
// GISEL-NEXT: // (atomic_store i32:{ *:[i32] }:$val, iPTR:{ *:[iPTR] }:$ptr)<<P:Predicate_atomic_store_8>> => (ST_ATOM_B32 GPR32Op:{ *:[i32] }:$val, GPR32Op:{ *:[i32] }:$ptr)
diff --git a/llvm/test/TableGen/GlobalISelEmitter/dead-def.td b/llvm/test/TableGen/GlobalISelEmitter/dead-def.td
index f05d7ec1c5a3d..b0610831a54ec 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/dead-def.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/dead-def.td
@@ -20,7 +20,7 @@ def : Pat<(abs i32:$x), (I1 (I2 $x))>;
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // x
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::I1),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[same_name]
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[same_name]
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
// CHECK-NEXT: // GIR_Coverage, 0,
diff --git a/llvm/test/TableGen/GlobalISelEmitter/frameindex.td b/llvm/test/TableGen/GlobalISelEmitter/frameindex.td
index 27784526a65ba..b411f97110a4c 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/frameindex.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/frameindex.td
@@ -15,12 +15,12 @@ def : Pat<(frameindex:$fi), (ADDI (to_tframeindex $fi), 0)>;
def : Pat<(ptradd frameindex:$fi, (i32 imm:$offset)),
(ADDI (to_tframeindex $fi), imm:$offset)>;
-// CHECK-LABEL: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(74), // Rule ID 1 //
+// CHECK-LABEL: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(71), // Rule ID 1 //
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_PTR_ADD),
// CHECK-NEXT: // MIs[0] DstI[dst]
// CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: // MIs[0] fi
// CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
@@ -31,7 +31,7 @@ def : Pat<(ptradd frameindex:$fi, (i32 imm:$offset)),
// CHECK-NEXT: // MIs[1] Operand 1
// CHECK-NEXT: // No operand predicates
// CHECK-NEXT: // MIs[0] offset
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/2, /*Expected*/2,
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
@@ -42,24 +42,24 @@ def : Pat<(ptradd frameindex:$fi, (i32 imm:$offset)),
// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/2,
// CHECK-NEXT: // (ptradd:{ *:[i32] } (frameindex:{ *:[i32] }):$fi, (imm:{ *:[i32] }):$offset) => (ADDI:{ *:[i32] } (to_tframeindex:{ *:[i32] } ?:{ *:[i32] }:$fi), (imm:{ *:[i32] }):$offset)
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::ADDI),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// CHECK-NEXT: GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFrameIndex), // fi
// CHECK-NEXT: GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // offset
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
// CHECK-NEXT: // GIR_Coverage, 1,
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
-// CHECK-LABEL: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(109), // Rule ID 0 //
+// CHECK-LABEL: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(104), // Rule ID 0 //
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FRAME_INDEX),
// CHECK-NEXT: // MIs[0] DstI[dst]
// CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: // MIs[0] Operand 1
// CHECK-NEXT: // No operand predicates
// CHECK-NEXT: // (frameindex:{ *:[i32] }):$fi => (ADDI:{ *:[i32] } (to_tframeindex:{ *:[i32] } ?:{ *:[i32] }:$fi), 0:{ *:[i32] })
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::ADDI),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// CHECK-NEXT: GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderFrameIndex), // fi
// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
diff --git a/llvm/test/TableGen/GlobalISelEmitter/gisel-physreg-input.td b/llvm/test/TableGen/GlobalISelEmitter/gisel-physreg-input.td
index 8fa004373ef69..8793e7b00541a 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/gisel-physreg-input.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/gisel-physreg-input.td
@@ -29,8 +29,8 @@ class I<dag OOps, dag IOps, list<dag> Pat>
// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_STORE),
// GISEL-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
// GISEL-NEXT: // MIs[0] src0
-// GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// GISEL-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// GISEL-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// GISEL-NEXT: // MIs[0] Operand 1
// GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
// GISEL-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
@@ -50,7 +50,7 @@ class I<dag OOps, dag IOps, list<dag> Pat>
// GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // SPECIAL
// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MULM_PHYS),
-// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // src0
+// GISEL-NEXT: GIR_RootToRootCopy0, // src0
// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
// GISEL-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
// GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
@@ -68,8 +68,8 @@ def MULM_PHYS : I<(outs), (ins GPR32:$src0, GPR32:$src1),
// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_STORE),
// GISEL-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
// GISEL-NEXT: // MIs[0] src0
-// GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// GISEL-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// GISEL-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// GISEL-NEXT: // MIs[0] Operand 1
// GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
// GISEL-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
@@ -92,7 +92,7 @@ def MULM_PHYS : I<(outs), (ins GPR32:$src0, GPR32:$src1),
// GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::R0), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // R0
// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MULMR0_PHYS),
-// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // src0
+// GISEL-NEXT: GIR_RootToRootCopy0, // src0
// GISEL-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
// GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
// GISEL-NEXT: // GIR_Coverage, 1,
@@ -108,21 +108,21 @@ def MULMR0_PHYS : I<(outs), (ins GPR32:$src0),
// GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ADD),
// GISEL-NEXT: // MIs[0] DstI[dst]
-// GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// GISEL-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// GISEL-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// GISEL-NEXT: // MIs[0] src0
-// GISEL-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// GISEL-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
+// GISEL-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// GISEL-NEXT: // MIs[0] Operand 2
-// GISEL-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
-// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::Special32RegClassID),
+// GISEL-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
+// GISEL-NEXT: GIM_RootCheckRegBankForClass2, /*RC*/GIMT_Encode2(MyTarget::Special32RegClassID),
// GISEL-NEXT: // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src0, SPECIAL:{ *:[i32] }) => (ADD_PHYS:{ *:[i32] } GPR32:{ *:[i32] }:$src0)
// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
// GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // SPECIAL
// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::ADD_PHYS),
-// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
-// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src0
+// GISEL-NEXT: GIR_RootToRootCopy0, // DstI[dst]
+// GISEL-NEXT: GIR_RootToRootCopy1, // src0
// GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
// GISEL-NEXT: // GIR_Coverage, 2,
// GISEL-NEXT: GIR_EraseRootFromParent_Done,
@@ -137,21 +137,21 @@ def ADD_PHYS : I<(outs GPR32:$dst), (ins GPR32:$src0),
// GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL),
// GISEL-NEXT: // MIs[0] DstI[dst]
-// GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// GISEL-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// GISEL-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// GISEL-NEXT: // MIs[0] SPECIAL
-// GISEL-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// GISEL-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
+// GISEL-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// GISEL-NEXT: // MIs[0] Operand 2
-// GISEL-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
-// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::Special32RegClassID),
+// GISEL-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
+// GISEL-NEXT: GIM_RootCheckRegBankForClass2, /*RC*/GIMT_Encode2(MyTarget::Special32RegClassID),
// GISEL-NEXT: // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$SPECIAL, SPECIAL:{ *:[i32] }) => (MUL_PHYS:{ *:[i32] } GPR32:{ *:[i32] }:$SPECIAL)
// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
// GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // SPECIAL
// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MUL_PHYS),
-// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
-// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // SPECIAL
+// GISEL-NEXT: GIR_RootToRootCopy0, // DstI[dst]
+// GISEL-NEXT: GIR_RootToRootCopy1, // SPECIAL
// GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
// GISEL-NEXT: // GIR_Coverage, 3,
// GISEL-NEXT: GIR_EraseRootFromParent_Done,
diff --git a/llvm/test/TableGen/GlobalISelEmitter/immAllZeroOne.td b/llvm/test/TableGen/GlobalISelEmitter/immAllZeroOne.td
index 68278f46627c6..f65dd05fafa61 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/immAllZeroOne.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/immAllZeroOne.td
@@ -11,12 +11,12 @@ include "GlobalISelEmitterCommon.td"
// GISEL-OPT: GIM_Try,
-// GISEL-OPT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
+// GISEL-OPT: GIM_RootCheckType2, /*Type*/GILLT_v4s16,
// GISEL-OPT: GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
// GISEL-OPT: GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
// GISEL-OPT: GIM_Try,
-// GISEL-OPT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
+// GISEL-OPT: GIM_RootCheckType2, /*Type*/GILLT_v4s16,
// GISEL-OPT: GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
// GISEL-OPT: GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
@@ -24,7 +24,7 @@ include "GlobalISelEmitterCommon.td"
// GISEL-NOOPT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_LSHR),
// GISEL-NOOPT: // MIs[0] Operand 2
-// GISEL-NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
+// GISEL-NOOPT-NEXT: GIM_RootCheckType2, /*Type*/GILLT_v4s16,
// GISEL-NOOPT-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
// GISEL-NOOPT-NEXT: GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
// GISEL-NOOPT-NEXT: GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
@@ -39,7 +39,7 @@ def VFOOONES : I<(outs VecReg128:$dst), (ins VecReg128:$src0),
// GISEL-NOOPT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SHL),
// GISEL-NOOPT: // MIs[0] Operand 2
-// GISEL-NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
+// GISEL-NOOPT-NEXT: GIM_RootCheckType2, /*Type*/GILLT_v4s16,
// GISEL-NOOPT-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
// GISEL-NOOPT-NEXT: GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
// GISEL-NOOPT-NEXT: GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
diff --git a/llvm/test/TableGen/GlobalISelEmitter/immarg-literal-pattern.td b/llvm/test/TableGen/GlobalISelEmitter/immarg-literal-pattern.td
index ff05ac12f32ce..dfc7118f2ce27 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/immarg-literal-pattern.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/immarg-literal-pattern.td
@@ -43,7 +43,7 @@ def : Pat<
// Check a non-intrinsic instruction with an immediate parameter.
// GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(MyTarget::G_TGT_CAT),
-// GISEL: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
+// GISEL: GIM_RootCheckType1, /*Type*/GILLT_s32,
// GISEL-NEXT: // MIs[0] Operand 2
// GISEL-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
def : Pat<
@@ -52,7 +52,7 @@ def : Pat<
>;
// GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(MyTarget::G_TGT_CAT),
-// GISEL: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
+// GISEL: GIM_RootCheckType1, /*Type*/GILLT_s32,
// GISEL-NEXT: // MIs[0] Operand 2
// GISEL-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(93),
def : Pat<
diff --git a/llvm/test/TableGen/GlobalISelEmitter/immarg-predicated.td b/llvm/test/TableGen/GlobalISelEmitter/immarg-predicated.td
index ab412fac48e12..f270d5054721a 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/immarg-predicated.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/immarg-predicated.td
@@ -15,7 +15,7 @@ def int_mytarget_sleep0 : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
// GISEL-NEXT: GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tuimm9),
// GISEL-NEXT: // (intrinsic_void {{[0-9]+}}:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_tuimm9>>:$src) => (SLEEP0 (timm:{ *:[i32] }):$src)
// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::SLEEP0),
-// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src
+// GISEL-NEXT: GIR_RootToRootCopy1, // src
def tuimm9 : TImmLeaf<i32, [{ return isUInt<9>(Imm); }]>;
def SLEEP0 : I<(outs), (ins i32imm:$src),
[(int_mytarget_sleep0 tuimm9:$src)]
diff --git a/llvm/test/TableGen/GlobalISelEmitter/immarg.td b/llvm/test/TableGen/GlobalISelEmitter/immarg.td
index eae04094a689e..d47649d9c230c 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/immarg.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/immarg.td
@@ -15,7 +15,7 @@ def int_mytarget_sleep1 : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
// GISEL-NEXT: GIM_CheckIsImm, /*MI*/0, /*Op*/1,
// GISEL-NEXT: // (intrinsic_void {{[0-9]+}}:{ *:[iPTR] }, (timm:{ *:[i32] }):$src) => (SLEEP0 (timm:{ *:[i32] }):$src)
// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::SLEEP0),
-// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src
+// GISEL-NEXT: GIR_RootToRootCopy1, // src
def SLEEP0 : I<(outs), (ins i32imm:$src),
[(int_mytarget_sleep0 timm:$src)]
>;
diff --git a/llvm/test/TableGen/GlobalISelEmitter/input-discard.td b/llvm/test/TableGen/GlobalISelEmitter/input-discard.td
index b18d905b0bbf7..97d5bc5ee406d 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/input-discard.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/input-discard.td
@@ -11,19 +11,19 @@ def FOO : I<(outs GPR32:$dst), (ins GPR32Op:$src0, GPR32Op:$src1), []>;
// GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS),
// GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
// GISEL-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::tgt_foo),
-// GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// GISEL-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
-// GISEL-NEXT: GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
-// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// GISEL-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// GISEL-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
+// GISEL-NEXT: GIM_RootCheckType3, /*Type*/GILLT_s32,
+// GISEL-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// GISEL-NEXT: // (intrinsic_w_chain:{ *:[i32] } {{[0-9]+}}:{ *:[iPTR] }, srcvalue:{ *:[i32] }, i32:{ *:[i32] }:$src1) => (FOO:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GPR32:{ *:[i32] }:$src1)
// GISEL-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
// GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FOO),
-// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// GISEL-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// GISEL-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
-// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/3, // src1
+// GISEL-NEXT: GIR_RootToRootCopy3, // src1
// GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
// GISEL-NEXT: // GIR_Coverage
// GISEL-NEXT: GIR_EraseRootFromParent_Done,
diff --git a/llvm/test/TableGen/GlobalISelEmitter/int64min.td b/llvm/test/TableGen/GlobalISelEmitter/int64min.td
index ccdb749f2c148..2359645b280be 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/int64min.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/int64min.td
@@ -6,22 +6,22 @@ include "GlobalISelEmitterCommon.td"
def GPR : RegisterClass<"MyTarget", [i64], 64, (add R0)>;
def ANDI : I<(outs GPR:$dst), (ins GPR:$src1, i64imm:$src2), []>;
-// CHECK-LABEL: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(59), // Rule ID 0 //
+// CHECK-LABEL: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(52), // Rule ID 0 //
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_AND),
// CHECK-NEXT: // MIs[0] DstI[dst]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s64,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID),
// CHECK-NEXT: // MIs[0] rs1
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID),
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s64,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID),
// CHECK-NEXT: // MIs[0] Operand 2
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
+// CHECK-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s64,
// CHECK-NEXT: GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(9223372036854775808u),
// CHECK-NEXT: // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, -9223372036854775808:{ *:[i64] }) => (ANDI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, -9223372036854775808:{ *:[i64] })
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::ANDI),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // rs1
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[dst]
+// CHECK-NEXT: GIR_RootToRootCopy1, // rs1
// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(9223372036854775808u),
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
// CHECK-NEXT: // GIR_Coverage, 0,
diff --git a/llvm/test/TableGen/GlobalISelEmitter/metadata-operand.td b/llvm/test/TableGen/GlobalISelEmitter/metadata-operand.td
index aee05d98dda4b..7538b175bae1f 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/metadata-operand.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/metadata-operand.td
@@ -19,8 +19,8 @@ def LOAD : I<(outs GPR32:$dst), (ins GPR32Op:$src), []>;
// CHECK: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS),
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
// CHECK-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::tgt_metadata_intrinsic),
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: // MIs[0] src
// CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
// CHECK-NEXT: // MIs[0] Operand 3
diff --git a/llvm/test/TableGen/GlobalISelEmitter/multiple-output-discard.td b/llvm/test/TableGen/GlobalISelEmitter/multiple-output-discard.td
index 54b0f4412da6e..c51da36c46932 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/multiple-output-discard.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/multiple-output-discard.td
@@ -23,21 +23,21 @@ def : Pat<(two_out GPR32:$val), (THREE_OUTS GPR32:$val)>;
// CHECK: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(MyTarget::G_TWO_OUT),
// CHECK-NEXT: // MIs[0] DstI[out1]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: // MIs[0] DstI[out2]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: // MIs[0] val
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: // (two_out:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$val) => (THREE_OUTS:{ *:[i32] }:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$val)
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::THREE_OUTS),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out1]
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // DstI[out2]
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[out1]
+// CHECK-NEXT: GIR_RootToRootCopy1, // DstI[out2]
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // val
+// CHECK-NEXT: GIR_RootToRootCopy2, // val
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
// CHECK-NEXT: // GIR_Coverage
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
diff --git a/llvm/test/TableGen/GlobalISelEmitter/multiple-output.td b/llvm/test/TableGen/GlobalISelEmitter/multiple-output.td
index 17cc0695a463d..c7fb9409fa0a3 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/multiple-output.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/multiple-output.td
@@ -30,19 +30,28 @@ def : Pat<(loadpost (p0 GPR32:$addr), (i32 GPR32:$off)),
(LDPost GPR32:$addr, GPR32:$off)
>;
+// CHECK: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(MyTarget::G_NINE_IN),
+// CHECK: GIM_RootCheckType8, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass8, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK: GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/9, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::NINE_INS),
+// CHECK: GIR_RootToRootCopy, /*OpIdx*/9,
+// CHECK-NEXT: GIR_RootToRootCopy8,
+
// CHECK: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(MyTarget::G_POST_LOAD),
// CHECK-NEXT: // MIs[0] DstI[val]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: // MIs[0] DstI[ptr_out]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_p0s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_p0s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: // MIs[0] addr
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType2, /*Type*/GILLT_p0s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: // MIs[0] off
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType3, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass3, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: // (loadpost:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$addr, GPR32:{ *:[i32] }:$off) => (LDPost:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$addr, GPR32:{ *:[i32] }:$off)
// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LDPost),
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
@@ -67,27 +76,54 @@ def : Pat<(two_in GPR32:$i1, GPR32:$i2), (TWO_INS GPR32:$i2, GPR32:$i1)>;
// CHECK: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(MyTarget::G_TWO_IN),
// CHECK-NEXT: // MIs[0] DstI[out1]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: // MIs[0] DstI[out2]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: // MIs[0] i1
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: // MIs[0] i2
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType3, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass3, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: // (two_in:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$i1, GPR32:{ *:[i32] }:$i2) => (TWO_INS:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$i2, GPR32:{ *:[i32] }:$i1)
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::TWO_INS),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out1]
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // DstI[out2]
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/3, // i2
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // i1
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[out1]
+// CHECK-NEXT: GIR_RootToRootCopy1, // DstI[out2]
+// CHECK-NEXT: GIR_RootToRootCopy3, // i2
+// CHECK-NEXT: GIR_RootToRootCopy2, // i1
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
// CHECK-NEXT: // GIR_Coverage
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
+//-----------------------------------------------------------------------------
+// Test root operand indices 8 and 9, including the ULEB128 fallback for 9.
+
+def NINE_INS : I<(outs GPR32:$out),
+ (ins GPR32:$in0, GPR32:$in1, GPR32:$in2, GPR32:$in3,
+ GPR32:$in4, GPR32:$in5, GPR32:$in6, GPR32:$in7,
+ GPR32:$in8), []>;
+
+def SDTNineIn : SDTypeProfile<1, 9, [
+ SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>, SDTCisInt<3>, SDTCisInt<4>,
+ SDTCisInt<5>, SDTCisInt<6>, SDTCisInt<7>, SDTCisInt<8>, SDTCisInt<9>
+]>;
+def nine_in : SDNode<"MyTgt::NINE_IN", SDTNineIn, []>;
+def G_NINE_IN : MyTargetGenericInstruction {
+ let OutOperandList = (outs type0:$out);
+ let InOperandList = (ins type0:$in0, type0:$in1, type0:$in2, type0:$in3,
+ type0:$in4, type0:$in5, type0:$in6, type0:$in7,
+ type0:$in8);
+}
+def : GINodeEquiv<G_NINE_IN, nine_in>;
+def : Pat<(nine_in GPR32:$in0, GPR32:$in1, GPR32:$in2, GPR32:$in3,
+ GPR32:$in4, GPR32:$in5, GPR32:$in6, GPR32:$in7,
+ GPR32:$in8),
+ (NINE_INS GPR32:$in8, GPR32:$in7, GPR32:$in6, GPR32:$in5,
+ GPR32:$in4, GPR32:$in3, GPR32:$in2, GPR32:$in1,
+ GPR32:$in0)>;
+
//-----------------------------------------------------------------------------
// Test where implicit defs are added using Defs.
@@ -100,10 +136,10 @@ def : Pat<(i32 (add i32:$src, i32:$src)),
// CHECK: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ADD),
// CHECK-NEXT: // MIs[0] DstI[dst]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: // MIs[0] src
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
// CHECK-NEXT: // MIs[0] src
// CHECK-NEXT: GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
// CHECK-NEXT: // (add:{ *:[i32] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$src) => (OtherInstr:{ *:[i32] } (ImplicitDefInstr:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$src))
@@ -114,7 +150,7 @@ def : Pat<(i32 (add i32:$src, i32:$src)),
// CHECK-NEXT: GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for MyTarget::R0*/0,
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::OtherInstr),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
// CHECK-NEXT: // GIR_Coverage
@@ -125,10 +161,10 @@ def : Pat<(i32 (add i32:$src, i32:$src)),
// CHECK: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ADD),
// CHECK-NEXT: // MIs[0] DstI[dst]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: // MIs[0] src
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
// CHECK-NEXT: // MIs[0] src
// CHECK-NEXT: GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
// CHECK-NEXT: // (add:{ *:[i32] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$src) => (OtherInstr:{ *:[i32] } (TwoOutsInstr:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$src))
@@ -140,7 +176,7 @@ def : Pat<(i32 (add i32:$src, i32:$src)),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::OtherInstr),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
// CHECK-NEXT: // GIR_Coverage
diff --git a/llvm/test/TableGen/GlobalISelEmitter/nested-subregs.td b/llvm/test/TableGen/GlobalISelEmitter/nested-subregs.td
index 2513161eec24f..7b517f4255c38 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/nested-subregs.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/nested-subregs.td
@@ -33,10 +33,10 @@ def A0 : RegisterClass<"MyTarget", [i32], 32, (add a0)>;
// CHECK: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ANYEXT),
// CHECK-NEXT: // MIs[0] DstI[dst]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::A0wRegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s16,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::A0wRegClassID),
// CHECK-NEXT: // MIs[0] src
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
+// CHECK-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s8,
// CHECK-NEXT: // (anyext:{ *:[i16] } i8:{ *:[i8] }:$src) => (EXTRACT_SUBREG:{ *:[i16] } (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), A0b:{ *:[i8] }:$src, lo8:{ *:[i32] }), lo16:{ *:[i32] })
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
@@ -52,7 +52,7 @@ def A0 : RegisterClass<"MyTarget", [i32], 32, (add a0)>;
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(MyTarget::A0RegClassID),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(MyTarget::A0bRegClassID),
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// CHECK-NEXT: GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(MyTarget::lo16),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(MyTarget::A0wRegClassID),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(MyTarget::A0RegClassID),
diff --git a/llvm/test/TableGen/GlobalISelEmitter/optional-def.td b/llvm/test/TableGen/GlobalISelEmitter/optional-def.td
index 3fc05dc368e1c..d038436c45222 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/optional-def.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/optional-def.td
@@ -10,18 +10,18 @@ def s_cc_out : OptionalDefOperand<i32, (ops GPR8, FPR32), (ops (i8 B0), F0)>;
// CHECK-LABEL: // (add:{ *:[i32] } i32:{ *:[i32] }:$rs1, i32:{ *:[i32] }:$rs2) => (tst2:{ *:[i32] } i32:{ *:[i32] }:$rs1, i32:{ *:[i32] }:$rs2)
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::tst2),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[rd]
// CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::B0), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
// CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::F0), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // rs1
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // rs2
+// CHECK-NEXT: GIR_RootToRootCopy1, // rs1
+// CHECK-NEXT: GIR_RootToRootCopy2, // rs2
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
// CHECK-NEXT: // GIR_Coverage, 1,
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
// CHECK-LABEL: // (imm:{ *:[i32] }):$imm => (tst1:{ *:[i32] } (imm:{ *:[i32] }):$imm)
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::tst1),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[rd]
// CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
// CHECK-NEXT: GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
diff --git a/llvm/test/TableGen/GlobalISelEmitter/output-discard.td b/llvm/test/TableGen/GlobalISelEmitter/output-discard.td
index dfb6b1f104711..8972c69a0a922 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/output-discard.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/output-discard.td
@@ -8,17 +8,17 @@ def ADD_CO : I<(outs GPR32:$dst, GPR8:$flag),
(ins GPR32Op:$src0, GPR32Op:$src1), []>;
// GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ADD),
-// GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// GISEL-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// GISEL-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
-// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// GISEL-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// GISEL-NEXT: GIM_RootCheckType1, /*Type*/GILLT_s32,
+// GISEL-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
+// GISEL-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// GISEL-NEXT: // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (ADD_CO:{ *:[i32] }:{ *:[i8] } GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1)
// GISEL-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::ADD_CO),
-// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
+// GISEL-NEXT: GIR_RootToRootCopy0, // DstI[dst]
// GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
-// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src0
-// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // src1
+// GISEL-NEXT: GIR_RootToRootCopy1, // src0
+// GISEL-NEXT: GIR_RootToRootCopy2, // src1
// GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
// GISEL-NEXT: // GIR_Coverage
// GISEL-NEXT: GIR_EraseRootFromParent_Done,
diff --git a/llvm/test/TableGen/GlobalISelEmitter/predicated-pattern-order.td b/llvm/test/TableGen/GlobalISelEmitter/predicated-pattern-order.td
index ce420dbe01a27..cc2ad9abb60a4 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/predicated-pattern-order.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/predicated-pattern-order.td
@@ -19,11 +19,11 @@ def aligned_store: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{
// CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
// CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
// CHECK-NEXT: // MIs[0] src0
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: // MIs[0] src1
// CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_store),
// CHECK-NEXT: // (st GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_aligned_store>> => (MOVALIGNED GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1)
// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOVALIGNED),
@@ -36,11 +36,11 @@ def aligned_store: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{
// CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
// CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
// CHECK-NEXT: // MIs[0] src0
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: // MIs[0] src1
// CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: // (st GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (MOVUNALIGNED GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1)
// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOVUNALIGNED),
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
@@ -48,15 +48,15 @@ def aligned_store: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{
// OPT: GIM_Try
// OPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_STORE),
-// OPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
+// OPT-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
// OPT-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
// OPT-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
// OPT-NEXT: GIM_Try
-// OPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// OPT-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// OPT-NEXT: // MIs[0] src1
// OPT-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
-// OPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// OPT-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// OPT-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_store),
// OPT-NEXT: // (st GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_aligned_store>> => (MOVALIGNED GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1)
// OPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOVALIGNED),
@@ -64,10 +64,10 @@ def aligned_store: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{
// OPT-NEXT: // GIR_Coverage
// OPT: GIM_Try
-// OPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// OPT-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// OPT-NEXT: // MIs[0] src1
// OPT-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
-// OPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// OPT-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// OPT-NEXT: // (st GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (MOVUNALIGNED GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1)
// OPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOVUNALIGNED),
// OPT-NEXT: GIR_RootConstrainSelectedInstOperands,
diff --git a/llvm/test/TableGen/GlobalISelEmitter/undef-tied-input.td b/llvm/test/TableGen/GlobalISelEmitter/undef-tied-input.td
index c0a9d2391b5a2..6ad5f24503ccb 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/undef-tied-input.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/undef-tied-input.td
@@ -27,8 +27,8 @@ def I2 : I<(outs GPR32:$rd), (ins GPR32:$rs, undef_tied_2:$opt),
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::I1),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // rs
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[rd]
+// CHECK-NEXT: GIR_RootToRootCopy1, // rs
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
// CHECK-NEXT: // GIR_Coverage, 0,
diff --git a/llvm/test/TableGen/GlobalISelEmitter/zero-reg.td b/llvm/test/TableGen/GlobalISelEmitter/zero-reg.td
index dfbe7f902c011..454222ee91105 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/zero-reg.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/zero-reg.td
@@ -25,15 +25,15 @@ def INST : PredI<(outs GPR32:$dst), (ins GPR32:$src), []>;
// CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
// CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
// CHECK-NEXT: // MIs[0] DstI[dst]
-// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: // MIs[0] src
// CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
-// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
+// CHECK-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: // (ld:{ *:[i32] } GPR32:{ *:[i32] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (INST:{ *:[i32] } GPR32:{ *:[i32] }:$src)
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::INST),
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
-// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src
+// CHECK-NEXT: GIR_RootToRootCopy0, // DstI[dst]
+// CHECK-NEXT: GIR_RootToRootCopy1, // src
// CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
diff --git a/llvm/test/TableGen/HasNoUse.td b/llvm/test/TableGen/HasNoUse.td
index d51fa9ef07230..7af776268e9b1 100644
--- a/llvm/test/TableGen/HasNoUse.td
+++ b/llvm/test/TableGen/HasNoUse.td
@@ -17,16 +17,16 @@ def NO_RET_ATOMIC_ADD : I<(outs), (ins GPR32Op:$src0, GPR32Op:$src1), []>;
// SDAG-NEXT: return true;
// GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ATOMICRMW_ADD),
-// GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
-// GISEL-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
+// GISEL-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
+// GISEL-NEXT: GIM_RootCheckType2, /*Type*/GILLT_s32,
// GISEL-NEXT: GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
// GISEL-NEXT: GIM_CheckHasNoUse, /*MI*/0,
// GISEL-NEXT: // MIs[0] src0
// GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
// GISEL-NEXT: // (atomic_load_add:{ *:[i32] } iPTR:{ *:[iPTR] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_atomic_load_add_no_ret_i32>> => (NO_RET_ATOMIC_ADD GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1)
// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::NO_RET_ATOMIC_ADD),
-// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src0
-// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // src1
+// GISEL-NEXT: GIR_RootToRootCopy1, // src0
+// GISEL-NEXT: GIR_RootToRootCopy2, // src1
// GISEL-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
// GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
// GISEL-NEXT: // GIR_Coverage, 0,
diff --git a/llvm/test/TableGen/RegClassByHwMode.td b/llvm/test/TableGen/RegClassByHwMode.td
index 46aef05ebc9c2..f2cd3e167405e 100644
--- a/llvm/test/TableGen/RegClassByHwMode.td
+++ b/llvm/test/TableGen/RegClassByHwMode.td
@@ -236,16 +236,16 @@ include "Common/RegClassByHwModeCommon.td"
// ISEL-GISEL: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4({{[0-9]+}}),
-// ISEL-GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
+// ISEL-GISEL-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s64,
// ISEL-GISEL-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
// ISEL-GISEL-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
-// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::XRegsRegClassID),
+// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::XRegsRegClassID),
// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4({{[0-9]+}}),
// ISEL-GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
// FIXME: This should be a direct check for regbank, not have an incorrect class
-// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID),
+// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID),
// ISEL-GISEL-NEXT: GIM_Try_CheckFeatures, /*On fail goto*//*Label 5*/ GIMT_Encode4({{[0-9]+}}), GIMT_Encode2(GIFBS_HwMode0), // Rule ID 4 //
// ISEL-GISEL-NEXT: // (ld:{ *:[i64] } PtrRegOperand:{ *:[i32] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (MY_LOAD:{ *:[i64] } ?:{ *:[i32] }:$src)
// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_LOAD),
@@ -265,7 +265,7 @@ include "Common/RegClassByHwModeCommon.td"
// ISEL-GISEL-NEXT: GIM_Try_CheckFeatures, /*On fail goto*//*Label 7*/ GIMT_Encode4({{[0-9]+}}), GIMT_Encode2(GIFBS_HwMode2), // Rule ID 6 //
// ISEL-GISEL-NEXT: // MIs[0] src
// ISEL-GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
-// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID),
+// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID),
// ISEL-GISEL-NEXT: // (ld:{ *:[i64] } PtrRegOperand:{ *:[i64] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (MY_LOAD:{ *:[i64] } ?:{ *:[i64] }:$src)
// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_LOAD),
// ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
@@ -275,7 +275,7 @@ include "Common/RegClassByHwModeCommon.td"
// ISEL-GISEL-NEXT: GIM_Try_CheckFeatures, /*On fail goto*//*Label 8*/ GIMT_Encode4({{[0-9]+}}), GIMT_Encode2(GIFBS_HwMode3), // Rule ID 7 //
// ISEL-GISEL-NEXT: // MIs[0] src
// ISEL-GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
-// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID),
+// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID),
// ISEL-GISEL-NEXT: // (ld:{ *:[i64] } PtrRegOperand:{ *:[i32] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (MY_LOAD:{ *:[i64] } ?:{ *:[i32] }:$src)
// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_LOAD),
// ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
@@ -287,13 +287,13 @@ include "Common/RegClassByHwModeCommon.td"
// ISEL-GISEL-NEXT: GIM_Reject,
// ISEL-GISEL-NEXT: // Label 1: @{{[0-9]+}}
// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 9*/ GIMT_Encode4({{[0-9]+}}),
-// ISEL-GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
+// ISEL-GISEL-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s64,
// ISEL-GISEL-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
// ISEL-GISEL-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
-// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::XRegsRegClassID),
+// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass0, /*RC*/GIMT_Encode2(MyTarget::XRegsRegClassID),
// ISEL-GISEL-NEXT: GIM_Try, /*On fail goto*//*Label 10*/ GIMT_Encode4({{[0-9]+}}),
// ISEL-GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
-// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID),
+// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID),
// ISEL-GISEL-NEXT: GIM_Try_CheckFeatures, /*On fail goto*//*Label 11*/ GIMT_Encode4({{[0-9]+}}), GIMT_Encode2(GIFBS_HwMode0), // Rule ID 0 //
// ISEL-GISEL-NEXT: // (st XRegs_EvenIfRequired:{ *:[i64] }:$val, MyPtrRC:{ *:[i32] }:$src)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (MY_STORE XRegs_EvenIfRequired:{ *:[i64] }:$val, ?:{ *:[i32] }:$src)
// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_STORE),
@@ -313,7 +313,7 @@ include "Common/RegClassByHwModeCommon.td"
// ISEL-GISEL-NEXT: GIM_Try_CheckFeatures, /*On fail goto*//*Label 13*/ GIMT_Encode4({{[0-9]+}}), GIMT_Encode2(GIFBS_HwMode2), // Rule ID 2 //
// ISEL-GISEL-NEXT: // MIs[0] src
// ISEL-GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
-// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID),
+// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID),
// ISEL-GISEL-NEXT: // (st XRegs_EvenIfRequired:{ *:[i64] }:$val, MyPtrRC:{ *:[i64] }:$src)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (MY_STORE XRegs_EvenIfRequired:{ *:[i64] }:$val, ?:{ *:[i64] }:$src)
// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_STORE),
// ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
@@ -323,7 +323,7 @@ include "Common/RegClassByHwModeCommon.td"
// ISEL-GISEL-NEXT: GIM_Try_CheckFeatures, /*On fail goto*//*Label 14*/ GIMT_Encode4({{[0-9]+}}), GIMT_Encode2(GIFBS_HwMode3), // Rule ID 3 //
// ISEL-GISEL-NEXT: // MIs[0] src
// ISEL-GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
-// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID),
+// ISEL-GISEL-NEXT: GIM_RootCheckRegBankForClass1, /*RC*/GIMT_Encode2(MyTarget::PtrRegs32RegClassID),
// ISEL-GISEL-NEXT: // (st XRegs_EvenIfRequired:{ *:[i64] }:$val, MyPtrRC:{ *:[i32] }:$src)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (MY_STORE XRegs_EvenIfRequired:{ *:[i64] }:$val, ?:{ *:[i32] }:$src)
// ISEL-GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MY_STORE)
// ISEL-GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
@@ -335,7 +335,7 @@ include "Common/RegClassByHwModeCommon.td"
// ISEL-GISEL-NEXT: GIM_Reject,
// ISEL-GISEL-NEXT: // Label 2: @{{[0-9]+}}
// ISEL-GISEL-NEXT: GIM_Reject,
-// ISEL-GISEL-NEXT: }; // Size: 257 bytes
+// ISEL-GISEL-NEXT: }; // Size: 247 bytes
def HasAlignedRegisters : Predicate<"Subtarget->hasAlignedRegisters()">;
def HasUnalignedRegisters : Predicate<"Subtarget->hasUnalignedRegisters()">;
diff --git a/llvm/test/TableGen/address-space-patfrags.td b/llvm/test/TableGen/address-space-patfrags.td
index a2e3c1506b65a..0875c88da6f91 100644
--- a/llvm/test/TableGen/address-space-patfrags.td
+++ b/llvm/test/TableGen/address-space-patfrags.td
@@ -104,7 +104,7 @@ def truncstorei16_addrspace : PatFrag<(ops node:$val, node:$ptr),
// GISEL-NEXT: GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
// GISEL-NEXT: GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/123, /*AddrSpace*//* 455(*/0xC7, 0x03/*)*/,
// GISEL-NEXT: // MIs[0] src0
-// GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
+// GISEL-NEXT: GIM_RootCheckType0, /*Type*/GILLT_s32,
diff --git a/llvm/test/TableGen/multiple-type-casts-patfrags.td b/llvm/test/TableGen/multiple-type-casts-patfrags.td
index 39a5b042eaa66..3d048d42ba859 100644
--- a/llvm/test/TableGen/multiple-type-casts-patfrags.td
+++ b/llvm/test/TableGen/multiple-type-casts-patfrags.td
@@ -22,8 +22,8 @@ def INSTR_FOO_I32_I16 : Instruction {
// SDAG: OPC_CheckTypeRes, 1, MVT::i32
// SDAG: OPC_MorphNodeTo2Chain, TARGET_VAL(::INSTR_FOO_I16_I32)
-// GISEL: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16
-// GISEL: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32
+// GISEL: GIM_RootCheckType0, /*Type*/GILLT_s16
+// GISEL: GIM_RootCheckType1, /*Type*/GILLT_s32
// GISEL: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(::INSTR_FOO_I16_I32)
def : Pat<([i16, i32] (int_foo)), ([i16, i32] (INSTR_FOO_I16_I32))>;
@@ -31,7 +31,7 @@ def : Pat<([i16, i32] (int_foo)), ([i16, i32] (INSTR_FOO_I16_I32))>;
// SDAG: OPC_CheckTypeRes, 1, MVT::i16
// SDAG: OPC_MorphNodeTo2Chain, TARGET_VAL(::INSTR_FOO_I32_I16)
-// GISEL: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32
-// GISEL: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16
+// GISEL: GIM_RootCheckType0, /*Type*/GILLT_s32
+// GISEL: GIM_RootCheckType1, /*Type*/GILLT_s16
// GISEL: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(::INSTR_FOO_I32_I16)
def : Pat<([i32, i16] (int_foo)), ([i32, i16] (INSTR_FOO_I32_I16))>;
diff --git a/llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.cpp b/llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.cpp
index cc1089fc316c7..dc810d476b8a6 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.cpp
+++ b/llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.cpp
@@ -960,14 +960,18 @@ bool LLTOperandMatcher::hasValue() const {
}
void LLTOperandMatcher::emitPredicateOpcodes(MatchTable &Table) const {
- if (InsnVarID == 0) {
- Table << MatchTable::Opcode("GIM_RootCheckType");
+ if (InsnVarID == 0 && OpIdx <= 8) {
+ Table << MatchTable::Opcode("GIM_RootCheckType" + llvm::to_string(OpIdx));
} else {
- Table << MatchTable::Opcode("GIM_CheckType") << MatchTable::Comment("MI")
- << MatchTable::ULEB128Value(InsnVarID);
+ if (InsnVarID == 0) {
+ Table << MatchTable::Opcode("GIM_RootCheckType");
+ } else {
+ Table << MatchTable::Opcode("GIM_CheckType") << MatchTable::Comment("MI")
+ << MatchTable::ULEB128Value(InsnVarID);
+ }
+ Table << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx);
}
- Table << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx)
- << MatchTable::Comment("Type") << getValue().Record
+ Table << MatchTable::Comment("Type") << getValue().Record
<< MatchTable::LineBreak;
}
@@ -1026,15 +1030,20 @@ bool RegisterBankOperandMatcher::isIdentical(const PredicateMatcher &B) const {
}
void RegisterBankOperandMatcher::emitPredicateOpcodes(MatchTable &Table) const {
- if (InsnVarID == 0) {
- Table << MatchTable::Opcode("GIM_RootCheckRegBankForClass");
+ if (InsnVarID == 0 && OpIdx <= 8) {
+ Table << MatchTable::Opcode("GIM_RootCheckRegBankForClass" +
+ llvm::to_string(OpIdx));
} else {
- Table << MatchTable::Opcode("GIM_CheckRegBankForClass")
- << MatchTable::Comment("MI") << MatchTable::ULEB128Value(InsnVarID);
+ if (InsnVarID == 0) {
+ Table << MatchTable::Opcode("GIM_RootCheckRegBankForClass");
+ } else {
+ Table << MatchTable::Opcode("GIM_CheckRegBankForClass")
+ << MatchTable::Comment("MI") << MatchTable::ULEB128Value(InsnVarID);
+ }
+ Table << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx);
}
- Table << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx)
- << MatchTable::Comment("RC")
+ Table << MatchTable::Comment("RC")
<< MatchTable::NamedValue(2, RC.getQualifiedIdName())
<< MatchTable::LineBreak;
}
@@ -1680,18 +1689,24 @@ OperandRenderer::~OperandRenderer() = default;
void CopyRenderer::emitRenderOpcodes(MatchTable &Table, unsigned NewInsnID,
unsigned OldInsnID, unsigned OldOpIdx,
StringRef Name, bool ForVariadic) {
- if (!ForVariadic && NewInsnID == 0 && OldInsnID == 0) {
- Table << MatchTable::Opcode("GIR_RootToRootCopy");
+ if (!ForVariadic && NewInsnID == 0 && OldInsnID == 0 && OldOpIdx <= 8) {
+ Table << MatchTable::Opcode("GIR_RootToRootCopy" +
+ llvm::to_string(OldOpIdx));
} else {
- Table << MatchTable::Opcode(ForVariadic ? "GIR_CopyRemaining" : "GIR_Copy")
- << MatchTable::Comment("NewInsnID")
- << MatchTable::ULEB128Value(NewInsnID)
- << MatchTable::Comment("OldInsnID")
- << MatchTable::ULEB128Value(OldInsnID);
+ if (!ForVariadic && NewInsnID == 0 && OldInsnID == 0) {
+ Table << MatchTable::Opcode("GIR_RootToRootCopy");
+ } else {
+ Table << MatchTable::Opcode(ForVariadic ? "GIR_CopyRemaining"
+ : "GIR_Copy")
+ << MatchTable::Comment("NewInsnID")
+ << MatchTable::ULEB128Value(NewInsnID)
+ << MatchTable::Comment("OldInsnID")
+ << MatchTable::ULEB128Value(OldInsnID);
+ }
+ Table << MatchTable::Comment("OpIdx") << MatchTable::ULEB128Value(OldOpIdx);
}
- Table << MatchTable::Comment("OpIdx") << MatchTable::ULEB128Value(OldOpIdx)
- << MatchTable::Comment(Name) << MatchTable::LineBreak;
+ Table << MatchTable::Comment(Name) << MatchTable::LineBreak;
}
void CopyRenderer::emitRenderOpcodes(MatchTable &Table) const {
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