[llvm] [InstCombine] Set nnan on fcmp with known non-NaN operands (PR #210560)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Jul 18 17:26:21 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-transforms
Author: Lucas Ly Ba (lucasly-ba)
<details>
<summary>Changes</summary>
When both operands of an fcmp are known to never be NaN, the comparison cannot involve a NaN, so nnan can be set. This exposes the fact to min/max recognition and lets codegen use the cheaper ordered comparison.
Fixes #<!-- -->199893
---
Patch is 74.04 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/210560.diff
12 Files Affected:
- (modified) llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp (+10)
- (modified) llvm/test/Transforms/InstCombine/cast-int-fcmp-eq-0.ll (+9-9)
- (modified) llvm/test/Transforms/InstCombine/fcmp-denormals-are-zero.ll (+1-1)
- (added) llvm/test/Transforms/InstCombine/fcmp-nnan-known-operands.ll (+48)
- (modified) llvm/test/Transforms/InstCombine/fcmp-select-sign.ll (+15-14)
- (modified) llvm/test/Transforms/InstCombine/fcmp.ll (+21-21)
- (modified) llvm/test/Transforms/InstCombine/fpclass-from-dom-cond.ll (+2-2)
- (modified) llvm/test/Transforms/InstCombine/frexp-implied-exponent-range-dominating-conditions.ll (+76-76)
- (modified) llvm/test/Transforms/InstCombine/is_fpclass.ll (+1-1)
- (modified) llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-exp.ll (+4-4)
- (modified) llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fdiv.ll (+1-1)
- (modified) llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll (+10-10)
``````````diff
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
index 42c2983034e22..0436c5e5b9460 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
@@ -9111,6 +9111,16 @@ Instruction *InstCombinerImpl::visitFCmpInst(FCmpInst &I) {
return replaceOperand(I, 1, ConstantFP::getZero(OpType));
}
+ // If neither operand can be a NaN, the comparison cannot see a NaN, so it is
+ // safe to set 'nnan'. This exposes the fact to min/max recognition and lets
+ // codegen use the cheaper ordered form.
+ if (!I.hasNoNaNs() &&
+ isKnownNeverNaN(Op0, getSimplifyQuery().getWithInstruction(&I)) &&
+ isKnownNeverNaN(Op1, getSimplifyQuery().getWithInstruction(&I))) {
+ I.setHasNoNaNs(true);
+ return &I;
+ }
+
// fcmp pred (fneg X), (fneg Y) -> fcmp swap(pred) X, Y
Value *X, *Y;
if (match(Op0, m_FNeg(m_Value(X))) && match(Op1, m_FNeg(m_Value(Y))))
diff --git a/llvm/test/Transforms/InstCombine/cast-int-fcmp-eq-0.ll b/llvm/test/Transforms/InstCombine/cast-int-fcmp-eq-0.ll
index daf48a6949a42..b2fb8ac33b4b3 100644
--- a/llvm/test/Transforms/InstCombine/cast-int-fcmp-eq-0.ll
+++ b/llvm/test/Transforms/InstCombine/cast-int-fcmp-eq-0.ll
@@ -274,7 +274,7 @@ define i1 @i64_cast_cmp_oeq_int_0_sitofp_half(i64 %i) {
define i1 @i32_cast_cmp_oeq_int_0_uitofp_ppcf128(i32 %i) {
; CHECK-LABEL: @i32_cast_cmp_oeq_int_0_uitofp_ppcf128(
; CHECK-NEXT: [[F:%.*]] = uitofp i32 [[I:%.*]] to ppc_fp128
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq ppc_fp128 [[F]], 0.000000e+00
+; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan oeq ppc_fp128 [[F]], 0.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%f = uitofp i32 %i to ppc_fp128
@@ -314,7 +314,7 @@ define i1 @i32_cast_cmp_oeq_int_i24max_sitofp(i32 %i) {
define i1 @i32_cast_cmp_oeq_int_i24maxp1_uitofp(i32 %i) {
; CHECK-LABEL: @i32_cast_cmp_oeq_int_i24maxp1_uitofp(
; CHECK-NEXT: [[F:%.*]] = uitofp i32 [[I:%.*]] to float
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[F]], f0x4B800000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan oeq float [[F]], f0x4B800000
; CHECK-NEXT: ret i1 [[CMP]]
;
%f = uitofp i32 %i to float
@@ -326,7 +326,7 @@ define i1 @i32_cast_cmp_oeq_int_i24maxp1_uitofp(i32 %i) {
define i1 @i32_cast_cmp_oeq_int_i24maxp1_sitofp(i32 %i) {
; CHECK-LABEL: @i32_cast_cmp_oeq_int_i24maxp1_sitofp(
; CHECK-NEXT: [[F:%.*]] = sitofp i32 [[I:%.*]] to float
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[F]], f0x4B800000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan oeq float [[F]], f0x4B800000
; CHECK-NEXT: ret i1 [[CMP]]
;
%f = sitofp i32 %i to float
@@ -337,7 +337,7 @@ define i1 @i32_cast_cmp_oeq_int_i24maxp1_sitofp(i32 %i) {
define i1 @i32_cast_cmp_oeq_int_i32umax_uitofp(i32 %i) {
; CHECK-LABEL: @i32_cast_cmp_oeq_int_i32umax_uitofp(
; CHECK-NEXT: [[F:%.*]] = uitofp i32 [[I:%.*]] to float
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[F]], f0x4F800000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan oeq float [[F]], f0x4F800000
; CHECK-NEXT: ret i1 [[CMP]]
;
%f = uitofp i32 %i to float
@@ -368,7 +368,7 @@ define i1 @i32_cast_cmp_oeq_int_i32umax_sitofp(i32 %i) {
define i1 @i32_cast_cmp_oeq_int_i32imin_sitofp(i32 %i) {
; CHECK-LABEL: @i32_cast_cmp_oeq_int_i32imin_sitofp(
; CHECK-NEXT: [[F:%.*]] = sitofp i32 [[I:%.*]] to float
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[F]], f0xCF000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan oeq float [[F]], f0xCF000000
; CHECK-NEXT: ret i1 [[CMP]]
;
%f = sitofp i32 %i to float
@@ -379,7 +379,7 @@ define i1 @i32_cast_cmp_oeq_int_i32imin_sitofp(i32 %i) {
define i1 @i32_cast_cmp_oeq_int_i32imax_uitofp(i32 %i) {
; CHECK-LABEL: @i32_cast_cmp_oeq_int_i32imax_uitofp(
; CHECK-NEXT: [[F:%.*]] = uitofp i32 [[I:%.*]] to float
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[F]], f0x4F000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan oeq float [[F]], f0x4F000000
; CHECK-NEXT: ret i1 [[CMP]]
;
%f = uitofp i32 %i to float
@@ -390,7 +390,7 @@ define i1 @i32_cast_cmp_oeq_int_i32imax_uitofp(i32 %i) {
define i1 @i32_cast_cmp_oeq_int_i32imax_sitofp(i32 %i) {
; CHECK-LABEL: @i32_cast_cmp_oeq_int_i32imax_sitofp(
; CHECK-NEXT: [[F:%.*]] = sitofp i32 [[I:%.*]] to float
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[F]], f0x4F000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan oeq float [[F]], f0x4F000000
; CHECK-NEXT: ret i1 [[CMP]]
;
%f = sitofp i32 %i to float
@@ -502,7 +502,7 @@ define i1 @i32_cast_cmp_oeq_int_inf_sitofp(i32 %i) {
define i1 @i128_cast_cmp_oeq_int_inf_uitofp(i128 %i) {
; CHECK-LABEL: @i128_cast_cmp_oeq_int_inf_uitofp(
; CHECK-NEXT: [[F:%.*]] = uitofp i128 [[I:%.*]] to float
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[F]], +inf
+; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan oeq float [[F]], +inf
; CHECK-NEXT: ret i1 [[CMP]]
;
%f = uitofp i128 %i to float
@@ -533,7 +533,7 @@ define <2 x i1> @i32_vec_cast_cmp_oeq_vec_int_n0_sitofp(<2 x i32> %i) {
define <2 x i1> @i32_vec_cast_cmp_oeq_vec_int_i32imax_sitofp(<2 x i32> %i) {
; CHECK-LABEL: @i32_vec_cast_cmp_oeq_vec_int_i32imax_sitofp(
; CHECK-NEXT: [[F:%.*]] = sitofp <2 x i32> [[I:%.*]] to <2 x float>
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq <2 x float> [[F]], splat (float f0x4F000000)
+; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan oeq <2 x float> [[F]], splat (float f0x4F000000)
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
%f = sitofp <2 x i32> %i to <2 x float>
diff --git a/llvm/test/Transforms/InstCombine/fcmp-denormals-are-zero.ll b/llvm/test/Transforms/InstCombine/fcmp-denormals-are-zero.ll
index 670ed619fe04c..46664ff41a94d 100644
--- a/llvm/test/Transforms/InstCombine/fcmp-denormals-are-zero.ll
+++ b/llvm/test/Transforms/InstCombine/fcmp-denormals-are-zero.ll
@@ -13,7 +13,7 @@ define void @denormal_input_preserve_sign_fcmp_olt_smallest_normalized(float %f3
; CHECK-NEXT: store volatile i1 [[CMPF64]], ptr @var, align 1
; CHECK-NEXT: [[CMPF16:%.*]] = fcmp oeq half [[F16:%.*]], 0.000000e+00
; CHECK-NEXT: store volatile i1 [[CMPF16]], ptr @var, align 1
-; CHECK-NEXT: [[CMPF32_FLAGS:%.*]] = fcmp oeq float [[F32]], 0.000000e+00
+; CHECK-NEXT: [[CMPF32_FLAGS:%.*]] = fcmp nnan oeq float [[F32]], 0.000000e+00
; CHECK-NEXT: store volatile i1 [[CMPF32_FLAGS]], ptr @var, align 1
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/InstCombine/fcmp-nnan-known-operands.ll b/llvm/test/Transforms/InstCombine/fcmp-nnan-known-operands.ll
new file mode 100644
index 0000000000000..53bc58ffaeafc
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/fcmp-nnan-known-operands.ll
@@ -0,0 +1,48 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+
+; Both operands come from uitofp, which is never NaN, so the compare gets nnan.
+define i1 @both_uitofp(i32 %x, i32 %y) {
+; CHECK-LABEL: @both_uitofp(
+; CHECK-NEXT: [[FX:%.*]] = uitofp i32 [[X:%.*]] to float
+; CHECK-NEXT: [[FY:%.*]] = uitofp i32 [[Y:%.*]] to float
+; CHECK-NEXT: [[C:%.*]] = fcmp nnan olt float [[FX]], [[FY]]
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %fx = uitofp i32 %x to float
+ %fy = uitofp i32 %y to float
+ %c = fcmp olt float %fx, %fy
+ ret i1 %c
+}
+
+define i1 @sitofp_and_const(i32 %x) {
+; CHECK-LABEL: @sitofp_and_const(
+; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[X:%.*]], 3
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %fx = sitofp i32 %x to double
+ %c = fcmp oge double %fx, 4.000000e+00
+ ret i1 %c
+}
+
+; Negative: generic floating-point operands may be NaN.
+define i1 @generic(float %x, float %y) {
+; CHECK-LABEL: @generic(
+; CHECK-NEXT: [[C:%.*]] = fcmp olt float [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %c = fcmp olt float %x, %y
+ ret i1 %c
+}
+
+; Negative: only one operand is known to be non-NaN.
+define i1 @one_unknown(i32 %x, float %y) {
+; CHECK-LABEL: @one_unknown(
+; CHECK-NEXT: [[FX:%.*]] = uitofp i32 [[X:%.*]] to float
+; CHECK-NEXT: [[C:%.*]] = fcmp ogt float [[Y:%.*]], [[FX]]
+; CHECK-NEXT: ret i1 [[C]]
+;
+ %fx = uitofp i32 %x to float
+ %c = fcmp olt float %fx, %y
+ ret i1 %c
+}
diff --git a/llvm/test/Transforms/InstCombine/fcmp-select-sign.ll b/llvm/test/Transforms/InstCombine/fcmp-select-sign.ll
index ac286040aafa7..bbf6ed6daf804 100644
--- a/llvm/test/Transforms/InstCombine/fcmp-select-sign.ll
+++ b/llvm/test/Transforms/InstCombine/fcmp-select-sign.ll
@@ -207,14 +207,15 @@ define <2 x i1> @fcmp_une_select_vec_mixed_mask_no_fold(<2 x i1> %c0, <2 x i1> %
; CHECK-LABEL: @fcmp_une_select_vec_mixed_mask_no_fold(
; CHECK-NEXT: [[S0:%.*]] = select <2 x i1> [[C0:%.*]], <2 x double> <double 1.000000e+00, double 2.000000e+00>, <2 x double> <double 3.000000e+00, double 4.000000e+00>
; CHECK-NEXT: [[S1:%.*]] = select <2 x i1> [[C1:%.*]], <2 x double> <double 1.000000e+00, double 9.000000e+00>, <2 x double> <double 8.000000e+00, double 4.000000e+00>
-; CHECK-NEXT: [[R:%.*]] = fcmp une <2 x double> [[S0]], [[S1]]
+; CHECK-NEXT: [[R:%.*]] = fcmp nnan une <2 x double> [[S0]], [[S1]]
; CHECK-NEXT: ret <2 x i1> [[R]]
+;
%s0 = select <2 x i1> %c0,
- <2 x double> <double 1.0, double 2.0>,
- <2 x double> <double 3.0, double 4.0>
+ <2 x double> <double 1.0, double 2.0>,
+ <2 x double> <double 3.0, double 4.0>
%s1 = select <2 x i1> %c1,
- <2 x double> <double 1.0, double 9.0>,
- <2 x double> <double 8.0, double 4.0>
+ <2 x double> <double 1.0, double 9.0>,
+ <2 x double> <double 8.0, double 4.0>
%r = fcmp une <2 x double> %s0, %s1
ret <2 x i1> %r
}
@@ -257,7 +258,7 @@ define i1 @fcmp_olt_select_multi_use_no_fold(double %a, double %b) {
; CHECK-NEXT: [[V3:%.*]] = select i1 [[V2]], double -1.000000e+00, double 1.000000e+00
; CHECK-NEXT: call void @use_double(double [[V1]])
; CHECK-NEXT: call void @use_double(double [[V3]])
-; CHECK-NEXT: [[V4:%.*]] = fcmp olt double [[V1]], [[V3]]
+; CHECK-NEXT: [[V4:%.*]] = fcmp nnan olt double [[V1]], [[V3]]
; CHECK-NEXT: ret i1 [[V4]]
;
%v0 = fcmp ult double %b, 0.000000e+00
@@ -396,11 +397,11 @@ define <2 x i1> @icmp_eq_select_vec_cond_no_fold(<2 x i1> %c1, <2 x i1> %c2) {
; CHECK-NEXT: ret <2 x i1> [[R]]
;
%s1 = select <2 x i1> %c1,
- <2 x i32> <i32 1, i32 2>,
- <2 x i32> <i32 3, i32 4>
+ <2 x i32> <i32 1, i32 2>,
+ <2 x i32> <i32 3, i32 4>
%s2 = select <2 x i1> %c2,
- <2 x i32> <i32 1, i32 9>,
- <2 x i32> <i32 8, i32 4>
+ <2 x i32> <i32 1, i32 9>,
+ <2 x i32> <i32 8, i32 4>
%r = icmp eq <2 x i32> %s1, %s2
ret <2 x i1> %r
}
@@ -418,11 +419,11 @@ define <2 x i1> @icmp_eq_mixed_cond_no_fold(<2 x i1> %c1, i1 %c2) {
; CHECK-NEXT: ret <2 x i1> [[R]]
;
%s1 = select <2 x i1> %c1,
- <2 x i32> <i32 1, i32 2>,
- <2 x i32> <i32 3, i32 4>
+ <2 x i32> <i32 1, i32 2>,
+ <2 x i32> <i32 3, i32 4>
%s2 = select i1 %c2,
- <2 x i32> <i32 1, i32 9>,
- <2 x i32> <i32 8, i32 4>
+ <2 x i32> <i32 1, i32 9>,
+ <2 x i32> <i32 8, i32 4>
%r = icmp eq <2 x i32> %s1, %s2
ret <2 x i1> %r
}
diff --git a/llvm/test/Transforms/InstCombine/fcmp.ll b/llvm/test/Transforms/InstCombine/fcmp.ll
index 6c3091afcacaa..7816c623cd349 100644
--- a/llvm/test/Transforms/InstCombine/fcmp.ll
+++ b/llvm/test/Transforms/InstCombine/fcmp.ll
@@ -598,7 +598,7 @@ define i1 @is_signbit_set(double %x) {
define i1 @is_signbit_set_1(double %x) {
; CHECK-LABEL: @is_signbit_set_1(
; CHECK-NEXT: [[S:%.*]] = call double @llvm.copysign.f64(double 1.000000e+00, double [[X:%.*]])
-; CHECK-NEXT: [[R:%.*]] = fcmp ult double [[S]], 0.000000e+00
+; CHECK-NEXT: [[R:%.*]] = fcmp nnan ult double [[S]], 0.000000e+00
; CHECK-NEXT: ret i1 [[R]]
;
%s = call double @llvm.copysign.f64(double 1.0, double %x)
@@ -609,7 +609,7 @@ define i1 @is_signbit_set_1(double %x) {
define i1 @is_signbit_set_2(double %x) {
; CHECK-LABEL: @is_signbit_set_2(
; CHECK-NEXT: [[S:%.*]] = call double @llvm.copysign.f64(double 1.000000e+00, double [[X:%.*]])
-; CHECK-NEXT: [[R:%.*]] = fcmp ole double [[S]], 0.000000e+00
+; CHECK-NEXT: [[R:%.*]] = fcmp nnan ole double [[S]], 0.000000e+00
; CHECK-NEXT: ret i1 [[R]]
;
%s = call double @llvm.copysign.f64(double 1.0, double %x)
@@ -620,7 +620,7 @@ define i1 @is_signbit_set_2(double %x) {
define i1 @is_signbit_set_3(double %x) {
; CHECK-LABEL: @is_signbit_set_3(
; CHECK-NEXT: [[S:%.*]] = call double @llvm.copysign.f64(double 1.000000e+00, double [[X:%.*]])
-; CHECK-NEXT: [[R:%.*]] = fcmp ule double [[S]], 0.000000e+00
+; CHECK-NEXT: [[R:%.*]] = fcmp nnan ule double [[S]], 0.000000e+00
; CHECK-NEXT: ret i1 [[R]]
;
%s = call double @llvm.copysign.f64(double 1.0, double %x)
@@ -646,7 +646,7 @@ define <2 x i1> @is_signbit_set_anyzero(<2 x double> %x) {
define i1 @is_signbit_clear(double %x) {
; CHECK-LABEL: @is_signbit_clear(
; CHECK-NEXT: [[S:%.*]] = call double @llvm.copysign.f64(double 4.200000e+01, double [[X:%.*]])
-; CHECK-NEXT: [[R:%.*]] = fcmp ogt double [[S]], 0.000000e+00
+; CHECK-NEXT: [[R:%.*]] = fcmp nnan ogt double [[S]], 0.000000e+00
; CHECK-NEXT: ret i1 [[R]]
;
%s = call double @llvm.copysign.f64(double -42.0, double %x)
@@ -657,7 +657,7 @@ define i1 @is_signbit_clear(double %x) {
define i1 @is_signbit_clear_1(double %x) {
; CHECK-LABEL: @is_signbit_clear_1(
; CHECK-NEXT: [[S:%.*]] = call double @llvm.copysign.f64(double 4.200000e+01, double [[X:%.*]])
-; CHECK-NEXT: [[R:%.*]] = fcmp ugt double [[S]], 0.000000e+00
+; CHECK-NEXT: [[R:%.*]] = fcmp nnan ugt double [[S]], 0.000000e+00
; CHECK-NEXT: ret i1 [[R]]
;
%s = call double @llvm.copysign.f64(double -42.0, double %x)
@@ -668,7 +668,7 @@ define i1 @is_signbit_clear_1(double %x) {
define i1 @is_signbit_clear_2(double %x) {
; CHECK-LABEL: @is_signbit_clear_2(
; CHECK-NEXT: [[S:%.*]] = call double @llvm.copysign.f64(double 4.200000e+01, double [[X:%.*]])
-; CHECK-NEXT: [[R:%.*]] = fcmp oge double [[S]], 0.000000e+00
+; CHECK-NEXT: [[R:%.*]] = fcmp nnan oge double [[S]], 0.000000e+00
; CHECK-NEXT: ret i1 [[R]]
;
%s = call double @llvm.copysign.f64(double -42.0, double %x)
@@ -679,7 +679,7 @@ define i1 @is_signbit_clear_2(double %x) {
define i1 @is_signbit_clear_3(double %x) {
; CHECK-LABEL: @is_signbit_clear_3(
; CHECK-NEXT: [[S:%.*]] = call double @llvm.copysign.f64(double 4.200000e+01, double [[X:%.*]])
-; CHECK-NEXT: [[R:%.*]] = fcmp uge double [[S]], 0.000000e+00
+; CHECK-NEXT: [[R:%.*]] = fcmp nnan uge double [[S]], 0.000000e+00
; CHECK-NEXT: ret i1 [[R]]
;
%s = call double @llvm.copysign.f64(double -42.0, double %x)
@@ -693,7 +693,7 @@ define i1 @is_signbit_set_extra_use(double %x, ptr %p) {
; CHECK-LABEL: @is_signbit_set_extra_use(
; CHECK-NEXT: [[S:%.*]] = call double @llvm.copysign.f64(double 1.000000e+00, double [[X:%.*]])
; CHECK-NEXT: store double [[S]], ptr [[P:%.*]], align 8
-; CHECK-NEXT: [[R:%.*]] = fcmp olt double [[S]], 0.000000e+00
+; CHECK-NEXT: [[R:%.*]] = fcmp nnan olt double [[S]], 0.000000e+00
; CHECK-NEXT: ret i1 [[R]]
;
%s = call double @llvm.copysign.f64(double 1.0, double %x)
@@ -707,7 +707,7 @@ define i1 @is_signbit_set_extra_use(double %x, ptr %p) {
define i1 @is_signbit_clear_nonzero(double %x) {
; CHECK-LABEL: @is_signbit_clear_nonzero(
; CHECK-NEXT: [[S:%.*]] = call double @llvm.copysign.f64(double 4.200000e+01, double [[X:%.*]])
-; CHECK-NEXT: [[R:%.*]] = fcmp ogt double [[S]], 1.000000e+00
+; CHECK-NEXT: [[R:%.*]] = fcmp nnan ogt double [[S]], 1.000000e+00
; CHECK-NEXT: ret i1 [[R]]
;
%s = call double @llvm.copysign.f64(double -42.0, double %x)
@@ -1852,7 +1852,7 @@ define i1 @same_const_sub_no_fold_large_c(i32 %x) {
; CHECK-LABEL: @same_const_sub_no_fold_large_c(
; CHECK-NEXT: [[F:%.*]] = sitofp i32 [[X:%.*]] to float
; CHECK-NEXT: [[S:%.*]] = fsub float f0x4BFFFFFF, [[F]]
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[S]], f0x4BFFFFFF
+; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan oeq float [[S]], f0x4BFFFFFF
; CHECK-NEXT: ret i1 [[CMP]]
;
%f = sitofp i32 %x to float
@@ -1889,7 +1889,7 @@ define i1 @same_const_sub_no_fold_subnormal_c(i32 %x) {
; CHECK-LABEL: @same_const_sub_no_fold_subnormal_c(
; CHECK-NEXT: [[F:%.*]] = sitofp i32 [[X:%.*]] to float
; CHECK-NEXT: [[S:%.*]] = fsub float 1.401300e-45, [[F]]
-; CHECK-NEXT: [[CMP:%.*]] = fcmp olt float [[S]], 1.401300e-45
+; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan olt float [[S]], 1.401300e-45
; CHECK-NEXT: ret i1 [[CMP]]
;
%f = sitofp i32 %x to float
@@ -1902,7 +1902,7 @@ define i1 @same_const_sub_no_fold_wrong_mantissa_width(i32 %x) {
; CHECK-LABEL: @same_const_sub_no_fold_wrong_mantissa_width(
; CHECK-NEXT: [[F:%.*]] = sitofp i32 [[X:%.*]] to float
; CHECK-NEXT: [[S:%.*]] = fsub float f0x4C000000, [[F]]
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[S]], f0x4C000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan oeq float [[S]], f0x4C000000
; CHECK-NEXT: ret i1 [[CMP]]
;
%f = sitofp i32 %x to float
@@ -1926,7 +1926,7 @@ define i1 @same_const_sub_no_fold_x86_fp80_large_c(i32 %x) {
; CHECK-LABEL: @same_const_sub_no_fold_x86_fp80_large_c(
; CHECK-NEXT: [[F:%.*]] = sitofp i32 [[X:%.*]] to x86_fp80
; CHECK-NEXT: [[S:%.*]] = fsub x86_fp80 f0x403F8000000000000000, [[F]]
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq x86_fp80 [[S]], f0x403F8000000000000000
+; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan oeq x86_fp80 [[S]], f0x403F8000000000000000
; CHECK-NEXT: ret i1 [[CMP]]
;
%f = sitofp i32 %x to x86_fp80
@@ -1940,7 +1940,7 @@ define i1 @same_const_sub_no_fold_ppcfp128(i32 %x) {
; CHECK-LABEL: @same_const_sub_no_fold_ppcfp128(
; CHECK-NEXT: [[F:%.*]] = sitofp i32 [[X:%.*]] to ppc_fp128
; CHECK-NEXT: [[S:%.*]] = fsub ppc_fp128 1.000000e+00, [[F]]
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq ppc_fp128 [[S]], 1.000000e+00
+; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan oeq ppc_fp128 [[S]], 1.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%f = sitofp i32 %x to ppc_fp128
@@ -2627,7 +2627,7 @@ define i1 @fabs_uitofp_sub_ule_one(i16 %x, i16 %y) {
; CHECK-NEXT: [[FY:%.*]] = uitofp i16 [[Y:%.*]] to float
; CHECK-NEXT: [[SUB:%.*]] = fsub float [[FX]], [[FY]]
; CHECK-NEXT: [[ABS:%.*]] = call float @llvm.fabs.f32(float [[SUB]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ule float [[ABS]], 1.000000e+00
+; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan ule float [[ABS]], 1.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%fx = uitofp i16 %x to float
@@ -2644,7 +2644,7 @@ define i1 @fabs_sitofp_sub_ole_one(i16 %x, i16 %y) {
; CHECK-NEXT: [[FY:%.*]] = sitofp i16 [[Y:%.*]] to float
; CHECK-NEXT: [[SUB:%.*]] = fsub float [[FX]], [[FY]]
; CHECK-NEXT: [[ABS:%.*]] = call float @llvm.fabs.f32(float [[SUB]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ole float [[ABS]], 1.000000e+00
+; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan ole float [[ABS]], 1.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%fx = sitofp i16 %x to float
@@ -2689,7 +2689,7 @@ define i1 @fabs_uitofp_sub_olt_two_no_fold(i16 %x, i16 %y) {
; CHECK-NEXT: [[FY:%.*]] = uitofp i16 [[Y:%.*]] to float
; CHECK-NEXT: [[SUB:%.*]] = fsub float [[FX]], [[FY]]
; CHECK-NEXT: [[ABS:%.*]] = call float @llvm.fabs.f32(float [[SUB]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp olt float [[ABS]], 2.000000e+00
+; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan olt float [[ABS]], 2.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%fx = uitofp i16 %x to float
@@ -2706,7 +2706,7 @@ define i1 @fabs_sitofp_sub_olt_one_i32_no_fold(i32 %x, i32 %y) {
; CHECK-NEXT: [[FY:%.*]] = sitofp i32 [[Y:%.*]] to float
; CHECK-NEXT: [[SUB:%.*]] = fsub float [[FX]], [[FY]]
; CHECK-NEXT: [[ABS:%.*]] = call float @llvm.fabs.f32(float [[SUB]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp olt float [[ABS]], 1.000000e+00
+; CHECK-NEXT: [[CMP:%.*]] = fcmp nnan olt float [[ABS]], 1.000000e+00
; CHECK-NEXT: ret i1 [[CMP]]
;
%fx = sitofp i32 %x to float
@@ -2724,7 +2724,7 @@ define i1 @fabs_sitofp_sub_ogt_one(i16 %x, i16 %y) {
; CHECK-NEXT: [[FY:%.*]] = sitofp i16 [[Y:%.*]] to float
; CHECK-NEXT: [[SUB:%.*]] = fsub float [[FX]], [[FY]]
; CHECK-NEXT: [[ABS:%.*]] = call float @llvm.fabs.f32(float [[SUB]])
-; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[ABS]], 1.000000e+00
+; CHECK-NEXT: [[CMP:%.*]] = fcmp nna...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/210560
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