[llvm] [AMDGPU] merge 16bit mov pairs in post-RA peephole (PR #208625)

[Guo Chen via llvm-commits]

broxigarchen wrote:

> LGTM thanks, just some minor nits.
> 
> Have you done any correctness testing e.g. with Vulkan CTS?

Hi Jay. I realized that moving inst upward could hit problems with mem hazard, i.e.
```
%1.l = v_mov_b16 %0.l
%2 = global_load_b32 xxx
waitcnt vmcnt
%3 = xxxxx %2
%1.h = v_mov_b16 %2.l

to

%2 = global_load_b32 xxx
%1 = v_pack_b32 %0.l, %2  (This is moved across waitcnt)
waitcnt vmcnt
%3 = xxxxx %2
```

The peephole pass run after the waitcnt pass, so the exisiting waitcnt could be break.

A few options I can think of:
1. Only insert at the SecondMI location so only move downward
2. track all mem hazzard in the sliding window. Set up propper lower/upper bound or modify existing waitcnt
3. run peephole pass before waitcnt pass

Do you have any suggestion on this? Thanks!


https://github.com/llvm/llvm-project/pull/208625