[llvm] [SelectionDAG] Add computeKnownBits support for ISD::VECREDUCE_ADD (PR #207631)

[Sabona Abdi via llvm-commits]

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@@ -73,29 +103,61 @@ entry:
 }
 
 define signext i16 @sad_16x8_as_i16(<16 x i8> %a, <16 x i8> %b) {
-; CHECK-LABEL: sad_16x8_as_i16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetivli zero, 16, e16, m1, ta, ma
-; CHECK-NEXT:    vmv.s.x v10, zero
-; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT:    vminu.vv v11, v8, v9
-; CHECK-NEXT:    vmaxu.vv v8, v8, v9
-; CHECK-NEXT:    vsub.vv v8, v8, v11
-; CHECK-NEXT:    vwredsumu.vs v8, v8, v10
-; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    ret
+; RV32-LABEL: sad_16x8_as_i16:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    vsetivli zero, 16, e16, m1, ta, ma
+; RV32-NEXT:    vmv.s.x v10, zero
+; RV32-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; RV32-NEXT:    vminu.vv v11, v8, v9
+; RV32-NEXT:    vmaxu.vv v8, v8, v9
+; RV32-NEXT:    vsub.vv v8, v8, v11
+; RV32-NEXT:    vwredsumu.vs v8, v8, v10
+; RV32-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
+; RV32-NEXT:    vmv.x.s a0, v8
+; RV32-NEXT:    slli a0, a0, 20
+; RV32-NEXT:    srli a0, a0, 20
+; RV32-NEXT:    ret
 ;
-; ZVABD-LABEL: sad_16x8_as_i16:
-; ZVABD:       # %bb.0: # %entry
-; ZVABD-NEXT:    vsetivli zero, 16, e16, m1, ta, ma
-; ZVABD-NEXT:    vmv.s.x v10, zero
-; ZVABD-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
-; ZVABD-NEXT:    vabdu.vv v8, v8, v9
-; ZVABD-NEXT:    vwredsumu.vs v8, v8, v10
-; ZVABD-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
-; ZVABD-NEXT:    vmv.x.s a0, v8
-; ZVABD-NEXT:    ret
+; RV64-LABEL: sad_16x8_as_i16:
+; RV64:       # %bb.0: # %entry
+; RV64-NEXT:    vsetivli zero, 16, e16, m1, ta, ma
+; RV64-NEXT:    vmv.s.x v10, zero
+; RV64-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; RV64-NEXT:    vminu.vv v11, v8, v9
+; RV64-NEXT:    vmaxu.vv v8, v8, v9
+; RV64-NEXT:    vsub.vv v8, v8, v11
+; RV64-NEXT:    vwredsumu.vs v8, v8, v10
+; RV64-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
+; RV64-NEXT:    vmv.x.s a0, v8
+; RV64-NEXT:    slli a0, a0, 52
+; RV64-NEXT:    srli a0, a0, 52
+; RV64-NEXT:    ret
+;
+; RV32ZVABD-LABEL: sad_16x8_as_i16:
+; RV32ZVABD:       # %bb.0: # %entry
+; RV32ZVABD-NEXT:    vsetivli zero, 16, e16, m1, ta, ma
+; RV32ZVABD-NEXT:    vmv.s.x v10, zero
+; RV32ZVABD-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; RV32ZVABD-NEXT:    vabdu.vv v8, v8, v9
+; RV32ZVABD-NEXT:    vwredsumu.vs v8, v8, v10
+; RV32ZVABD-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
+; RV32ZVABD-NEXT:    vmv.x.s a0, v8
+; RV32ZVABD-NEXT:    slli a0, a0, 20
+; RV32ZVABD-NEXT:    srli a0, a0, 20
+; RV32ZVABD-NEXT:    ret
+;
+; RV64ZVABD-LABEL: sad_16x8_as_i16:
+; RV64ZVABD:       # %bb.0: # %entry
+; RV64ZVABD-NEXT:    vsetivli zero, 16, e16, m1, ta, ma
+; RV64ZVABD-NEXT:    vmv.s.x v10, zero
+; RV64ZVABD-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; RV64ZVABD-NEXT:    vabdu.vv v8, v8, v9
+; RV64ZVABD-NEXT:    vwredsumu.vs v8, v8, v10
+; RV64ZVABD-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVABD-NEXT:    vmv.x.s a0, v8
+; RV64ZVABD-NEXT:    slli a0, a0, 52
+; RV64ZVABD-NEXT:    srli a0, a0, 52
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sabonaoabdi wrote:

I added the new case (#210493) but the slli/srli pair persisted. I traced it further and added cases for the following nodes: `RISCVISD::VMV_X_S`, `RISCVISD::VMV_S_X_VL`, `RISCVISD::VZEXT_VL`, `RISCVISD::VWADDU_VL`, and `RISCVISD::SUB_VL`. This removed the slli/srli pair across the file, and additionally dropped a pre-existing `andi a0, a0, 1023` instruction fin some of the 4 element cases (e.g. line 94). It turned out to be redudant due to vmv.x.s's sign extension guarantee. 

It's a much bigger change than the original case. Let me know if I split it into separate issues/PRs or other ways this should be scoped.

https://github.com/llvm/llvm-project/pull/207631