[llvm] [RISCV] computeKnownBits - add support for RISCVISD::VECREDUCE_ADD_VL (PR #210493)
Sabona Abdi via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 17 23:59:28 PDT 2026
https://github.com/sabonaoabdi created https://github.com/llvm/llvm-project/pull/210493
[RISCV] Add computeKnownBits support for RISCVISD::VECREDUCE_ADD_VL
Stacked on #207631, only the last commit on this branch is new.
## Summary
Adds a computeKnownBitsForTargetNode case for RISCVISD::VECREDUCE_ADD_VL,
complementing the generic ISD::VECREDUCE_ADD case from #207631, which
bails out for scalable vectors. Bounds the element count from the VL operand — exact if constant,
otherwise a conservative bound via computeVLMAXBounds — and feeds it
into KnownBits::reduceAdd, folding in the accumulator via
KnownBits::add.
>From 62178b956c369249fe10080b645139c9ee6198b4 Mon Sep 17 00:00:00 2001
From: sabonaoabdi <sabonaoabdi at gmail.com>
Date: Thu, 9 Jul 2026 20:05:35 -0500
Subject: [PATCH 1/4] [SelectionDAG] Add baseline test coverage for
VECREDUCE_ADD known bits
---
.../AArch64/vecreduce-add-knownbits-sve.ll | 18 +++++
.../AArch64/vecreduce-add-knownbits.ll | 80 +++++++++++++++++++
2 files changed, 98 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/vecreduce-add-knownbits-sve.ll
create mode 100644 llvm/test/CodeGen/AArch64/vecreduce-add-knownbits.ll
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-add-knownbits-sve.ll b/llvm/test/CodeGen/AArch64/vecreduce-add-knownbits-sve.ll
new file mode 100644
index 0000000000000..92ed0b29c120e
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/vecreduce-add-knownbits-sve.ll
@@ -0,0 +1,18 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+sve | FileCheck %s --check-prefix=CHECK
+
+define i64 @vreduce_add_scalable_nxv4i32(<vscale x 4 x i32> %v) nounwind {
+; CHECK-LABEL: vreduce_add_scalable_nxv4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: and z0.s, z0.s, #0xff
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: uaddv d0, p0, z0.s
+; CHECK-NEXT: fmov x8, d0
+; CHECK-NEXT: and x0, x8, #0xffff
+; CHECK-NEXT: ret
+ %masked = and <vscale x 4 x i32> %v, splat (i32 255)
+ %sum = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %masked)
+ %narrow = trunc i32 %sum to i16
+ %wide = zext i16 %narrow to i64
+ ret i64 %wide
+}
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-add-knownbits.ll b/llvm/test/CodeGen/AArch64/vecreduce-add-knownbits.ll
new file mode 100644
index 0000000000000..eae995848ae76
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/vecreduce-add-knownbits.ll
@@ -0,0 +1,80 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
+
+define i64 @vreduce_add_assertzext_v4i32(<4 x i32> %v) nounwind {
+; CHECK-LABEL: vreduce_add_assertzext_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v1.2d, #0x0000ff000000ff
+; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: addv s0, v0.4s
+; CHECK-NEXT: fmov w8, s0
+; CHECK-NEXT: and x0, x8, #0xffff
+; CHECK-NEXT: ret
+ %masked = and <4 x i32> %v, <i32 255, i32 255, i32 255, i32 255>
+ %sum = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %masked)
+ %narrow = trunc i32 %sum to i16
+ %wide = zext i16 %narrow to i64
+ ret i64 %wide
+}
+
+define i64 @vreduce_add_knownbits_v16i32(<16 x i32> %v) nounwind {
+; CHECK-LABEL: vreduce_add_knownbits_v16i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v4.2d, #0x0000ff000000ff
+; CHECK-NEXT: and v2.16b, v2.16b, v4.16b
+; CHECK-NEXT: and v0.16b, v0.16b, v4.16b
+; CHECK-NEXT: and v3.16b, v3.16b, v4.16b
+; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
+; CHECK-NEXT: add v0.4s, v0.4s, v2.4s
+; CHECK-NEXT: add v1.4s, v1.4s, v3.4s
+; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: addv s0, v0.4s
+; CHECK-NEXT: fmov w8, s0
+; CHECK-NEXT: and x0, x8, #0xffff
+; CHECK-NEXT: ret
+ %masked = and <16 x i32> %v, splat (i32 255)
+ %sum = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %masked)
+ %narrow = trunc i32 %sum to i16
+ %wide = zext i16 %narrow to i64
+ ret i64 %wide
+}
+
+define i64 @vreduce_add_knownbits_v8i16(<8 x i16> %v) nounwind {
+; CHECK-LABEL: vreduce_add_knownbits_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v1.8h, #15
+; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: addv h0, v0.8h
+; CHECK-NEXT: umov w0, v0.h[0]
+; CHECK-NEXT: ret
+ %masked = and <8 x i16> %v, splat (i16 15)
+ %sum = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %masked)
+ %wide = zext i16 %sum to i64
+ ret i64 %wide
+}
+
+define i64 @vreduce_add_noknownbits_v4i32(<4 x i32> %v) nounwind {
+; CHECK-LABEL: vreduce_add_noknownbits_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: addv s0, v0.4s
+; CHECK-NEXT: fmov w8, s0
+; CHECK-NEXT: and x0, x8, #0xffff
+; CHECK-NEXT: ret
+ %sum = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %v)
+ %narrow = trunc i32 %sum to i16
+ %wide = zext i16 %narrow to i64
+ ret i64 %wide
+}
+
+define i64 @vreduce_add_knownbits_signed_v4i32(<4 x i32> %v) nounwind {
+; CHECK-LABEL: vreduce_add_knownbits_signed_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sshr v0.4s, v0.4s, #28
+; CHECK-NEXT: addv s0, v0.4s
+; CHECK-NEXT: smov x0, v0.s[0]
+; CHECK-NEXT: ret
+ %shifted = ashr <4 x i32> %v, splat (i32 28)
+ %sum = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %shifted)
+ %wide = sext i32 %sum to i64
+ ret i64 %wide
+}
>From 076071fa966ac052ee567dae99e11d1bc3abdb03 Mon Sep 17 00:00:00 2001
From: sabonaoabdi <sabonaoabdi at gmail.com>
Date: Thu, 9 Jul 2026 20:14:18 -0500
Subject: [PATCH 2/4] [SelectionDAG] Add computeKnownBits support for
ISD::VECREDUCE_ADD
---
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 12 +
.../CodeGen/AArch64/sve-vector-compress.ll | 7 +-
.../AArch64/vecreduce-add-knownbits.ll | 9 +-
llvm/test/CodeGen/AArch64/vecreduce-add.ll | 18 +-
.../CodeGen/RISCV/rvv/fixed-vectors-sad.ll | 887 +++++++++++++-----
llvm/test/CodeGen/X86/vector-compress.ll | 44 +-
6 files changed, 718 insertions(+), 259 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 626803ed92a40..7cb812ce7e46f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -3578,6 +3578,18 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
break;
}
+ case ISD::VECREDUCE_ADD: {
+ SDValue Src = Op.getOperand(0);
+ if (Src.getValueType().isScalableVector())
+ break;
+
+ unsigned NumElts = Src.getValueType().getVectorNumElements();
+ KnownBits KnownAcrossElts =
+ computeKnownBits(Src, APInt::getAllOnes(NumElts), Depth + 1);
+ Known = KnownAcrossElts.reduceAdd(NumElts);
+ Known = Known.anyext(Op.getScalarValueSizeInBits());
+ break;
+ }
case ISD::BITCAST: {
if (Op.getValueType().isScalableVector())
break;
diff --git a/llvm/test/CodeGen/AArch64/sve-vector-compress.ll b/llvm/test/CodeGen/AArch64/sve-vector-compress.ll
index 8e15385b5783b..e729ecbbc7a82 100644
--- a/llvm/test/CodeGen/AArch64/sve-vector-compress.ll
+++ b/llvm/test/CodeGen/AArch64/sve-vector-compress.ll
@@ -284,15 +284,14 @@ define <4 x double> @test_compress_v4f64_with_sve(<4 x double> %vec, <4 x i1> %m
; CHECK-NEXT: ushll2 v5.2d, v2.4s, #0
; CHECK-NEXT: and v2.8b, v2.8b, v4.8b
; CHECK-NEXT: shl v3.2d, v3.2d, #63
-; CHECK-NEXT: shl v4.2d, v5.2d, #63
+; CHECK-NEXT: shl v5.2d, v5.2d, #63
; CHECK-NEXT: addp v2.2s, v2.2s, v2.2s
; CHECK-NEXT: cmpne p1.d, p0/z, z3.d, #0
-; CHECK-NEXT: cmpne p2.d, p0/z, z4.d, #0
+; CHECK-NEXT: cmpne p2.d, p0/z, z5.d, #0
; CHECK-NEXT: fmov w8, s2
; CHECK-NEXT: compact z0.d, p1, z0.d
-; CHECK-NEXT: and x8, x8, #0x3
; CHECK-NEXT: compact z1.d, p2, z1.d
-; CHECK-NEXT: lsl x8, x8, #3
+; CHECK-NEXT: ubfiz x8, x8, #3, #32
; CHECK-NEXT: str q0, [sp]
; CHECK-NEXT: str q1, [x9, x8]
; CHECK-NEXT: ldp q0, q1, [sp], #32
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-add-knownbits.ll b/llvm/test/CodeGen/AArch64/vecreduce-add-knownbits.ll
index eae995848ae76..d2599f0933c9f 100644
--- a/llvm/test/CodeGen/AArch64/vecreduce-add-knownbits.ll
+++ b/llvm/test/CodeGen/AArch64/vecreduce-add-knownbits.ll
@@ -7,8 +7,7 @@ define i64 @vreduce_add_assertzext_v4i32(<4 x i32> %v) nounwind {
; CHECK-NEXT: movi v1.2d, #0x0000ff000000ff
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: addv s0, v0.4s
-; CHECK-NEXT: fmov w8, s0
-; CHECK-NEXT: and x0, x8, #0xffff
+; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
%masked = and <4 x i32> %v, <i32 255, i32 255, i32 255, i32 255>
%sum = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %masked)
@@ -29,8 +28,7 @@ define i64 @vreduce_add_knownbits_v16i32(<16 x i32> %v) nounwind {
; CHECK-NEXT: add v1.4s, v1.4s, v3.4s
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: addv s0, v0.4s
-; CHECK-NEXT: fmov w8, s0
-; CHECK-NEXT: and x0, x8, #0xffff
+; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
%masked = and <16 x i32> %v, splat (i32 255)
%sum = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %masked)
@@ -45,7 +43,8 @@ define i64 @vreduce_add_knownbits_v8i16(<8 x i16> %v) nounwind {
; CHECK-NEXT: movi v1.8h, #15
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: addv h0, v0.8h
-; CHECK-NEXT: umov w0, v0.h[0]
+; CHECK-NEXT: fmov w8, s0
+; CHECK-NEXT: and x0, x8, #0x7f
; CHECK-NEXT: ret
%masked = and <8 x i16> %v, splat (i16 15)
%sum = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %masked)
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-add.ll b/llvm/test/CodeGen/AArch64/vecreduce-add.ll
index 995bf28060e8d..f7000e33b4d5d 100644
--- a/llvm/test/CodeGen/AArch64/vecreduce-add.ll
+++ b/llvm/test/CodeGen/AArch64/vecreduce-add.ll
@@ -514,9 +514,9 @@ entry:
define zeroext i16 @add_v16i8_v16i16_zext(<16 x i8> %x) {
; CHECK-SD-LABEL: add_v16i8_v16i16_zext:
; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: uaddlp v0.8h, v0.16b
-; CHECK-SD-NEXT: addv h0, v0.8h
-; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: uaddlv h0, v0.16b
+; CHECK-SD-NEXT: fmov w8, s0
+; CHECK-SD-NEXT: and w0, w8, #0xfff
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: add_v16i8_v16i16_zext:
@@ -554,9 +554,9 @@ entry:
define zeroext i16 @add_v8i8_v8i16_zext(<8 x i8> %x) {
; CHECK-SD-LABEL: add_v8i8_v8i16_zext:
; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-SD-NEXT: addv h0, v0.8h
-; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: uaddlv h0, v0.8b
+; CHECK-SD-NEXT: fmov w8, s0
+; CHECK-SD-NEXT: and w0, w8, #0x7ff
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: add_v8i8_v8i16_zext:
@@ -3000,7 +3000,8 @@ define zeroext i16 @add_pair_v16i8_v16i16_zext(<16 x i8> %x, <16 x i8> %y) {
; CHECK-SD-NEXT: uaddlp v1.8h, v1.16b
; CHECK-SD-NEXT: uadalp v1.8h, v0.16b
; CHECK-SD-NEXT: addv h0, v1.8h
-; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: fmov w8, s0
+; CHECK-SD-NEXT: and w0, w8, #0x1fff
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: add_pair_v16i8_v16i16_zext:
@@ -3055,7 +3056,8 @@ define zeroext i16 @add_pair_v8i8_v8i16_zext(<8 x i8> %x, <8 x i8> %y) {
; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
; CHECK-SD-NEXT: uaddlv h0, v0.16b
-; CHECK-SD-NEXT: umov w0, v0.h[0]
+; CHECK-SD-NEXT: umov w8, v0.h[0]
+; CHECK-SD-NEXT: and w0, w8, #0xfff
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: add_pair_v8i8_v8i16_zext:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
index e2c85e58cd34a..cd9d4efe3c09f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc < %s -mtriple=riscv32 -mattr=+v | FileCheck %s
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s
-; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+experimental-zvabd | FileCheck %s --check-prefix=ZVABD
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+experimental-zvabd | FileCheck %s --check-prefix=ZVABD
+; RUN: llc < %s -mtriple=riscv32 -mattr=+v | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s --check-prefixes=CHECK,RV64
+; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+experimental-zvabd | FileCheck %s --check-prefixes=ZVABD,RV32ZVABD
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+experimental-zvabd | FileCheck %s --check-prefixes=ZVABD,RV64ZVABD
define signext i16 @sad_4x8_as_i16(<4 x i8> %a, <4 x i8> %b) {
; CHECK-LABEL: sad_4x8_as_i16:
@@ -16,6 +16,7 @@ define signext i16 @sad_4x8_as_i16(<4 x i8> %a, <4 x i8> %b) {
; CHECK-NEXT: vwredsumu.vs v8, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: andi a0, a0, 1023
; CHECK-NEXT: ret
;
; ZVABD-LABEL: sad_4x8_as_i16:
@@ -27,6 +28,7 @@ define signext i16 @sad_4x8_as_i16(<4 x i8> %a, <4 x i8> %b) {
; ZVABD-NEXT: vwredsumu.vs v8, v8, v10
; ZVABD-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVABD-NEXT: vmv.x.s a0, v8
+; ZVABD-NEXT: andi a0, a0, 1023
; ZVABD-NEXT: ret
entry:
%1 = zext <4 x i8> %a to <4 x i16>
@@ -38,31 +40,82 @@ entry:
}
define signext i32 @sad_4x8_as_i32(<4 x i8> %a, <4 x i8> %b) {
-; CHECK-LABEL: sad_4x8_as_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmv.s.x v10, zero
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vminu.vv v11, v8, v9
-; CHECK-NEXT: vmaxu.vv v8, v8, v9
-; CHECK-NEXT: vsub.vv v8, v8, v11
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vzext.vf4 v9, v8
-; CHECK-NEXT: vredsum.vs v8, v9, v10
-; CHECK-NEXT: vmv.x.s a0, v8
-; CHECK-NEXT: ret
+; RV32-LABEL: sad_4x8_as_i32:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; RV32-NEXT: vmv.s.x v10, zero
+; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; RV32-NEXT: vminu.vv v11, v8, v9
+; RV32-NEXT: vmaxu.vv v8, v8, v9
+; RV32-NEXT: vsub.vv v8, v8, v11
+; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32-NEXT: vzext.vf4 v9, v8
+; RV32-NEXT: vredsum.vs v8, v9, v10
+; RV32-NEXT: vmv.x.s a0, v8
+; RV32-NEXT: ret
;
-; ZVABD-LABEL: sad_4x8_as_i32:
-; ZVABD: # %bb.0: # %entry
-; ZVABD-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVABD-NEXT: vmv.s.x v10, zero
-; ZVABD-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; ZVABD-NEXT: vabdu.vv v8, v8, v9
-; ZVABD-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVABD-NEXT: vzext.vf4 v9, v8
-; ZVABD-NEXT: vredsum.vs v8, v9, v10
-; ZVABD-NEXT: vmv.x.s a0, v8
-; ZVABD-NEXT: ret
+; RV64-LABEL: sad_4x8_as_i32:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; RV64-NEXT: vmv.s.x v10, zero
+; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; RV64-NEXT: vminu.vv v11, v8, v9
+; RV64-NEXT: vmaxu.vv v8, v8, v9
+; RV64-NEXT: vsub.vv v8, v8, v11
+; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-NEXT: vzext.vf4 v9, v8
+; RV64-NEXT: vredsum.vs v8, v9, v10
+; RV64-NEXT: vmv.x.s a0, v8
+; RV64-NEXT: andi a0, a0, 1023
+; RV64-NEXT: ret
+;
+; RV32ZVABD-LABEL: sad_4x8_as_i32:
+; RV32ZVABD: # %bb.0: # %entry
+; RV32ZVABD-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; RV32ZVABD-NEXT: vmv.s.x v10, zero
+; RV32ZVABD-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; RV32ZVABD-NEXT: vabdu.vv v8, v8, v9
+; RV32ZVABD-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32ZVABD-NEXT: vzext.vf4 v9, v8
+; RV32ZVABD-NEXT: vredsum.vs v8, v9, v10
+; RV32ZVABD-NEXT: vmv.x.s a0, v8
+; RV32ZVABD-NEXT: ret
+;
+; RV64ZVABD-LABEL: sad_4x8_as_i32:
+; RV64ZVABD: # %bb.0: # %entry
+; RV64ZVABD-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; RV64ZVABD-NEXT: vmv.s.x v10, zero
+; RV64ZVABD-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; RV64ZVABD-NEXT: vabdu.vv v8, v8, v9
+; RV64ZVABD-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVABD-NEXT: vzext.vf4 v9, v8
+; RV64ZVABD-NEXT: vredsum.vs v8, v9, v10
+; RV64ZVABD-NEXT: vmv.x.s a0, v8
+; RV64ZVABD-NEXT: andi a0, a0, 1023
+; RV64ZVABD-NEXT: ret
+; ZVABD32-LABEL: sad_4x8_as_i32:
+; ZVABD32: # %bb.0: # %entry
+; ZVABD32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVABD32-NEXT: vmv.s.x v10, zero
+; ZVABD32-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; ZVABD32-NEXT: vabdu.vv v8, v8, v9
+; ZVABD32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVABD32-NEXT: vzext.vf4 v9, v8
+; ZVABD32-NEXT: vredsum.vs v8, v9, v10
+; ZVABD32-NEXT: vmv.x.s a0, v8
+; ZVABD32-NEXT: ret
+; ZVABD64-LABEL: sad_4x8_as_i32:
+; ZVABD64: # %bb.0: # %entry
+; ZVABD64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVABD64-NEXT: vmv.s.x v10, zero
+; ZVABD64-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; ZVABD64-NEXT: vabdu.vv v8, v8, v9
+; ZVABD64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVABD64-NEXT: vzext.vf4 v9, v8
+; ZVABD64-NEXT: vredsum.vs v8, v9, v10
+; ZVABD64-NEXT: vmv.x.s a0, v8
+; ZVABD64-NEXT: andi a0, a0, 1023
+; ZVABD64-NEXT: ret
entry:
%1 = zext <4 x i8> %a to <4 x i32>
%3 = zext <4 x i8> %b to <4 x i32>
@@ -73,29 +126,85 @@ entry:
}
define signext i16 @sad_16x8_as_i16(<16 x i8> %a, <16 x i8> %b) {
-; CHECK-LABEL: sad_16x8_as_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetivli zero, 16, e16, m1, ta, ma
-; CHECK-NEXT: vmv.s.x v10, zero
-; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT: vminu.vv v11, v8, v9
-; CHECK-NEXT: vmaxu.vv v8, v8, v9
-; CHECK-NEXT: vsub.vv v8, v8, v11
-; CHECK-NEXT: vwredsumu.vs v8, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmv.x.s a0, v8
-; CHECK-NEXT: ret
+; RV32-LABEL: sad_16x8_as_i16:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: vsetivli zero, 16, e16, m1, ta, ma
+; RV32-NEXT: vmv.s.x v10, zero
+; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; RV32-NEXT: vminu.vv v11, v8, v9
+; RV32-NEXT: vmaxu.vv v8, v8, v9
+; RV32-NEXT: vsub.vv v8, v8, v11
+; RV32-NEXT: vwredsumu.vs v8, v8, v10
+; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32-NEXT: vmv.x.s a0, v8
+; RV32-NEXT: slli a0, a0, 20
+; RV32-NEXT: srli a0, a0, 20
+; RV32-NEXT: ret
;
-; ZVABD-LABEL: sad_16x8_as_i16:
-; ZVABD: # %bb.0: # %entry
-; ZVABD-NEXT: vsetivli zero, 16, e16, m1, ta, ma
-; ZVABD-NEXT: vmv.s.x v10, zero
-; ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVABD-NEXT: vabdu.vv v8, v8, v9
-; ZVABD-NEXT: vwredsumu.vs v8, v8, v10
-; ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVABD-NEXT: vmv.x.s a0, v8
-; ZVABD-NEXT: ret
+; RV64-LABEL: sad_16x8_as_i16:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetivli zero, 16, e16, m1, ta, ma
+; RV64-NEXT: vmv.s.x v10, zero
+; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; RV64-NEXT: vminu.vv v11, v8, v9
+; RV64-NEXT: vmaxu.vv v8, v8, v9
+; RV64-NEXT: vsub.vv v8, v8, v11
+; RV64-NEXT: vwredsumu.vs v8, v8, v10
+; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64-NEXT: vmv.x.s a0, v8
+; RV64-NEXT: slli a0, a0, 52
+; RV64-NEXT: srli a0, a0, 52
+; RV64-NEXT: ret
+;
+; RV32ZVABD-LABEL: sad_16x8_as_i16:
+; RV32ZVABD: # %bb.0: # %entry
+; RV32ZVABD-NEXT: vsetivli zero, 16, e16, m1, ta, ma
+; RV32ZVABD-NEXT: vmv.s.x v10, zero
+; RV32ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; RV32ZVABD-NEXT: vabdu.vv v8, v8, v9
+; RV32ZVABD-NEXT: vwredsumu.vs v8, v8, v10
+; RV32ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32ZVABD-NEXT: vmv.x.s a0, v8
+; RV32ZVABD-NEXT: slli a0, a0, 20
+; RV32ZVABD-NEXT: srli a0, a0, 20
+; RV32ZVABD-NEXT: ret
+;
+; RV64ZVABD-LABEL: sad_16x8_as_i16:
+; RV64ZVABD: # %bb.0: # %entry
+; RV64ZVABD-NEXT: vsetivli zero, 16, e16, m1, ta, ma
+; RV64ZVABD-NEXT: vmv.s.x v10, zero
+; RV64ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; RV64ZVABD-NEXT: vabdu.vv v8, v8, v9
+; RV64ZVABD-NEXT: vwredsumu.vs v8, v8, v10
+; RV64ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVABD-NEXT: vmv.x.s a0, v8
+; RV64ZVABD-NEXT: slli a0, a0, 52
+; RV64ZVABD-NEXT: srli a0, a0, 52
+; RV64ZVABD-NEXT: ret
+; ZVABD32-LABEL: sad_16x8_as_i16:
+; ZVABD32: # %bb.0: # %entry
+; ZVABD32-NEXT: vsetivli zero, 16, e16, m1, ta, ma
+; ZVABD32-NEXT: vmv.s.x v10, zero
+; ZVABD32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; ZVABD32-NEXT: vabdu.vv v8, v8, v9
+; ZVABD32-NEXT: vwredsumu.vs v8, v8, v10
+; ZVABD32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVABD32-NEXT: vmv.x.s a0, v8
+; ZVABD32-NEXT: slli a0, a0, 20
+; ZVABD32-NEXT: srli a0, a0, 20
+; ZVABD32-NEXT: ret
+; ZVABD64-LABEL: sad_16x8_as_i16:
+; ZVABD64: # %bb.0: # %entry
+; ZVABD64-NEXT: vsetivli zero, 16, e16, m1, ta, ma
+; ZVABD64-NEXT: vmv.s.x v10, zero
+; ZVABD64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; ZVABD64-NEXT: vabdu.vv v8, v8, v9
+; ZVABD64-NEXT: vwredsumu.vs v8, v8, v10
+; ZVABD64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVABD64-NEXT: vmv.x.s a0, v8
+; ZVABD64-NEXT: slli a0, a0, 52
+; ZVABD64-NEXT: srli a0, a0, 52
+; ZVABD64-NEXT: ret
entry:
%1 = zext <16 x i8> %a to <16 x i16>
%3 = zext <16 x i8> %b to <16 x i16>
@@ -106,29 +215,79 @@ entry:
}
define signext i32 @sad_16x8_as_i32(<16 x i8> %a, <16 x i8> %b) {
-; CHECK-LABEL: sad_16x8_as_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT: vminu.vv v10, v8, v9
-; CHECK-NEXT: vmaxu.vv v8, v8, v9
-; CHECK-NEXT: vsub.vv v12, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; CHECK-NEXT: vzext.vf4 v8, v12
-; CHECK-NEXT: vmv.s.x v12, zero
-; CHECK-NEXT: vredsum.vs v8, v8, v12
-; CHECK-NEXT: vmv.x.s a0, v8
-; CHECK-NEXT: ret
+; RV32-LABEL: sad_16x8_as_i32:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; RV32-NEXT: vminu.vv v10, v8, v9
+; RV32-NEXT: vmaxu.vv v8, v8, v9
+; RV32-NEXT: vsub.vv v12, v8, v10
+; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32-NEXT: vzext.vf4 v8, v12
+; RV32-NEXT: vmv.s.x v12, zero
+; RV32-NEXT: vredsum.vs v8, v8, v12
+; RV32-NEXT: vmv.x.s a0, v8
+; RV32-NEXT: ret
;
-; ZVABD-LABEL: sad_16x8_as_i32:
-; ZVABD: # %bb.0: # %entry
-; ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVABD-NEXT: vabdu.vv v12, v8, v9
-; ZVABD-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVABD-NEXT: vzext.vf4 v8, v12
-; ZVABD-NEXT: vmv.s.x v12, zero
-; ZVABD-NEXT: vredsum.vs v8, v8, v12
-; ZVABD-NEXT: vmv.x.s a0, v8
-; ZVABD-NEXT: ret
+; RV64-LABEL: sad_16x8_as_i32:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; RV64-NEXT: vminu.vv v10, v8, v9
+; RV64-NEXT: vmaxu.vv v8, v8, v9
+; RV64-NEXT: vsub.vv v12, v8, v10
+; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64-NEXT: vzext.vf4 v8, v12
+; RV64-NEXT: vmv.s.x v12, zero
+; RV64-NEXT: vredsum.vs v8, v8, v12
+; RV64-NEXT: vmv.x.s a0, v8
+; RV64-NEXT: slli a0, a0, 52
+; RV64-NEXT: srli a0, a0, 52
+; RV64-NEXT: ret
+;
+; RV32ZVABD-LABEL: sad_16x8_as_i32:
+; RV32ZVABD: # %bb.0: # %entry
+; RV32ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; RV32ZVABD-NEXT: vabdu.vv v12, v8, v9
+; RV32ZVABD-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32ZVABD-NEXT: vzext.vf4 v8, v12
+; RV32ZVABD-NEXT: vmv.s.x v12, zero
+; RV32ZVABD-NEXT: vredsum.vs v8, v8, v12
+; RV32ZVABD-NEXT: vmv.x.s a0, v8
+; RV32ZVABD-NEXT: ret
+;
+; RV64ZVABD-LABEL: sad_16x8_as_i32:
+; RV64ZVABD: # %bb.0: # %entry
+; RV64ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; RV64ZVABD-NEXT: vabdu.vv v12, v8, v9
+; RV64ZVABD-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVABD-NEXT: vzext.vf4 v8, v12
+; RV64ZVABD-NEXT: vmv.s.x v12, zero
+; RV64ZVABD-NEXT: vredsum.vs v8, v8, v12
+; RV64ZVABD-NEXT: vmv.x.s a0, v8
+; RV64ZVABD-NEXT: slli a0, a0, 52
+; RV64ZVABD-NEXT: srli a0, a0, 52
+; RV64ZVABD-NEXT: ret
+; ZVABD32-LABEL: sad_16x8_as_i32:
+; ZVABD32: # %bb.0: # %entry
+; ZVABD32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; ZVABD32-NEXT: vabdu.vv v12, v8, v9
+; ZVABD32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVABD32-NEXT: vzext.vf4 v8, v12
+; ZVABD32-NEXT: vmv.s.x v12, zero
+; ZVABD32-NEXT: vredsum.vs v8, v8, v12
+; ZVABD32-NEXT: vmv.x.s a0, v8
+; ZVABD32-NEXT: ret
+; ZVABD64-LABEL: sad_16x8_as_i32:
+; ZVABD64: # %bb.0: # %entry
+; ZVABD64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; ZVABD64-NEXT: vabdu.vv v12, v8, v9
+; ZVABD64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVABD64-NEXT: vzext.vf4 v8, v12
+; ZVABD64-NEXT: vmv.s.x v12, zero
+; ZVABD64-NEXT: vredsum.vs v8, v8, v12
+; ZVABD64-NEXT: vmv.x.s a0, v8
+; ZVABD64-NEXT: slli a0, a0, 52
+; ZVABD64-NEXT: srli a0, a0, 52
+; ZVABD64-NEXT: ret
entry:
%1 = zext <16 x i8> %a to <16 x i32>
%3 = zext <16 x i8> %b to <16 x i32>
@@ -139,79 +298,227 @@ entry:
}
define signext i32 @sad_2block_16xi8_as_i32(ptr %a, ptr %b, i32 signext %stridea, i32 signext %strideb) {
-; CHECK-LABEL: sad_2block_16xi8_as_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT: vle8.v v8, (a0)
-; CHECK-NEXT: vle8.v v9, (a1)
-; CHECK-NEXT: add a0, a0, a2
-; CHECK-NEXT: vle8.v v10, (a0)
-; CHECK-NEXT: add a1, a1, a3
-; CHECK-NEXT: vle8.v v11, (a1)
-; CHECK-NEXT: add a0, a0, a2
-; CHECK-NEXT: vle8.v v12, (a0)
-; CHECK-NEXT: vminu.vv v13, v8, v9
-; CHECK-NEXT: vmaxu.vv v8, v8, v9
-; CHECK-NEXT: add a1, a1, a3
-; CHECK-NEXT: vminu.vv v9, v10, v11
-; CHECK-NEXT: vle8.v v14, (a1)
-; CHECK-NEXT: vmaxu.vv v10, v10, v11
-; CHECK-NEXT: add a0, a0, a2
-; CHECK-NEXT: vsub.vv v8, v8, v13
-; CHECK-NEXT: vle8.v v11, (a0)
-; CHECK-NEXT: vsub.vv v9, v10, v9
-; CHECK-NEXT: add a1, a1, a3
-; CHECK-NEXT: vle8.v v10, (a1)
-; CHECK-NEXT: vminu.vv v13, v12, v14
-; CHECK-NEXT: vmaxu.vv v12, v12, v14
-; CHECK-NEXT: vminu.vv v14, v11, v10
-; CHECK-NEXT: vmaxu.vv v10, v11, v10
-; CHECK-NEXT: vsub.vv v11, v12, v13
-; CHECK-NEXT: vsub.vv v10, v10, v14
-; CHECK-NEXT: vwaddu.vv v12, v9, v8
-; CHECK-NEXT: vwaddu.vv v14, v10, v11
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vwaddu.vv v8, v14, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.s.x v12, zero
-; CHECK-NEXT: vredsum.vs v8, v8, v12
-; CHECK-NEXT: vmv.x.s a0, v8
-; CHECK-NEXT: ret
+; RV32-LABEL: sad_2block_16xi8_as_i32:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; RV32-NEXT: vle8.v v8, (a0)
+; RV32-NEXT: vle8.v v9, (a1)
+; RV32-NEXT: add a0, a0, a2
+; RV32-NEXT: vle8.v v10, (a0)
+; RV32-NEXT: add a1, a1, a3
+; RV32-NEXT: vle8.v v11, (a1)
+; RV32-NEXT: add a0, a0, a2
+; RV32-NEXT: vle8.v v12, (a0)
+; RV32-NEXT: vminu.vv v13, v8, v9
+; RV32-NEXT: vmaxu.vv v8, v8, v9
+; RV32-NEXT: add a1, a1, a3
+; RV32-NEXT: vminu.vv v9, v10, v11
+; RV32-NEXT: vle8.v v14, (a1)
+; RV32-NEXT: vmaxu.vv v10, v10, v11
+; RV32-NEXT: add a0, a0, a2
+; RV32-NEXT: vsub.vv v8, v8, v13
+; RV32-NEXT: vle8.v v11, (a0)
+; RV32-NEXT: vsub.vv v9, v10, v9
+; RV32-NEXT: add a1, a1, a3
+; RV32-NEXT: vle8.v v10, (a1)
+; RV32-NEXT: vminu.vv v13, v12, v14
+; RV32-NEXT: vmaxu.vv v12, v12, v14
+; RV32-NEXT: vminu.vv v14, v11, v10
+; RV32-NEXT: vmaxu.vv v10, v11, v10
+; RV32-NEXT: vsub.vv v11, v12, v13
+; RV32-NEXT: vsub.vv v10, v10, v14
+; RV32-NEXT: vwaddu.vv v12, v9, v8
+; RV32-NEXT: vwaddu.vv v14, v10, v11
+; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32-NEXT: vwaddu.vv v8, v14, v12
+; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32-NEXT: vmv.s.x v12, zero
+; RV32-NEXT: vredsum.vs v8, v8, v12
+; RV32-NEXT: vmv.x.s a0, v8
+; RV32-NEXT: ret
;
-; ZVABD-LABEL: sad_2block_16xi8_as_i32:
-; ZVABD: # %bb.0: # %entry
-; ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVABD-NEXT: vle8.v v8, (a0)
-; ZVABD-NEXT: vle8.v v9, (a1)
-; ZVABD-NEXT: add a0, a0, a2
-; ZVABD-NEXT: add a4, a0, a2
-; ZVABD-NEXT: vabdu.vv v8, v8, v9
-; ZVABD-NEXT: vle8.v v9, (a4)
-; ZVABD-NEXT: add a1, a1, a3
-; ZVABD-NEXT: add a5, a1, a3
-; ZVABD-NEXT: vle8.v v10, (a5)
-; ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVABD-NEXT: vzext.vf2 v12, v8
-; ZVABD-NEXT: vle8.v v8, (a0)
-; ZVABD-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; ZVABD-NEXT: vabdu.vv v9, v9, v10
-; ZVABD-NEXT: vle8.v v10, (a1)
-; ZVABD-NEXT: add a2, a4, a2
-; ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVABD-NEXT: vzext.vf2 v14, v9
-; ZVABD-NEXT: vle8.v v9, (a2)
-; ZVABD-NEXT: add a3, a5, a3
-; ZVABD-NEXT: vle8.v v11, (a3)
-; ZVABD-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; ZVABD-NEXT: vwabdau.vv v12, v8, v10
-; ZVABD-NEXT: vwabdau.vv v14, v9, v11
-; ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVABD-NEXT: vwaddu.vv v8, v14, v12
-; ZVABD-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVABD-NEXT: vmv.s.x v12, zero
-; ZVABD-NEXT: vredsum.vs v8, v8, v12
-; ZVABD-NEXT: vmv.x.s a0, v8
-; ZVABD-NEXT: ret
+; RV64-LABEL: sad_2block_16xi8_as_i32:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; RV64-NEXT: vle8.v v8, (a0)
+; RV64-NEXT: vle8.v v9, (a1)
+; RV64-NEXT: add a0, a0, a2
+; RV64-NEXT: vle8.v v10, (a0)
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vle8.v v11, (a1)
+; RV64-NEXT: add a0, a0, a2
+; RV64-NEXT: vle8.v v12, (a0)
+; RV64-NEXT: vminu.vv v13, v8, v9
+; RV64-NEXT: vmaxu.vv v8, v8, v9
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vminu.vv v9, v10, v11
+; RV64-NEXT: vle8.v v14, (a1)
+; RV64-NEXT: vmaxu.vv v10, v10, v11
+; RV64-NEXT: add a0, a0, a2
+; RV64-NEXT: vsub.vv v8, v8, v13
+; RV64-NEXT: vle8.v v11, (a0)
+; RV64-NEXT: vsub.vv v9, v10, v9
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vle8.v v10, (a1)
+; RV64-NEXT: vminu.vv v13, v12, v14
+; RV64-NEXT: vmaxu.vv v12, v12, v14
+; RV64-NEXT: vminu.vv v14, v11, v10
+; RV64-NEXT: vmaxu.vv v10, v11, v10
+; RV64-NEXT: vsub.vv v11, v12, v13
+; RV64-NEXT: vsub.vv v10, v10, v14
+; RV64-NEXT: vwaddu.vv v12, v9, v8
+; RV64-NEXT: vwaddu.vv v14, v10, v11
+; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64-NEXT: vwaddu.vv v8, v14, v12
+; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64-NEXT: vmv.s.x v12, zero
+; RV64-NEXT: vredsum.vs v8, v8, v12
+; RV64-NEXT: vmv.x.s a0, v8
+; RV64-NEXT: slli a0, a0, 50
+; RV64-NEXT: srli a0, a0, 50
+; RV64-NEXT: ret
+;
+; RV32ZVABD-LABEL: sad_2block_16xi8_as_i32:
+; RV32ZVABD: # %bb.0: # %entry
+; RV32ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; RV32ZVABD-NEXT: vle8.v v8, (a0)
+; RV32ZVABD-NEXT: vle8.v v9, (a1)
+; RV32ZVABD-NEXT: add a0, a0, a2
+; RV32ZVABD-NEXT: add a4, a0, a2
+; RV32ZVABD-NEXT: vabdu.vv v8, v8, v9
+; RV32ZVABD-NEXT: vle8.v v9, (a4)
+; RV32ZVABD-NEXT: add a1, a1, a3
+; RV32ZVABD-NEXT: add a5, a1, a3
+; RV32ZVABD-NEXT: vle8.v v10, (a5)
+; RV32ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32ZVABD-NEXT: vzext.vf2 v12, v8
+; RV32ZVABD-NEXT: vle8.v v8, (a0)
+; RV32ZVABD-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; RV32ZVABD-NEXT: vabdu.vv v9, v9, v10
+; RV32ZVABD-NEXT: vle8.v v10, (a1)
+; RV32ZVABD-NEXT: add a2, a4, a2
+; RV32ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32ZVABD-NEXT: vzext.vf2 v14, v9
+; RV32ZVABD-NEXT: vle8.v v9, (a2)
+; RV32ZVABD-NEXT: add a3, a5, a3
+; RV32ZVABD-NEXT: vle8.v v11, (a3)
+; RV32ZVABD-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; RV32ZVABD-NEXT: vwabdau.vv v12, v8, v10
+; RV32ZVABD-NEXT: vwabdau.vv v14, v9, v11
+; RV32ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32ZVABD-NEXT: vwaddu.vv v8, v14, v12
+; RV32ZVABD-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32ZVABD-NEXT: vmv.s.x v12, zero
+; RV32ZVABD-NEXT: vredsum.vs v8, v8, v12
+; RV32ZVABD-NEXT: vmv.x.s a0, v8
+; RV32ZVABD-NEXT: ret
+;
+; RV64ZVABD-LABEL: sad_2block_16xi8_as_i32:
+; RV64ZVABD: # %bb.0: # %entry
+; RV64ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; RV64ZVABD-NEXT: vle8.v v8, (a0)
+; RV64ZVABD-NEXT: vle8.v v9, (a1)
+; RV64ZVABD-NEXT: add a0, a0, a2
+; RV64ZVABD-NEXT: add a4, a0, a2
+; RV64ZVABD-NEXT: vabdu.vv v8, v8, v9
+; RV64ZVABD-NEXT: vle8.v v9, (a4)
+; RV64ZVABD-NEXT: add a1, a1, a3
+; RV64ZVABD-NEXT: add a5, a1, a3
+; RV64ZVABD-NEXT: vle8.v v10, (a5)
+; RV64ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVABD-NEXT: vzext.vf2 v12, v8
+; RV64ZVABD-NEXT: vle8.v v8, (a0)
+; RV64ZVABD-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; RV64ZVABD-NEXT: vabdu.vv v9, v9, v10
+; RV64ZVABD-NEXT: vle8.v v10, (a1)
+; RV64ZVABD-NEXT: add a2, a4, a2
+; RV64ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVABD-NEXT: vzext.vf2 v14, v9
+; RV64ZVABD-NEXT: vle8.v v9, (a2)
+; RV64ZVABD-NEXT: add a3, a5, a3
+; RV64ZVABD-NEXT: vle8.v v11, (a3)
+; RV64ZVABD-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; RV64ZVABD-NEXT: vwabdau.vv v12, v8, v10
+; RV64ZVABD-NEXT: vwabdau.vv v14, v9, v11
+; RV64ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVABD-NEXT: vwaddu.vv v8, v14, v12
+; RV64ZVABD-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVABD-NEXT: vmv.s.x v12, zero
+; RV64ZVABD-NEXT: vredsum.vs v8, v8, v12
+; RV64ZVABD-NEXT: vmv.x.s a0, v8
+; RV64ZVABD-NEXT: slli a0, a0, 50
+; RV64ZVABD-NEXT: srli a0, a0, 50
+; RV64ZVABD-NEXT: ret
+; ZVABD32-LABEL: sad_2block_16xi8_as_i32:
+; ZVABD32: # %bb.0: # %entry
+; ZVABD32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; ZVABD32-NEXT: vle8.v v8, (a0)
+; ZVABD32-NEXT: vle8.v v9, (a1)
+; ZVABD32-NEXT: add a0, a0, a2
+; ZVABD32-NEXT: add a4, a0, a2
+; ZVABD32-NEXT: vabdu.vv v8, v8, v9
+; ZVABD32-NEXT: vle8.v v9, (a4)
+; ZVABD32-NEXT: add a1, a1, a3
+; ZVABD32-NEXT: add a5, a1, a3
+; ZVABD32-NEXT: vle8.v v10, (a5)
+; ZVABD32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVABD32-NEXT: vzext.vf2 v12, v8
+; ZVABD32-NEXT: vle8.v v8, (a0)
+; ZVABD32-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; ZVABD32-NEXT: vabdu.vv v9, v9, v10
+; ZVABD32-NEXT: vle8.v v10, (a1)
+; ZVABD32-NEXT: add a2, a4, a2
+; ZVABD32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVABD32-NEXT: vzext.vf2 v14, v9
+; ZVABD32-NEXT: vle8.v v9, (a2)
+; ZVABD32-NEXT: add a3, a5, a3
+; ZVABD32-NEXT: vle8.v v11, (a3)
+; ZVABD32-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; ZVABD32-NEXT: vwabdau.vv v12, v8, v10
+; ZVABD32-NEXT: vwabdau.vv v14, v9, v11
+; ZVABD32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVABD32-NEXT: vwaddu.vv v8, v14, v12
+; ZVABD32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVABD32-NEXT: vmv.s.x v12, zero
+; ZVABD32-NEXT: vredsum.vs v8, v8, v12
+; ZVABD32-NEXT: vmv.x.s a0, v8
+; ZVABD32-NEXT: ret
+; ZVABD64-LABEL: sad_2block_16xi8_as_i32:
+; ZVABD64: # %bb.0: # %entry
+; ZVABD64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; ZVABD64-NEXT: vle8.v v8, (a0)
+; ZVABD64-NEXT: vle8.v v9, (a1)
+; ZVABD64-NEXT: add a0, a0, a2
+; ZVABD64-NEXT: add a4, a0, a2
+; ZVABD64-NEXT: vabdu.vv v8, v8, v9
+; ZVABD64-NEXT: vle8.v v9, (a4)
+; ZVABD64-NEXT: add a1, a1, a3
+; ZVABD64-NEXT: add a5, a1, a3
+; ZVABD64-NEXT: vle8.v v10, (a5)
+; ZVABD64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVABD64-NEXT: vzext.vf2 v12, v8
+; ZVABD64-NEXT: vle8.v v8, (a0)
+; ZVABD64-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; ZVABD64-NEXT: vabdu.vv v9, v9, v10
+; ZVABD64-NEXT: vle8.v v10, (a1)
+; ZVABD64-NEXT: add a2, a4, a2
+; ZVABD64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVABD64-NEXT: vzext.vf2 v14, v9
+; ZVABD64-NEXT: vle8.v v9, (a2)
+; ZVABD64-NEXT: add a3, a5, a3
+; ZVABD64-NEXT: vle8.v v11, (a3)
+; ZVABD64-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; ZVABD64-NEXT: vwabdau.vv v12, v8, v10
+; ZVABD64-NEXT: vwabdau.vv v14, v9, v11
+; ZVABD64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVABD64-NEXT: vwaddu.vv v8, v14, v12
+; ZVABD64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVABD64-NEXT: vmv.s.x v12, zero
+; ZVABD64-NEXT: vredsum.vs v8, v8, v12
+; ZVABD64-NEXT: vmv.x.s a0, v8
+; ZVABD64-NEXT: slli a0, a0, 50
+; ZVABD64-NEXT: srli a0, a0, 50
+; ZVABD64-NEXT: ret
entry:
%idx.ext8 = sext i32 %strideb to i64
%idx.ext = sext i32 %stridea to i64
@@ -256,79 +563,227 @@ entry:
}
define signext i32 @sadu_2block_16xi8_as_i32(ptr %a, ptr %b, i32 signext %stridea, i32 signext %strideb) {
-; CHECK-LABEL: sadu_2block_16xi8_as_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT: vle8.v v8, (a0)
-; CHECK-NEXT: vle8.v v9, (a1)
-; CHECK-NEXT: add a0, a0, a2
-; CHECK-NEXT: vle8.v v10, (a0)
-; CHECK-NEXT: add a1, a1, a3
-; CHECK-NEXT: vle8.v v11, (a1)
-; CHECK-NEXT: add a0, a0, a2
-; CHECK-NEXT: vle8.v v12, (a0)
-; CHECK-NEXT: vmin.vv v13, v8, v9
-; CHECK-NEXT: vmax.vv v8, v8, v9
-; CHECK-NEXT: add a1, a1, a3
-; CHECK-NEXT: vmin.vv v9, v10, v11
-; CHECK-NEXT: vle8.v v14, (a1)
-; CHECK-NEXT: vmax.vv v10, v10, v11
-; CHECK-NEXT: add a0, a0, a2
-; CHECK-NEXT: vsub.vv v8, v8, v13
-; CHECK-NEXT: vle8.v v11, (a0)
-; CHECK-NEXT: vsub.vv v9, v10, v9
-; CHECK-NEXT: add a1, a1, a3
-; CHECK-NEXT: vle8.v v10, (a1)
-; CHECK-NEXT: vmin.vv v13, v12, v14
-; CHECK-NEXT: vmax.vv v12, v12, v14
-; CHECK-NEXT: vmin.vv v14, v11, v10
-; CHECK-NEXT: vmax.vv v10, v11, v10
-; CHECK-NEXT: vsub.vv v11, v12, v13
-; CHECK-NEXT: vsub.vv v10, v10, v14
-; CHECK-NEXT: vwaddu.vv v12, v9, v8
-; CHECK-NEXT: vwaddu.vv v14, v10, v11
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vwaddu.vv v8, v14, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.s.x v12, zero
-; CHECK-NEXT: vredsum.vs v8, v8, v12
-; CHECK-NEXT: vmv.x.s a0, v8
-; CHECK-NEXT: ret
+; RV32-LABEL: sadu_2block_16xi8_as_i32:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; RV32-NEXT: vle8.v v8, (a0)
+; RV32-NEXT: vle8.v v9, (a1)
+; RV32-NEXT: add a0, a0, a2
+; RV32-NEXT: vle8.v v10, (a0)
+; RV32-NEXT: add a1, a1, a3
+; RV32-NEXT: vle8.v v11, (a1)
+; RV32-NEXT: add a0, a0, a2
+; RV32-NEXT: vle8.v v12, (a0)
+; RV32-NEXT: vmin.vv v13, v8, v9
+; RV32-NEXT: vmax.vv v8, v8, v9
+; RV32-NEXT: add a1, a1, a3
+; RV32-NEXT: vmin.vv v9, v10, v11
+; RV32-NEXT: vle8.v v14, (a1)
+; RV32-NEXT: vmax.vv v10, v10, v11
+; RV32-NEXT: add a0, a0, a2
+; RV32-NEXT: vsub.vv v8, v8, v13
+; RV32-NEXT: vle8.v v11, (a0)
+; RV32-NEXT: vsub.vv v9, v10, v9
+; RV32-NEXT: add a1, a1, a3
+; RV32-NEXT: vle8.v v10, (a1)
+; RV32-NEXT: vmin.vv v13, v12, v14
+; RV32-NEXT: vmax.vv v12, v12, v14
+; RV32-NEXT: vmin.vv v14, v11, v10
+; RV32-NEXT: vmax.vv v10, v11, v10
+; RV32-NEXT: vsub.vv v11, v12, v13
+; RV32-NEXT: vsub.vv v10, v10, v14
+; RV32-NEXT: vwaddu.vv v12, v9, v8
+; RV32-NEXT: vwaddu.vv v14, v10, v11
+; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32-NEXT: vwaddu.vv v8, v14, v12
+; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32-NEXT: vmv.s.x v12, zero
+; RV32-NEXT: vredsum.vs v8, v8, v12
+; RV32-NEXT: vmv.x.s a0, v8
+; RV32-NEXT: ret
;
-; ZVABD-LABEL: sadu_2block_16xi8_as_i32:
-; ZVABD: # %bb.0: # %entry
-; ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVABD-NEXT: vle8.v v8, (a0)
-; ZVABD-NEXT: vle8.v v9, (a1)
-; ZVABD-NEXT: add a0, a0, a2
-; ZVABD-NEXT: add a4, a0, a2
-; ZVABD-NEXT: vabd.vv v8, v8, v9
-; ZVABD-NEXT: vle8.v v9, (a4)
-; ZVABD-NEXT: add a1, a1, a3
-; ZVABD-NEXT: add a5, a1, a3
-; ZVABD-NEXT: vle8.v v10, (a5)
-; ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVABD-NEXT: vzext.vf2 v12, v8
-; ZVABD-NEXT: vle8.v v8, (a0)
-; ZVABD-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; ZVABD-NEXT: vabd.vv v9, v9, v10
-; ZVABD-NEXT: vle8.v v10, (a1)
-; ZVABD-NEXT: add a2, a4, a2
-; ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVABD-NEXT: vzext.vf2 v14, v9
-; ZVABD-NEXT: vle8.v v9, (a2)
-; ZVABD-NEXT: add a3, a5, a3
-; ZVABD-NEXT: vle8.v v11, (a3)
-; ZVABD-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; ZVABD-NEXT: vwabda.vv v12, v8, v10
-; ZVABD-NEXT: vwabda.vv v14, v9, v11
-; ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVABD-NEXT: vwaddu.vv v8, v14, v12
-; ZVABD-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVABD-NEXT: vmv.s.x v12, zero
-; ZVABD-NEXT: vredsum.vs v8, v8, v12
-; ZVABD-NEXT: vmv.x.s a0, v8
-; ZVABD-NEXT: ret
+; RV64-LABEL: sadu_2block_16xi8_as_i32:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; RV64-NEXT: vle8.v v8, (a0)
+; RV64-NEXT: vle8.v v9, (a1)
+; RV64-NEXT: add a0, a0, a2
+; RV64-NEXT: vle8.v v10, (a0)
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vle8.v v11, (a1)
+; RV64-NEXT: add a0, a0, a2
+; RV64-NEXT: vle8.v v12, (a0)
+; RV64-NEXT: vmin.vv v13, v8, v9
+; RV64-NEXT: vmax.vv v8, v8, v9
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vmin.vv v9, v10, v11
+; RV64-NEXT: vle8.v v14, (a1)
+; RV64-NEXT: vmax.vv v10, v10, v11
+; RV64-NEXT: add a0, a0, a2
+; RV64-NEXT: vsub.vv v8, v8, v13
+; RV64-NEXT: vle8.v v11, (a0)
+; RV64-NEXT: vsub.vv v9, v10, v9
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vle8.v v10, (a1)
+; RV64-NEXT: vmin.vv v13, v12, v14
+; RV64-NEXT: vmax.vv v12, v12, v14
+; RV64-NEXT: vmin.vv v14, v11, v10
+; RV64-NEXT: vmax.vv v10, v11, v10
+; RV64-NEXT: vsub.vv v11, v12, v13
+; RV64-NEXT: vsub.vv v10, v10, v14
+; RV64-NEXT: vwaddu.vv v12, v9, v8
+; RV64-NEXT: vwaddu.vv v14, v10, v11
+; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64-NEXT: vwaddu.vv v8, v14, v12
+; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64-NEXT: vmv.s.x v12, zero
+; RV64-NEXT: vredsum.vs v8, v8, v12
+; RV64-NEXT: vmv.x.s a0, v8
+; RV64-NEXT: slli a0, a0, 50
+; RV64-NEXT: srli a0, a0, 50
+; RV64-NEXT: ret
+;
+; RV32ZVABD-LABEL: sadu_2block_16xi8_as_i32:
+; RV32ZVABD: # %bb.0: # %entry
+; RV32ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; RV32ZVABD-NEXT: vle8.v v8, (a0)
+; RV32ZVABD-NEXT: vle8.v v9, (a1)
+; RV32ZVABD-NEXT: add a0, a0, a2
+; RV32ZVABD-NEXT: add a4, a0, a2
+; RV32ZVABD-NEXT: vabd.vv v8, v8, v9
+; RV32ZVABD-NEXT: vle8.v v9, (a4)
+; RV32ZVABD-NEXT: add a1, a1, a3
+; RV32ZVABD-NEXT: add a5, a1, a3
+; RV32ZVABD-NEXT: vle8.v v10, (a5)
+; RV32ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32ZVABD-NEXT: vzext.vf2 v12, v8
+; RV32ZVABD-NEXT: vle8.v v8, (a0)
+; RV32ZVABD-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; RV32ZVABD-NEXT: vabd.vv v9, v9, v10
+; RV32ZVABD-NEXT: vle8.v v10, (a1)
+; RV32ZVABD-NEXT: add a2, a4, a2
+; RV32ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32ZVABD-NEXT: vzext.vf2 v14, v9
+; RV32ZVABD-NEXT: vle8.v v9, (a2)
+; RV32ZVABD-NEXT: add a3, a5, a3
+; RV32ZVABD-NEXT: vle8.v v11, (a3)
+; RV32ZVABD-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; RV32ZVABD-NEXT: vwabda.vv v12, v8, v10
+; RV32ZVABD-NEXT: vwabda.vv v14, v9, v11
+; RV32ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32ZVABD-NEXT: vwaddu.vv v8, v14, v12
+; RV32ZVABD-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32ZVABD-NEXT: vmv.s.x v12, zero
+; RV32ZVABD-NEXT: vredsum.vs v8, v8, v12
+; RV32ZVABD-NEXT: vmv.x.s a0, v8
+; RV32ZVABD-NEXT: ret
+;
+; RV64ZVABD-LABEL: sadu_2block_16xi8_as_i32:
+; RV64ZVABD: # %bb.0: # %entry
+; RV64ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; RV64ZVABD-NEXT: vle8.v v8, (a0)
+; RV64ZVABD-NEXT: vle8.v v9, (a1)
+; RV64ZVABD-NEXT: add a0, a0, a2
+; RV64ZVABD-NEXT: add a4, a0, a2
+; RV64ZVABD-NEXT: vabd.vv v8, v8, v9
+; RV64ZVABD-NEXT: vle8.v v9, (a4)
+; RV64ZVABD-NEXT: add a1, a1, a3
+; RV64ZVABD-NEXT: add a5, a1, a3
+; RV64ZVABD-NEXT: vle8.v v10, (a5)
+; RV64ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVABD-NEXT: vzext.vf2 v12, v8
+; RV64ZVABD-NEXT: vle8.v v8, (a0)
+; RV64ZVABD-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; RV64ZVABD-NEXT: vabd.vv v9, v9, v10
+; RV64ZVABD-NEXT: vle8.v v10, (a1)
+; RV64ZVABD-NEXT: add a2, a4, a2
+; RV64ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVABD-NEXT: vzext.vf2 v14, v9
+; RV64ZVABD-NEXT: vle8.v v9, (a2)
+; RV64ZVABD-NEXT: add a3, a5, a3
+; RV64ZVABD-NEXT: vle8.v v11, (a3)
+; RV64ZVABD-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; RV64ZVABD-NEXT: vwabda.vv v12, v8, v10
+; RV64ZVABD-NEXT: vwabda.vv v14, v9, v11
+; RV64ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVABD-NEXT: vwaddu.vv v8, v14, v12
+; RV64ZVABD-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVABD-NEXT: vmv.s.x v12, zero
+; RV64ZVABD-NEXT: vredsum.vs v8, v8, v12
+; RV64ZVABD-NEXT: vmv.x.s a0, v8
+; RV64ZVABD-NEXT: slli a0, a0, 50
+; RV64ZVABD-NEXT: srli a0, a0, 50
+; RV64ZVABD-NEXT: ret
+; ZVABD32-LABEL: sadu_2block_16xi8_as_i32:
+; ZVABD32: # %bb.0: # %entry
+; ZVABD32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; ZVABD32-NEXT: vle8.v v8, (a0)
+; ZVABD32-NEXT: vle8.v v9, (a1)
+; ZVABD32-NEXT: add a0, a0, a2
+; ZVABD32-NEXT: add a4, a0, a2
+; ZVABD32-NEXT: vabd.vv v8, v8, v9
+; ZVABD32-NEXT: vle8.v v9, (a4)
+; ZVABD32-NEXT: add a1, a1, a3
+; ZVABD32-NEXT: add a5, a1, a3
+; ZVABD32-NEXT: vle8.v v10, (a5)
+; ZVABD32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVABD32-NEXT: vzext.vf2 v12, v8
+; ZVABD32-NEXT: vle8.v v8, (a0)
+; ZVABD32-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; ZVABD32-NEXT: vabd.vv v9, v9, v10
+; ZVABD32-NEXT: vle8.v v10, (a1)
+; ZVABD32-NEXT: add a2, a4, a2
+; ZVABD32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVABD32-NEXT: vzext.vf2 v14, v9
+; ZVABD32-NEXT: vle8.v v9, (a2)
+; ZVABD32-NEXT: add a3, a5, a3
+; ZVABD32-NEXT: vle8.v v11, (a3)
+; ZVABD32-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; ZVABD32-NEXT: vwabda.vv v12, v8, v10
+; ZVABD32-NEXT: vwabda.vv v14, v9, v11
+; ZVABD32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVABD32-NEXT: vwaddu.vv v8, v14, v12
+; ZVABD32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVABD32-NEXT: vmv.s.x v12, zero
+; ZVABD32-NEXT: vredsum.vs v8, v8, v12
+; ZVABD32-NEXT: vmv.x.s a0, v8
+; ZVABD32-NEXT: ret
+; ZVABD64-LABEL: sadu_2block_16xi8_as_i32:
+; ZVABD64: # %bb.0: # %entry
+; ZVABD64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; ZVABD64-NEXT: vle8.v v8, (a0)
+; ZVABD64-NEXT: vle8.v v9, (a1)
+; ZVABD64-NEXT: add a0, a0, a2
+; ZVABD64-NEXT: add a4, a0, a2
+; ZVABD64-NEXT: vabd.vv v8, v8, v9
+; ZVABD64-NEXT: vle8.v v9, (a4)
+; ZVABD64-NEXT: add a1, a1, a3
+; ZVABD64-NEXT: add a5, a1, a3
+; ZVABD64-NEXT: vle8.v v10, (a5)
+; ZVABD64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVABD64-NEXT: vzext.vf2 v12, v8
+; ZVABD64-NEXT: vle8.v v8, (a0)
+; ZVABD64-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; ZVABD64-NEXT: vabd.vv v9, v9, v10
+; ZVABD64-NEXT: vle8.v v10, (a1)
+; ZVABD64-NEXT: add a2, a4, a2
+; ZVABD64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVABD64-NEXT: vzext.vf2 v14, v9
+; ZVABD64-NEXT: vle8.v v9, (a2)
+; ZVABD64-NEXT: add a3, a5, a3
+; ZVABD64-NEXT: vle8.v v11, (a3)
+; ZVABD64-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; ZVABD64-NEXT: vwabda.vv v12, v8, v10
+; ZVABD64-NEXT: vwabda.vv v14, v9, v11
+; ZVABD64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVABD64-NEXT: vwaddu.vv v8, v14, v12
+; ZVABD64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVABD64-NEXT: vmv.s.x v12, zero
+; ZVABD64-NEXT: vredsum.vs v8, v8, v12
+; ZVABD64-NEXT: vmv.x.s a0, v8
+; ZVABD64-NEXT: slli a0, a0, 50
+; ZVABD64-NEXT: srli a0, a0, 50
+; ZVABD64-NEXT: ret
entry:
%idx.ext8 = sext i32 %strideb to i64
%idx.ext = sext i32 %stridea to i64
diff --git a/llvm/test/CodeGen/X86/vector-compress.ll b/llvm/test/CodeGen/X86/vector-compress.ll
index a0548ce8abdc3..619db0096adbc 100644
--- a/llvm/test/CodeGen/X86/vector-compress.ll
+++ b/llvm/test/CodeGen/X86/vector-compress.ll
@@ -1566,7 +1566,6 @@ define <32 x i8> @test_compress_v32i8(<32 x i8> %vec, <32 x i1> %mask, <32 x i8>
; AVX512F-NEXT: vpextrd $1, %xmm3, %eax
; AVX512F-NEXT: vmovd %xmm3, %ecx
; AVX512F-NEXT: addl %eax, %ecx
-; AVX512F-NEXT: andl $31, %ecx
; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX512F-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; AVX512F-NEXT: vpcompressd %zmm0, %zmm0 {%k1} {z}
@@ -2437,7 +2436,6 @@ define <64 x i8> @test_compress_v64i8(<64 x i8> %vec, <64 x i1> %mask, <64 x i8>
; AVX512F-NEXT: vpextrd $1, %xmm3, %eax
; AVX512F-NEXT: vmovd %xmm3, %ecx
; AVX512F-NEXT: addl %eax, %ecx
-; AVX512F-NEXT: andl $31, %ecx
; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm3
; AVX512F-NEXT: vpmovzxbd {{.*#+}} zmm3 = xmm3[0],zero,zero,zero,xmm3[1],zero,zero,zero,xmm3[2],zero,zero,zero,xmm3[3],zero,zero,zero,xmm3[4],zero,zero,zero,xmm3[5],zero,zero,zero,xmm3[6],zero,zero,zero,xmm3[7],zero,zero,zero,xmm3[8],zero,zero,zero,xmm3[9],zero,zero,zero,xmm3[10],zero,zero,zero,xmm3[11],zero,zero,zero,xmm3[12],zero,zero,zero,xmm3[13],zero,zero,zero,xmm3[14],zero,zero,zero,xmm3[15],zero,zero,zero
; AVX512F-NEXT: vpcompressd %zmm3, %zmm3 {%k2} {z}
@@ -2457,7 +2455,6 @@ define <64 x i8> @test_compress_v64i8(<64 x i8> %vec, <64 x i1> %mask, <64 x i8>
; AVX512F-NEXT: vpextrd $1, %xmm4, %eax
; AVX512F-NEXT: vmovd %xmm4, %ecx
; AVX512F-NEXT: addl %eax, %ecx
-; AVX512F-NEXT: andl $31, %ecx
; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX512F-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; AVX512F-NEXT: vpcompressd %zmm0, %zmm0 {%k1} {z}
@@ -2761,35 +2758,34 @@ define <32 x i16> @test_compress_v32i16(<32 x i16> %vec, <32 x i1> %mask, <32 x
; AVX512F-NEXT: andq $-64, %rsp
; AVX512F-NEXT: subq $128, %rsp
; AVX512F-NEXT: vpmovzxbw {{.*#+}} ymm3 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
-; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm5
-; AVX512F-NEXT: vpmovzxbw {{.*#+}} ymm4 = xmm5[0],zero,xmm5[1],zero,xmm5[2],zero,xmm5[3],zero,xmm5[4],zero,xmm5[5],zero,xmm5[6],zero,xmm5[7],zero,xmm5[8],zero,xmm5[9],zero,xmm5[10],zero,xmm5[11],zero,xmm5[12],zero,xmm5[13],zero,xmm5[14],zero,xmm5[15],zero
-; AVX512F-NEXT: vpmovsxbd %xmm5, %zmm5
-; AVX512F-NEXT: vpslld $31, %zmm5, %zmm5
-; AVX512F-NEXT: vptestmd %zmm5, %zmm5, %k1
-; AVX512F-NEXT: vpmovsxbd %xmm1, %zmm5
-; AVX512F-NEXT: vpslld $31, %zmm5, %zmm5
-; AVX512F-NEXT: vptestmd %zmm5, %zmm5, %k2
-; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm5 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
-; AVX512F-NEXT: vpcompressd %zmm5, %zmm5 {%k2} {z}
-; AVX512F-NEXT: vpmovdw %zmm5, (%rsp)
+; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm4
+; AVX512F-NEXT: vpmovzxbw {{.*#+}} ymm5 = xmm4[0],zero,xmm4[1],zero,xmm4[2],zero,xmm4[3],zero,xmm4[4],zero,xmm4[5],zero,xmm4[6],zero,xmm4[7],zero,xmm4[8],zero,xmm4[9],zero,xmm4[10],zero,xmm4[11],zero,xmm4[12],zero,xmm4[13],zero,xmm4[14],zero,xmm4[15],zero
+; AVX512F-NEXT: vpmovsxbd %xmm4, %zmm4
+; AVX512F-NEXT: vpslld $31, %zmm4, %zmm4
+; AVX512F-NEXT: vptestmd %zmm4, %zmm4, %k1
+; AVX512F-NEXT: vpmovsxbd %xmm1, %zmm4
+; AVX512F-NEXT: vpslld $31, %zmm4, %zmm4
+; AVX512F-NEXT: vptestmd %zmm4, %zmm4, %k2
+; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm4 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
+; AVX512F-NEXT: vpcompressd %zmm4, %zmm4 {%k2} {z}
+; AVX512F-NEXT: vpmovdw %zmm4, (%rsp)
; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512F-NEXT: vpmovzxbd {{.*#+}} zmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero,xmm1[8],zero,zero,zero,xmm1[9],zero,zero,zero,xmm1[10],zero,zero,zero,xmm1[11],zero,zero,zero,xmm1[12],zero,zero,zero,xmm1[13],zero,zero,zero,xmm1[14],zero,zero,zero,xmm1[15],zero,zero,zero
-; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm5
-; AVX512F-NEXT: vpaddd %ymm5, %ymm1, %ymm1
-; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm5
-; AVX512F-NEXT: vpaddd %xmm5, %xmm1, %xmm1
-; AVX512F-NEXT: vpshufd {{.*#+}} xmm5 = xmm1[2,3,2,3]
-; AVX512F-NEXT: vpaddd %xmm5, %xmm1, %xmm1
+; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm4
+; AVX512F-NEXT: vpaddd %ymm4, %ymm1, %ymm1
+; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm4
+; AVX512F-NEXT: vpaddd %xmm4, %xmm1, %xmm1
+; AVX512F-NEXT: vpshufd {{.*#+}} xmm4 = xmm1[2,3,2,3]
+; AVX512F-NEXT: vpaddd %xmm4, %xmm1, %xmm1
; AVX512F-NEXT: vpextrd $1, %xmm1, %eax
; AVX512F-NEXT: vmovd %xmm1, %ecx
; AVX512F-NEXT: addl %eax, %ecx
-; AVX512F-NEXT: andl $31, %ecx
; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm0
; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512F-NEXT: vpcompressd %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: vpmovdw %zmm0, (%rsp,%rcx,2)
; AVX512F-NEXT: vextracti64x4 $1, %zmm2, %ymm0
-; AVX512F-NEXT: vpsllw $15, %ymm4, %ymm1
+; AVX512F-NEXT: vpsllw $15, %ymm5, %ymm1
; AVX512F-NEXT: vpsraw $15, %ymm1, %ymm1
; AVX512F-NEXT: vpblendvb %ymm1, {{[0-9]+}}(%rsp), %ymm0, %ymm0
; AVX512F-NEXT: vpsllw $15, %ymm3, %ymm1
@@ -3363,7 +3359,6 @@ define <64 x i32> @test_compress_large(<64 x i1> %mask, <64 x i32> %vec, <64 x i
; AVX512F-NEXT: vpextrd $1, %xmm4, %eax
; AVX512F-NEXT: vmovd %xmm4, %ecx
; AVX512F-NEXT: addl %eax, %ecx
-; AVX512F-NEXT: andl $31, %ecx
; AVX512F-NEXT: vpcompressd %zmm1, %zmm1 {%k2} {z}
; AVX512F-NEXT: vmovdqa64 %zmm1, (%rsp,%rcx,4)
; AVX512F-NEXT: vpcompressd %zmm2, %zmm1 {%k3} {z}
@@ -3379,7 +3374,6 @@ define <64 x i32> @test_compress_large(<64 x i1> %mask, <64 x i32> %vec, <64 x i
; AVX512F-NEXT: vpextrd $1, %xmm1, %eax
; AVX512F-NEXT: vmovd %xmm1, %ecx
; AVX512F-NEXT: addl %eax, %ecx
-; AVX512F-NEXT: andl $31, %ecx
; AVX512F-NEXT: vpcompressd %zmm3, %zmm1 {%k1} {z}
; AVX512F-NEXT: vmovdqa64 %zmm1, 128(%rsp,%rcx,4)
; AVX512F-NEXT: vmovdqa64 (%rsp), %zmm1
@@ -3434,7 +3428,6 @@ define <64 x i32> @test_compress_large(<64 x i1> %mask, <64 x i32> %vec, <64 x i
; AVX512VL-NEXT: vpextrd $1, %xmm1, %eax
; AVX512VL-NEXT: vmovd %xmm1, %ecx
; AVX512VL-NEXT: addl %eax, %ecx
-; AVX512VL-NEXT: andl $31, %ecx
; AVX512VL-NEXT: kshiftrq $16, %k2, %k2
; AVX512VL-NEXT: vpcompressd %zmm2, %zmm1 {%k2} {z}
; AVX512VL-NEXT: vmovdqa64 %zmm1, (%rsp,%rcx,4)
@@ -3451,7 +3444,6 @@ define <64 x i32> @test_compress_large(<64 x i1> %mask, <64 x i32> %vec, <64 x i
; AVX512VL-NEXT: vpextrd $1, %xmm1, %eax
; AVX512VL-NEXT: vmovd %xmm1, %ecx
; AVX512VL-NEXT: addl %eax, %ecx
-; AVX512VL-NEXT: andl $31, %ecx
; AVX512VL-NEXT: vpcompressd %zmm4, %zmm1 {%k1} {z}
; AVX512VL-NEXT: vmovdqa64 %zmm1, 128(%rsp,%rcx,4)
; AVX512VL-NEXT: vmovdqa64 (%rsp), %zmm1
>From 0263f86641941c925a607cdbce64e97f127d8b68 Mon Sep 17 00:00:00 2001
From: sabonaoabdi <sabonaoabdi at gmail.com>
Date: Thu, 9 Jul 2026 20:48:09 -0500
Subject: [PATCH 3/4] [SelectionDAG] Remove dead check prefixes in
fixed-vectors-sad.ll
---
.../CodeGen/RISCV/rvv/fixed-vectors-sad.ll | 209 ------------------
1 file changed, 209 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
index cd9d4efe3c09f..aebf6819dc9d0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
@@ -93,29 +93,6 @@ define signext i32 @sad_4x8_as_i32(<4 x i8> %a, <4 x i8> %b) {
; RV64ZVABD-NEXT: vmv.x.s a0, v8
; RV64ZVABD-NEXT: andi a0, a0, 1023
; RV64ZVABD-NEXT: ret
-; ZVABD32-LABEL: sad_4x8_as_i32:
-; ZVABD32: # %bb.0: # %entry
-; ZVABD32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVABD32-NEXT: vmv.s.x v10, zero
-; ZVABD32-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; ZVABD32-NEXT: vabdu.vv v8, v8, v9
-; ZVABD32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVABD32-NEXT: vzext.vf4 v9, v8
-; ZVABD32-NEXT: vredsum.vs v8, v9, v10
-; ZVABD32-NEXT: vmv.x.s a0, v8
-; ZVABD32-NEXT: ret
-; ZVABD64-LABEL: sad_4x8_as_i32:
-; ZVABD64: # %bb.0: # %entry
-; ZVABD64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVABD64-NEXT: vmv.s.x v10, zero
-; ZVABD64-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; ZVABD64-NEXT: vabdu.vv v8, v8, v9
-; ZVABD64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVABD64-NEXT: vzext.vf4 v9, v8
-; ZVABD64-NEXT: vredsum.vs v8, v9, v10
-; ZVABD64-NEXT: vmv.x.s a0, v8
-; ZVABD64-NEXT: andi a0, a0, 1023
-; ZVABD64-NEXT: ret
entry:
%1 = zext <4 x i8> %a to <4 x i32>
%3 = zext <4 x i8> %b to <4 x i32>
@@ -181,30 +158,6 @@ define signext i16 @sad_16x8_as_i16(<16 x i8> %a, <16 x i8> %b) {
; RV64ZVABD-NEXT: slli a0, a0, 52
; RV64ZVABD-NEXT: srli a0, a0, 52
; RV64ZVABD-NEXT: ret
-; ZVABD32-LABEL: sad_16x8_as_i16:
-; ZVABD32: # %bb.0: # %entry
-; ZVABD32-NEXT: vsetivli zero, 16, e16, m1, ta, ma
-; ZVABD32-NEXT: vmv.s.x v10, zero
-; ZVABD32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVABD32-NEXT: vabdu.vv v8, v8, v9
-; ZVABD32-NEXT: vwredsumu.vs v8, v8, v10
-; ZVABD32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVABD32-NEXT: vmv.x.s a0, v8
-; ZVABD32-NEXT: slli a0, a0, 20
-; ZVABD32-NEXT: srli a0, a0, 20
-; ZVABD32-NEXT: ret
-; ZVABD64-LABEL: sad_16x8_as_i16:
-; ZVABD64: # %bb.0: # %entry
-; ZVABD64-NEXT: vsetivli zero, 16, e16, m1, ta, ma
-; ZVABD64-NEXT: vmv.s.x v10, zero
-; ZVABD64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVABD64-NEXT: vabdu.vv v8, v8, v9
-; ZVABD64-NEXT: vwredsumu.vs v8, v8, v10
-; ZVABD64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVABD64-NEXT: vmv.x.s a0, v8
-; ZVABD64-NEXT: slli a0, a0, 52
-; ZVABD64-NEXT: srli a0, a0, 52
-; ZVABD64-NEXT: ret
entry:
%1 = zext <16 x i8> %a to <16 x i16>
%3 = zext <16 x i8> %b to <16 x i16>
@@ -266,28 +219,6 @@ define signext i32 @sad_16x8_as_i32(<16 x i8> %a, <16 x i8> %b) {
; RV64ZVABD-NEXT: slli a0, a0, 52
; RV64ZVABD-NEXT: srli a0, a0, 52
; RV64ZVABD-NEXT: ret
-; ZVABD32-LABEL: sad_16x8_as_i32:
-; ZVABD32: # %bb.0: # %entry
-; ZVABD32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVABD32-NEXT: vabdu.vv v12, v8, v9
-; ZVABD32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVABD32-NEXT: vzext.vf4 v8, v12
-; ZVABD32-NEXT: vmv.s.x v12, zero
-; ZVABD32-NEXT: vredsum.vs v8, v8, v12
-; ZVABD32-NEXT: vmv.x.s a0, v8
-; ZVABD32-NEXT: ret
-; ZVABD64-LABEL: sad_16x8_as_i32:
-; ZVABD64: # %bb.0: # %entry
-; ZVABD64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVABD64-NEXT: vabdu.vv v12, v8, v9
-; ZVABD64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVABD64-NEXT: vzext.vf4 v8, v12
-; ZVABD64-NEXT: vmv.s.x v12, zero
-; ZVABD64-NEXT: vredsum.vs v8, v8, v12
-; ZVABD64-NEXT: vmv.x.s a0, v8
-; ZVABD64-NEXT: slli a0, a0, 52
-; ZVABD64-NEXT: srli a0, a0, 52
-; ZVABD64-NEXT: ret
entry:
%1 = zext <16 x i8> %a to <16 x i32>
%3 = zext <16 x i8> %b to <16 x i32>
@@ -449,76 +380,6 @@ define signext i32 @sad_2block_16xi8_as_i32(ptr %a, ptr %b, i32 signext %stridea
; RV64ZVABD-NEXT: slli a0, a0, 50
; RV64ZVABD-NEXT: srli a0, a0, 50
; RV64ZVABD-NEXT: ret
-; ZVABD32-LABEL: sad_2block_16xi8_as_i32:
-; ZVABD32: # %bb.0: # %entry
-; ZVABD32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVABD32-NEXT: vle8.v v8, (a0)
-; ZVABD32-NEXT: vle8.v v9, (a1)
-; ZVABD32-NEXT: add a0, a0, a2
-; ZVABD32-NEXT: add a4, a0, a2
-; ZVABD32-NEXT: vabdu.vv v8, v8, v9
-; ZVABD32-NEXT: vle8.v v9, (a4)
-; ZVABD32-NEXT: add a1, a1, a3
-; ZVABD32-NEXT: add a5, a1, a3
-; ZVABD32-NEXT: vle8.v v10, (a5)
-; ZVABD32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVABD32-NEXT: vzext.vf2 v12, v8
-; ZVABD32-NEXT: vle8.v v8, (a0)
-; ZVABD32-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; ZVABD32-NEXT: vabdu.vv v9, v9, v10
-; ZVABD32-NEXT: vle8.v v10, (a1)
-; ZVABD32-NEXT: add a2, a4, a2
-; ZVABD32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVABD32-NEXT: vzext.vf2 v14, v9
-; ZVABD32-NEXT: vle8.v v9, (a2)
-; ZVABD32-NEXT: add a3, a5, a3
-; ZVABD32-NEXT: vle8.v v11, (a3)
-; ZVABD32-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; ZVABD32-NEXT: vwabdau.vv v12, v8, v10
-; ZVABD32-NEXT: vwabdau.vv v14, v9, v11
-; ZVABD32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVABD32-NEXT: vwaddu.vv v8, v14, v12
-; ZVABD32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVABD32-NEXT: vmv.s.x v12, zero
-; ZVABD32-NEXT: vredsum.vs v8, v8, v12
-; ZVABD32-NEXT: vmv.x.s a0, v8
-; ZVABD32-NEXT: ret
-; ZVABD64-LABEL: sad_2block_16xi8_as_i32:
-; ZVABD64: # %bb.0: # %entry
-; ZVABD64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVABD64-NEXT: vle8.v v8, (a0)
-; ZVABD64-NEXT: vle8.v v9, (a1)
-; ZVABD64-NEXT: add a0, a0, a2
-; ZVABD64-NEXT: add a4, a0, a2
-; ZVABD64-NEXT: vabdu.vv v8, v8, v9
-; ZVABD64-NEXT: vle8.v v9, (a4)
-; ZVABD64-NEXT: add a1, a1, a3
-; ZVABD64-NEXT: add a5, a1, a3
-; ZVABD64-NEXT: vle8.v v10, (a5)
-; ZVABD64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVABD64-NEXT: vzext.vf2 v12, v8
-; ZVABD64-NEXT: vle8.v v8, (a0)
-; ZVABD64-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; ZVABD64-NEXT: vabdu.vv v9, v9, v10
-; ZVABD64-NEXT: vle8.v v10, (a1)
-; ZVABD64-NEXT: add a2, a4, a2
-; ZVABD64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVABD64-NEXT: vzext.vf2 v14, v9
-; ZVABD64-NEXT: vle8.v v9, (a2)
-; ZVABD64-NEXT: add a3, a5, a3
-; ZVABD64-NEXT: vle8.v v11, (a3)
-; ZVABD64-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; ZVABD64-NEXT: vwabdau.vv v12, v8, v10
-; ZVABD64-NEXT: vwabdau.vv v14, v9, v11
-; ZVABD64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVABD64-NEXT: vwaddu.vv v8, v14, v12
-; ZVABD64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVABD64-NEXT: vmv.s.x v12, zero
-; ZVABD64-NEXT: vredsum.vs v8, v8, v12
-; ZVABD64-NEXT: vmv.x.s a0, v8
-; ZVABD64-NEXT: slli a0, a0, 50
-; ZVABD64-NEXT: srli a0, a0, 50
-; ZVABD64-NEXT: ret
entry:
%idx.ext8 = sext i32 %strideb to i64
%idx.ext = sext i32 %stridea to i64
@@ -714,76 +575,6 @@ define signext i32 @sadu_2block_16xi8_as_i32(ptr %a, ptr %b, i32 signext %stride
; RV64ZVABD-NEXT: slli a0, a0, 50
; RV64ZVABD-NEXT: srli a0, a0, 50
; RV64ZVABD-NEXT: ret
-; ZVABD32-LABEL: sadu_2block_16xi8_as_i32:
-; ZVABD32: # %bb.0: # %entry
-; ZVABD32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVABD32-NEXT: vle8.v v8, (a0)
-; ZVABD32-NEXT: vle8.v v9, (a1)
-; ZVABD32-NEXT: add a0, a0, a2
-; ZVABD32-NEXT: add a4, a0, a2
-; ZVABD32-NEXT: vabd.vv v8, v8, v9
-; ZVABD32-NEXT: vle8.v v9, (a4)
-; ZVABD32-NEXT: add a1, a1, a3
-; ZVABD32-NEXT: add a5, a1, a3
-; ZVABD32-NEXT: vle8.v v10, (a5)
-; ZVABD32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVABD32-NEXT: vzext.vf2 v12, v8
-; ZVABD32-NEXT: vle8.v v8, (a0)
-; ZVABD32-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; ZVABD32-NEXT: vabd.vv v9, v9, v10
-; ZVABD32-NEXT: vle8.v v10, (a1)
-; ZVABD32-NEXT: add a2, a4, a2
-; ZVABD32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVABD32-NEXT: vzext.vf2 v14, v9
-; ZVABD32-NEXT: vle8.v v9, (a2)
-; ZVABD32-NEXT: add a3, a5, a3
-; ZVABD32-NEXT: vle8.v v11, (a3)
-; ZVABD32-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; ZVABD32-NEXT: vwabda.vv v12, v8, v10
-; ZVABD32-NEXT: vwabda.vv v14, v9, v11
-; ZVABD32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVABD32-NEXT: vwaddu.vv v8, v14, v12
-; ZVABD32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVABD32-NEXT: vmv.s.x v12, zero
-; ZVABD32-NEXT: vredsum.vs v8, v8, v12
-; ZVABD32-NEXT: vmv.x.s a0, v8
-; ZVABD32-NEXT: ret
-; ZVABD64-LABEL: sadu_2block_16xi8_as_i32:
-; ZVABD64: # %bb.0: # %entry
-; ZVABD64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVABD64-NEXT: vle8.v v8, (a0)
-; ZVABD64-NEXT: vle8.v v9, (a1)
-; ZVABD64-NEXT: add a0, a0, a2
-; ZVABD64-NEXT: add a4, a0, a2
-; ZVABD64-NEXT: vabd.vv v8, v8, v9
-; ZVABD64-NEXT: vle8.v v9, (a4)
-; ZVABD64-NEXT: add a1, a1, a3
-; ZVABD64-NEXT: add a5, a1, a3
-; ZVABD64-NEXT: vle8.v v10, (a5)
-; ZVABD64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVABD64-NEXT: vzext.vf2 v12, v8
-; ZVABD64-NEXT: vle8.v v8, (a0)
-; ZVABD64-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; ZVABD64-NEXT: vabd.vv v9, v9, v10
-; ZVABD64-NEXT: vle8.v v10, (a1)
-; ZVABD64-NEXT: add a2, a4, a2
-; ZVABD64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVABD64-NEXT: vzext.vf2 v14, v9
-; ZVABD64-NEXT: vle8.v v9, (a2)
-; ZVABD64-NEXT: add a3, a5, a3
-; ZVABD64-NEXT: vle8.v v11, (a3)
-; ZVABD64-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; ZVABD64-NEXT: vwabda.vv v12, v8, v10
-; ZVABD64-NEXT: vwabda.vv v14, v9, v11
-; ZVABD64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVABD64-NEXT: vwaddu.vv v8, v14, v12
-; ZVABD64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVABD64-NEXT: vmv.s.x v12, zero
-; ZVABD64-NEXT: vredsum.vs v8, v8, v12
-; ZVABD64-NEXT: vmv.x.s a0, v8
-; ZVABD64-NEXT: slli a0, a0, 50
-; ZVABD64-NEXT: srli a0, a0, 50
-; ZVABD64-NEXT: ret
entry:
%idx.ext8 = sext i32 %strideb to i64
%idx.ext = sext i32 %stridea to i64
>From 3ffb6b429a8940906cc62e2c19f9911b30bf8b78 Mon Sep 17 00:00:00 2001
From: sabonaoabdi <sabonaoabdi at gmail.com>
Date: Sat, 18 Jul 2026 01:45:43 -0500
Subject: [PATCH 4/4] [RISCV] Add computeKnownBits support for
RISCVISD::VECREDUCE_ADD_VL
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 22 +++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 2c8f05d2d298a..b015ee4980a8b 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -23817,6 +23817,28 @@ void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
Known.Zero.setBitsFrom(Known2.countMaxActiveBits());
break;
}
+ case RISCVISD::VECREDUCE_ADD_VL: {
+ SDValue Src = Op.getOperand(1);
+ SDValue InitVal = Op.getOperand(2);
+ SDValue VL = Op.getOperand(4);
+ unsigned NumElts;
+
+ if (isa<ConstantSDNode>(VL)) {
+ NumElts = VL->getAsZExtVal();
+ } else {
+ const RISCVSubtarget &SubTarget = DAG.getSubtarget<RISCVSubtarget>();
+ auto [Min, Max] = computeVLMAXBounds(Src.getSimpleValueType(), SubTarget);
+ NumElts = Max;
+ }
+
+ KnownBits KnownAcrossElts =
+ DAG.computeKnownBits(Src, APInt::getAllOnes(1), Depth + 1);
+ KnownBits VecSum = KnownAcrossElts.reduceAdd(NumElts);
+ KnownBits Start = DAG.computeKnownBits(InitVal, Depth + 1);
+
+ Known = KnownBits::add(Start, VecSum);
+ break;
+ }
case RISCVISD::CZERO_EQZ:
case RISCVISD::CZERO_NEZ:
Known = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);
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