[llvm] [SPARC] Emit a TRUNCATE when combining truncating BSWAP-STOREs (PR #210483)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 17 21:49:44 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-sparc
Author: Koakuma (koachan)
<details>
<summary>Changes</summary>
Failure to cause this will result in narrower STORE_BIG/LITTLE being fed with a wider operand, causing instruction selection to fail.
Also, for completeness, add variants of extending/truncating ops for LOAD-BSWAP pairs too.
---
Full diff: https://github.com/llvm/llvm-project/pull/210483.diff
2 Files Affected:
- (modified) llvm/lib/Target/Sparc/SparcISelLowering.cpp (+3)
- (modified) llvm/test/CodeGen/SPARC/bswap.ll (+279)
``````````diff
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index c45babaec5dc2..96a7ae75bd541 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -3333,6 +3333,9 @@ SDValue SparcTargetLowering::PerformSTORECombine(SDNode *N,
unsigned Shift = VT.getSizeInBits() - MemVT.getSizeInBits();
BSwapOp = DAG.getNode(ISD::SRL, DL, VT, BSwapOp,
DAG.getShiftAmountConstant(Shift, VT, DL));
+ // Need to truncate if this is a bswap of i64 stored as i32/i16.
+ if (VT == MVT::i64)
+ BSwapOp = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BSwapOp);
}
SDValue Ops[] = {N->getOperand(0), BSwapOp, N->getOperand(2),
diff --git a/llvm/test/CodeGen/SPARC/bswap.ll b/llvm/test/CodeGen/SPARC/bswap.ll
index e63efcec77101..ea82e6df8831f 100644
--- a/llvm/test/CodeGen/SPARC/bswap.ll
+++ b/llvm/test/CodeGen/SPARC/bswap.ll
@@ -403,6 +403,140 @@ define i64 @u64_bswapload_misaligned(ptr %0) #0 {
ret i64 %3
}
+define i16 @u16_bswapload_truncated(ptr %0) #0 {
+; SPARC32-LABEL: u16_bswapload_truncated:
+; SPARC32: ! %bb.0:
+; SPARC32-NEXT: add %o0, 2, %o0
+; SPARC32-NEXT: retl
+; SPARC32-NEXT: lduha [%o0] #ASI_P_L, %o0
+;
+; SPARCEL-LABEL: u16_bswapload_truncated:
+; SPARCEL: ! %bb.0:
+; SPARCEL-NEXT: retl
+; SPARCEL-NEXT: lduha [%o0] #ASI_P, %o0
+;
+; SPARC64-LABEL: u16_bswapload_truncated:
+; SPARC64: ! %bb.0:
+; SPARC64-NEXT: add %o0, 2, %o0
+; SPARC64-NEXT: retl
+; SPARC64-NEXT: lduha [%o0] #ASI_P_L, %o0
+ %2 = load i32, ptr %0, align 4
+ %3 = trunc i32 %2 to i16
+ %4 = tail call i16 @llvm.bswap.i16(i16 %3)
+ ret i16 %4
+}
+
+define i32 @u32_bswapload_truncated(ptr %0) #0 {
+; SPARC32-LABEL: u32_bswapload_truncated:
+; SPARC32: ! %bb.0:
+; SPARC32-NEXT: add %o0, 4, %o0
+; SPARC32-NEXT: retl
+; SPARC32-NEXT: lda [%o0] #ASI_P_L, %o0
+;
+; SPARCEL-LABEL: u32_bswapload_truncated:
+; SPARCEL: ! %bb.0:
+; SPARCEL-NEXT: retl
+; SPARCEL-NEXT: lda [%o0] #ASI_P, %o0
+;
+; SPARC64-LABEL: u32_bswapload_truncated:
+; SPARC64: ! %bb.0:
+; SPARC64-NEXT: add %o0, 4, %o0
+; SPARC64-NEXT: retl
+; SPARC64-NEXT: lda [%o0] #ASI_P_L, %o0
+ %2 = load i64, ptr %0, align 8
+ %3 = trunc i64 %2 to i32
+ %4 = tail call i32 @llvm.bswap.i32(i32 %3)
+ ret i32 %4
+}
+
+define i16 @u16_bswapload_extended(ptr %0) #0 {
+; SPARC32-LABEL: u16_bswapload_extended:
+; SPARC32: ! %bb.0:
+; SPARC32-NEXT: ldub [%o0], %o0
+; SPARC32-NEXT: retl
+; SPARC32-NEXT: sll %o0, 8, %o0
+;
+; SPARCEL-LABEL: u16_bswapload_extended:
+; SPARCEL: ! %bb.0:
+; SPARCEL-NEXT: ldub [%o0], %o0
+; SPARCEL-NEXT: retl
+; SPARCEL-NEXT: sll %o0, 8, %o0
+;
+; SPARC64-LABEL: u16_bswapload_extended:
+; SPARC64: ! %bb.0:
+; SPARC64-NEXT: ldub [%o0], %o0
+; SPARC64-NEXT: retl
+; SPARC64-NEXT: sll %o0, 8, %o0
+ %2 = load i8, ptr %0, align 1
+ %3 = zext i8 %2 to i16
+ %4 = tail call i16 @llvm.bswap.i16(i16 %3)
+ ret i16 %4
+}
+
+define i32 @u32_bswapload_extended(ptr %0) #0 {
+; SPARC32-LABEL: u32_bswapload_extended:
+; SPARC32: ! %bb.0:
+; SPARC32-NEXT: add %sp, -96, %sp
+; SPARC32-NEXT: lduh [%o0], %o0
+; SPARC32-NEXT: add %sp, 92, %o1
+; SPARC32-NEXT: sta %o0, [%o1] #ASI_P_L
+; SPARC32-NEXT: ld [%sp+92], %o0
+; SPARC32-NEXT: retl
+; SPARC32-NEXT: add %sp, 96, %sp
+;
+; SPARCEL-LABEL: u32_bswapload_extended:
+; SPARCEL: ! %bb.0:
+; SPARCEL-NEXT: add %sp, -96, %sp
+; SPARCEL-NEXT: lduh [%o0], %o0
+; SPARCEL-NEXT: add %sp, 92, %o1
+; SPARCEL-NEXT: sta %o0, [%o1] #ASI_P
+; SPARCEL-NEXT: ld [%sp+92], %o0
+; SPARCEL-NEXT: retl
+; SPARCEL-NEXT: add %sp, 96, %sp
+;
+; SPARC64-LABEL: u32_bswapload_extended:
+; SPARC64: ! %bb.0:
+; SPARC64-NEXT: add %sp, -144, %sp
+; SPARC64-NEXT: lduh [%o0], %o0
+; SPARC64-NEXT: add %sp, 2187, %o1
+; SPARC64-NEXT: sta %o0, [%o1] #ASI_P_L
+; SPARC64-NEXT: ld [%sp+2187], %o0
+; SPARC64-NEXT: retl
+; SPARC64-NEXT: add %sp, 144, %sp
+ %2 = load i16, ptr %0, align 2
+ %3 = zext i16 %2 to i32
+ %4 = tail call i32 @llvm.bswap.i32(i32 %3)
+ ret i32 %4
+}
+
+define i64 @u64_bswapload_extended(ptr %0) #0 {
+; SPARC32-LABEL: u64_bswapload_extended:
+; SPARC32: ! %bb.0:
+; SPARC32-NEXT: lda [%o0] #ASI_P_L, %o0
+; SPARC32-NEXT: retl
+; SPARC32-NEXT: mov %g0, %o1
+;
+; SPARCEL-LABEL: u64_bswapload_extended:
+; SPARCEL: ! %bb.0:
+; SPARCEL-NEXT: lda [%o0] #ASI_P, %o1
+; SPARCEL-NEXT: retl
+; SPARCEL-NEXT: mov %g0, %o0
+;
+; SPARC64-LABEL: u64_bswapload_extended:
+; SPARC64: ! %bb.0:
+; SPARC64-NEXT: add %sp, -144, %sp
+; SPARC64-NEXT: ld [%o0], %o0
+; SPARC64-NEXT: add %sp, 2183, %o1
+; SPARC64-NEXT: stxa %o0, [%o1] #ASI_P_L
+; SPARC64-NEXT: ldx [%sp+2183], %o0
+; SPARC64-NEXT: retl
+; SPARC64-NEXT: add %sp, 144, %sp
+ %2 = load i32, ptr %0, align 4
+ %3 = zext i32 %2 to i64
+ %4 = tail call i64 @llvm.bswap.i64(i64 %3)
+ ret i64 %4
+}
+
define void @u16_bswapstore(ptr %0, i16 %1) #0 {
; SPARC32-LABEL: u16_bswapstore:
; SPARC32: ! %bb.0:
@@ -667,4 +801,149 @@ define void @u64_bswapstore_misaligned(ptr %0, i64 %1) #0 {
ret void
}
+define void @u16_bswapstore_extended(ptr %0, i16 %1) #0 {
+; SPARC32-LABEL: u16_bswapstore_extended:
+; SPARC32: ! %bb.0:
+; SPARC32-NEXT: add %sp, -96, %sp
+; SPARC32-NEXT: add %sp, 92, %o2
+; SPARC32-NEXT: sta %o1, [%o2] #ASI_P_L
+; SPARC32-NEXT: lduh [%sp+92], %o1
+; SPARC32-NEXT: st %o1, [%o0]
+; SPARC32-NEXT: retl
+; SPARC32-NEXT: add %sp, 96, %sp
+;
+; SPARCEL-LABEL: u16_bswapstore_extended:
+; SPARCEL: ! %bb.0:
+; SPARCEL-NEXT: add %sp, -96, %sp
+; SPARCEL-NEXT: add %sp, 92, %o2
+; SPARCEL-NEXT: sta %o1, [%o2] #ASI_P
+; SPARCEL-NEXT: or %o2, 2, %o1
+; SPARCEL-NEXT: lduh [%o1], %o1
+; SPARCEL-NEXT: st %o1, [%o0]
+; SPARCEL-NEXT: retl
+; SPARCEL-NEXT: add %sp, 96, %sp
+;
+; SPARC64-LABEL: u16_bswapstore_extended:
+; SPARC64: ! %bb.0:
+; SPARC64-NEXT: add %sp, -144, %sp
+; SPARC64-NEXT: add %sp, 2187, %o2
+; SPARC64-NEXT: sta %o1, [%o2] #ASI_P_L
+; SPARC64-NEXT: lduh [%sp+2187], %o1
+; SPARC64-NEXT: st %o1, [%o0]
+; SPARC64-NEXT: retl
+; SPARC64-NEXT: add %sp, 144, %sp
+ %3 = tail call i16 @llvm.bswap.i16(i16 %1)
+ %4 = zext i16 %3 to i32
+ store i32 %4, ptr %0, align 4
+ ret void
+}
+
+define void @u32_bswapstore_extended(ptr %0, i32 %1) #0 {
+; SPARC32-LABEL: u32_bswapstore_extended:
+; SPARC32: ! %bb.0:
+; SPARC32-NEXT: add %sp, -96, %sp
+; SPARC32-NEXT: add %sp, 92, %o2
+; SPARC32-NEXT: sta %o1, [%o2] #ASI_P_L
+; SPARC32-NEXT: ld [%sp+92], %o3
+; SPARC32-NEXT: mov %g0, %o2
+; SPARC32-NEXT: std %o2, [%o0]
+; SPARC32-NEXT: retl
+; SPARC32-NEXT: add %sp, 96, %sp
+;
+; SPARCEL-LABEL: u32_bswapstore_extended:
+; SPARCEL: ! %bb.0:
+; SPARCEL-NEXT: add %sp, -96, %sp
+; SPARCEL-NEXT: add %sp, 92, %o2
+; SPARCEL-NEXT: sta %o1, [%o2] #ASI_P
+; SPARCEL-NEXT: ld [%sp+92], %o2
+; SPARCEL-NEXT: mov %g0, %o3
+; SPARCEL-NEXT: std %o2, [%o0]
+; SPARCEL-NEXT: retl
+; SPARCEL-NEXT: add %sp, 96, %sp
+;
+; SPARC64-LABEL: u32_bswapstore_extended:
+; SPARC64: ! %bb.0:
+; SPARC64-NEXT: add %sp, -144, %sp
+; SPARC64-NEXT: add %sp, 2187, %o2
+; SPARC64-NEXT: sta %o1, [%o2] #ASI_P_L
+; SPARC64-NEXT: ld [%sp+2187], %o1
+; SPARC64-NEXT: stx %o1, [%o0]
+; SPARC64-NEXT: retl
+; SPARC64-NEXT: add %sp, 144, %sp
+ %3 = tail call i32 @llvm.bswap.i32(i32 %1)
+ %4 = zext i32 %3 to i64
+ store i64 %4, ptr %0, align 8
+ ret void
+}
+
+define void @u16_bswapstore_truncated(ptr %0, i16 %1) #0 {
+; SPARC32-LABEL: u16_bswapstore_truncated:
+; SPARC32: ! %bb.0:
+; SPARC32-NEXT: srl %o1, 8, %o1
+; SPARC32-NEXT: retl
+; SPARC32-NEXT: stb %o1, [%o0]
+;
+; SPARCEL-LABEL: u16_bswapstore_truncated:
+; SPARCEL: ! %bb.0:
+; SPARCEL-NEXT: srl %o1, 8, %o1
+; SPARCEL-NEXT: retl
+; SPARCEL-NEXT: stb %o1, [%o0]
+;
+; SPARC64-LABEL: u16_bswapstore_truncated:
+; SPARC64: ! %bb.0:
+; SPARC64-NEXT: srl %o1, 8, %o1
+; SPARC64-NEXT: retl
+; SPARC64-NEXT: stb %o1, [%o0]
+ %3 = tail call i16 @llvm.bswap.i16(i16 %1)
+ %4 = trunc i16 %3 to i8
+ store i8 %4, ptr %0, align 1
+ ret void
+}
+
+define void @u32_bswapstore_truncated(ptr %0, i32 %1) #0 {
+; SPARC32-LABEL: u32_bswapstore_truncated:
+; SPARC32: ! %bb.0:
+; SPARC32-NEXT: srl %o1, 16, %o1
+; SPARC32-NEXT: retl
+; SPARC32-NEXT: stha %o1, [%o0] #ASI_P_L
+;
+; SPARCEL-LABEL: u32_bswapstore_truncated:
+; SPARCEL: ! %bb.0:
+; SPARCEL-NEXT: srl %o1, 16, %o1
+; SPARCEL-NEXT: retl
+; SPARCEL-NEXT: stha %o1, [%o0] #ASI_P
+;
+; SPARC64-LABEL: u32_bswapstore_truncated:
+; SPARC64: ! %bb.0:
+; SPARC64-NEXT: srl %o1, 16, %o1
+; SPARC64-NEXT: retl
+; SPARC64-NEXT: stha %o1, [%o0] #ASI_P_L
+ %3 = tail call i32 @llvm.bswap.i32(i32 %1)
+ %4 = trunc i32 %3 to i16
+ store i16 %4, ptr %0, align 2
+ ret void
+}
+
+define void @u64_bswapstore_truncated(ptr %0, i64 %1) #0 {
+; SPARC32-LABEL: u64_bswapstore_truncated:
+; SPARC32: ! %bb.0:
+; SPARC32-NEXT: retl
+; SPARC32-NEXT: sta %o1, [%o0] #ASI_P_L
+;
+; SPARCEL-LABEL: u64_bswapstore_truncated:
+; SPARCEL: ! %bb.0:
+; SPARCEL-NEXT: retl
+; SPARCEL-NEXT: sta %o2, [%o0] #ASI_P
+;
+; SPARC64-LABEL: u64_bswapstore_truncated:
+; SPARC64: ! %bb.0:
+; SPARC64-NEXT: srlx %o1, 32, %o1
+; SPARC64-NEXT: retl
+; SPARC64-NEXT: sta %o1, [%o0] #ASI_P_L
+ %3 = tail call i64 @llvm.bswap.i64(i64 %1)
+ %4 = trunc i64 %3 to i32
+ store i32 %4, ptr %0, align 4
+ ret void
+}
+
attributes #0 = { nounwind }
``````````
</details>
https://github.com/llvm/llvm-project/pull/210483
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