[llvm] [AMDGPU][TTI] Refine gfx9 packed FP32 SLP costs for pair formation and shuffles (PR #208572)

[Akash Dutta via llvm-commits]

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@@ -1042,6 +1042,17 @@ InstructionCost GCNTTIImpl::getVectorInstrCost(
                                        VIC);
     }
 
+    // Gfx9 packed <2 x f32> pair formation for v_pk_*_f32: lanes must occupy an
+    // aligned VGPR pair. A load-fed insert can be allocated into its slot for
+    // free; a compute-fed insert typically needs an alignment move, so charge 1.
+    // f32-only on gfx9 targets with packed FP32 ops.
+    if (Opcode == Instruction::InsertElement && EltSize == 32 &&
+        ST->hasPackedFP32Ops() && ST->getGeneration() == AMDGPUSubtarget::GFX9)
+      if (auto *VecTy = dyn_cast<FixedVectorType>(ValTy))
+        if (VecTy->getNumElements() == 2 &&
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akadutta wrote:

Updated the patch to use legalization cost. Is this what you were suggesting? 

Please note that in _notriviallyvectorizableintrinsicoperands.ll_ and _combine-scalar-selects.ll_, this change makes wide-vector formation more expensive in the cost model, so SLP no longer vectorizes the 4-scalar-load reduction on gfx1250 (keeps scalar loads + fadds) and prefers a single <8 x float> load with shuffles over two <4 x float> loads for the WMMA. VectorCombine likewise stops merging eight scalar i16 selects into one <4 x float> vector select on gfx942, leaving the scalar path in place. The <2 x f32> SLP pair path is unchanged; these are only wider-vector changes. 

https://github.com/llvm/llvm-project/pull/208572