[llvm] [CodeGen] Fix stale LiveIntervals regmask tables after MachineBasicBl… (PR #209610)
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Fri Jul 17 10:25:08 PDT 2026
https://github.com/dlei6g updated https://github.com/llvm/llvm-project/pull/209610
>From 7452374a5854d0e36308048b579185f4b6e47b1a Mon Sep 17 00:00:00 2001
From: David Lei <dalei at nvidia.com>
Date: Tue, 7 Jul 2026 21:19:12 +0000
Subject: [PATCH] [CodeGen] Fix stale LiveIntervals regmask tables after
MachineBasicBlock::splitAt
MachineBasicBlock::splitAt() moves the tail of a block -- including any call
instructions carrying register-mask operands -- into a newly created block.
When LiveIntervals is attached it calls LIS->insertMBBInMaps() for the new
block, which records the block with zero regmask slots. That is only correct
for a fresh, empty block: because the tail (and its regmasks) was *moved* out
of the original block, the per-block RegMaskBlocks index for both the original
and the split block is left stale.
checkRegMaskInterference() consults RegMaskBlocks to find the regmask slots
that apply to a live range. With the stale index a value that is live across a
moved call regmask is no longer seen to interfere with the call clobber, so the
register allocator can assign it to a clobbered physical register, which then
trips the machine verifier (-verify-machineinstrs).
Add LiveIntervals::reassignRegMaskSlots(Orig, SplitBB), which re-slices the
moved regmask slots out of the original block's RegMaskBlocks entry into the
split block's entry (RegMaskSlots is sorted, so the slots that moved are those
at/after the split block's start index), and call it from splitAt() right after
insertMBBInMaps().
Adds a LiveIntervals unit test (SplitAtMovesRegMaskInterference) that splits a
block so a value becomes block-local yet still crosses a call regmask, and
checks that checkRegMaskInterference() still reports the clobber.
---
llvm/include/llvm/CodeGen/LiveIntervals.h | 14 ++++++++++
llvm/lib/CodeGen/LiveIntervals.cpp | 21 +++++++++++++++
llvm/lib/CodeGen/MachineBasicBlock.cpp | 7 ++++-
llvm/unittests/MI/LiveIntervalTest.cpp | 33 +++++++++++++++++++++++
4 files changed, 74 insertions(+), 1 deletion(-)
diff --git a/llvm/include/llvm/CodeGen/LiveIntervals.h b/llvm/include/llvm/CodeGen/LiveIntervals.h
index 99a0122265d3b..fcb465c49e922 100644
--- a/llvm/include/llvm/CodeGen/LiveIntervals.h
+++ b/llvm/include/llvm/CodeGen/LiveIntervals.h
@@ -281,6 +281,12 @@ class LiveIntervals {
return Indexes->getMBBFromIndex(index);
}
+ // NOTE: records the new block with zero regmask slots ({end, 0}), which is
+ // only correct for a fresh, empty block. If you pre-populate \p MBB by
+ // *moving* regmask-bearing instructions (e.g. CALLs) into it -- as
+ // MachineBasicBlock::splitAt does -- the per-block RegMaskBlocks slices for
+ // the source and new block are left stale (the allocator can then miss call
+ // interference); call reassignRegMaskSlots() afterward to fix them up.
void insertMBBInMaps(MachineBasicBlock *MBB) {
Indexes->insertMBBInMaps(MBB);
assert(unsigned(MBB->getNumber()) == RegMaskBlocks.size() &&
@@ -396,6 +402,14 @@ class LiveIntervals {
return getRegMaskBits().slice(P.first, P.second);
}
+ /// Move the per-block regmask table (RegMaskBlocks) entries for the
+ /// instructions splitAt() moved from \p Orig into the new block \p SplitBB.
+ /// insertMBBInMaps() records SplitBB as having no regmasks, so without this
+ /// checkRegMaskInterference can miss call clobbers for ranges local to
+ /// either block.
+ void reassignRegMaskSlots(MachineBasicBlock &Orig,
+ MachineBasicBlock &SplitBB);
+
/// Test if \p LI is live across any register mask instructions, and
/// compute a bit mask of physical registers that are not clobbered by any
/// of them.
diff --git a/llvm/lib/CodeGen/LiveIntervals.cpp b/llvm/lib/CodeGen/LiveIntervals.cpp
index 3da53566ae0c2..a213692535886 100644
--- a/llvm/lib/CodeGen/LiveIntervals.cpp
+++ b/llvm/lib/CodeGen/LiveIntervals.cpp
@@ -294,6 +294,27 @@ void LiveIntervals::computeRegMasks() {
}
}
+void LiveIntervals::reassignRegMaskSlots(MachineBasicBlock &Orig,
+ MachineBasicBlock &SplitBB) {
+ assert(&Orig != &SplitBB && "expected distinct blocks");
+ std::pair<unsigned, unsigned> &OrigRMB = RegMaskBlocks[Orig.getNumber()];
+ std::pair<unsigned, unsigned> &SplitRMB = RegMaskBlocks[SplitBB.getNumber()];
+
+ // splitAt moved the tail of Orig into SplitBB. RegMaskSlots is sorted, so the
+ // slots now belonging to SplitBB are those in Orig's slice at/after SplitBB's
+ // start index.
+ ArrayRef<SlotIndex> OrigSlots =
+ getRegMaskSlots().slice(OrigRMB.first, OrigRMB.second);
+ unsigned KeptCount = llvm::lower_bound(OrigSlots, getMBBStartIdx(&SplitBB)) -
+ OrigSlots.begin();
+ if (KeptCount == OrigRMB.second)
+ return; // No regmask slots moved into SplitBB.
+
+ SplitRMB.first = OrigRMB.first + KeptCount;
+ SplitRMB.second = OrigRMB.second - KeptCount;
+ OrigRMB.second = KeptCount;
+}
+
//===----------------------------------------------------------------------===//
// Register Unit Liveness
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
index 2870bf404644c..5d2726260c9ac 100644
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -1087,8 +1087,13 @@ MachineBasicBlock *MachineBasicBlock::splitAt(MachineInstr &MI,
if (UpdateLiveIns)
addLiveIns(*SplitBB, LiveRegs);
- if (LIS)
+ if (LIS) {
LIS->insertMBBInMaps(SplitBB);
+ // splitAt() may have moved regmask-bearing instructions into SplitBB;
+ // insertMBBInMaps() recorded it with none. Fix up the per-block regmask
+ // table so the allocator still sees call clobbers across the split.
+ LIS->reassignRegMaskSlots(*this, *SplitBB);
+ }
return SplitBB;
}
diff --git a/llvm/unittests/MI/LiveIntervalTest.cpp b/llvm/unittests/MI/LiveIntervalTest.cpp
index 45b8aeb72b598..4f4e99a1ea882 100644
--- a/llvm/unittests/MI/LiveIntervalTest.cpp
+++ b/llvm/unittests/MI/LiveIntervalTest.cpp
@@ -790,6 +790,39 @@ TEST(LiveIntervalTest, SplitAtMultiInstruction) {
});
}
+TEST(LiveIntervalTest, SplitAtMovesRegMaskInterference) {
+ // %0 is defined before and used after a call-clobber regmask, then split
+ // (with the regmask) into a new block, so %0 becomes block-local and still
+ // crosses the regmask. checkRegMaskInterference takes the single-MBB fast
+ // path over the per-block regmask slice, so a stale slice after splitAt
+ // makes it miss the clobber.
+ liveIntervalTest(
+ R"MIR(
+ successors: %bb.1
+ S_NOP 0
+ %0 = IMPLICIT_DEF
+ S_NOP 0, csr_amdgpu
+ S_NOP 0, implicit %0
+ S_BRANCH %bb.1
+ bb.1:
+ S_NOP 0
+)MIR",
+ [](MachineFunction &MF, LiveIntervalsWrapperPass &LISWrapper) {
+ LiveIntervals &LIS = LISWrapper.getLIS();
+ // Split before the def, moving the def, regmask, and use into a new
+ // block; %0 is then block-local and still crosses the regmask.
+ testSplitAt(MF, LIS, 0, 0);
+ LiveInterval &LI = LIS.getInterval(Register::index2VirtReg(0));
+ MachineBasicBlock *MBB = LIS.intervalIsInOneMBB(LI);
+ ASSERT_TRUE(MBB);
+ // The block %0 now lives in must own the moved regmask slot...
+ EXPECT_FALSE(LIS.getRegMaskSlotsInBlock(MBB->getNumber()).empty());
+ // ...so the allocator still sees the call-clobber interference.
+ BitVector UsableRegs(MF.getSubtarget().getRegisterInfo()->getNumRegs());
+ EXPECT_TRUE(LIS.checkRegMaskInterference(LI, UsableRegs));
+ });
+}
+
TEST(LiveIntervalTest, RepairIntervals) {
liveIntervalTest(
R"MIR(
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