[llvm] [NFC] Cleanup in SOPInstructions.td (PR #210367)

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<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-amdgpu

Author: Anshil Gandhi (gandhi56)

<details>
<summary>Changes</summary>

- Eliminate code which was accidentally merged during a merge-conflict
(https://github.com/llvm/llvm-project/pull/203155/changes#r3560059941)
- Remove comments as they are specific to usubsat.


---
Full diff: https://github.com/llvm/llvm-project/pull/210367.diff


1 Files Affected:

- (modified) llvm/lib/Target/AMDGPU/SOPInstructions.td (-9) 


``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index 97d50d6142d35..8fa54de570e67 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -2073,8 +2073,6 @@ let AddedComplexity = 20 in {
   >;
 }
 
-// Uniform saturating unsigned subtraction: usubsat(a, b) = max(a, b) - b
-// If a >= b, result is a - b; otherwise max(a, b) = b, so b - b = 0.
 // Higher complexity to prefer scalar over VALU patterns for uniform values.
 let AddedComplexity = 20 in {
   def : GCNPat<
@@ -2087,13 +2085,6 @@ let AddedComplexity = 20 in {
   >;
 } // End AddedComplexity = 20
 
-// V_ADD_I32_e32/S_ADD_U32 produces carry in VCC/SCC. For the vector
-// case, the sgpr-copies pass will fix this to use the vector version.
-def : GCNPat <
-  (i32 (addc i32:$src0, i32:$src1)),
-  (S_ADD_U32 $src0, $src1)
->;
-
 // FIXME: We need to use COPY_TO_REGCLASS to work-around the fact that
 // REG_SEQUENCE patterns don't support instructions with multiple
 // outputs.

``````````

</details>


https://github.com/llvm/llvm-project/pull/210367