[llvm] 709b7d1 - [X86] Pull out isFoldableAsShuffle lamdba as helper function. NFC. (#210354)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 17 08:43:45 PDT 2026
Author: Simon Pilgrim
Date: 2026-07-17T15:43:40Z
New Revision: 709b7d1bd4a71e484702d610f81b5cf84303386f
URL: https://github.com/llvm/llvm-project/commit/709b7d1bd4a71e484702d610f81b5cf84303386f
DIFF: https://github.com/llvm/llvm-project/commit/709b7d1bd4a71e484702d610f81b5cf84303386f.diff
LOG: [X86] Pull out isFoldableAsShuffle lamdba as helper function. NFC. (#210354)
For future reuse.
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 97e783c09f0f2..f9ec233bd4431 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -8184,6 +8184,13 @@ static bool isFoldableUseOfShuffle(SDNode *N) {
return false;
}
+static bool isFoldableAsShuffle(SDValue V) {
+ while (V.getOpcode() == ISD::BITCAST ||
+ V.getOpcode() == ISD::EXTRACT_SUBVECTOR)
+ V = V.getOperand(0);
+ return isTargetShuffle(V.getOpcode());
+}
+
// If the node has a single use by a VSELECT then AVX512 targets may be able to
// fold as a predicated instruction.
static bool isMaskableNode(SDValue V, const X86Subtarget &Subtarget) {
@@ -61511,13 +61518,6 @@ static SDValue combineINSERT_SUBVECTOR(SDNode *N, SelectionDAG &DAG,
}
}
- auto isFoldableAsShuffle = [](SDValue V) {
- while (V.getOpcode() == ISD::BITCAST ||
- V.getOpcode() == ISD::EXTRACT_SUBVECTOR)
- V = V.getOperand(0);
- return isTargetShuffle(V.getOpcode());
- };
-
// Match concat_vector style patterns.
SmallVector<SDValue, 2> SubVectorOps;
if (collectConcatOps(N, SubVectorOps, DAG)) {
More information about the llvm-commits
mailing list