[llvm] [SelectionDAG] Fold VECREDUCE_MUL of a constant BUILD_VECTOR (PR #210126)

[Ankit Kumar Tiwari via llvm-commits]

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ankit-cybertron wrote:

Sorry for the confusion here. I added the RISC-V test same way as VECREDUCE_MUL. Will remove it and keep only AArch64. Is that what you are asking?

https://github.com/llvm/llvm-project/pull/210126