[llvm] [AMDGPU] Fix computeKnownBitsForTargetNode for AMDGPUISD::LDS (PR #210350)
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 17 07:49:35 PDT 2026
https://github.com/jayfoad created https://github.com/llvm/llvm-project/pull/210350
This was assuming a maximum LDS size of 64 KiB which is not true on all
targets.
>From 5306766a45cacc5cc5e872dbf34d0bcbe50298fe Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Fri, 17 Jul 2026 15:44:04 +0100
Subject: [PATCH 1/2] Precommit GFX950 testing
---
....amdgcn.struct.buffer.load.format.v3f16.ll | 27 +++++++++++++++++++
...gcn.struct.ptr.buffer.load.format.v3f16.ll | 27 +++++++++++++++++++
2 files changed, 54 insertions(+)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
index 6cdee67f6382c..73691eb8382b8 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgpu10.10-- < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -mtriple=amdgpu9.50-- < %s | FileCheck -check-prefix=GFX950 %s
; RUN: llc -mtriple=amdgpu9.00-- < %s | FileCheck -check-prefix=GFX9 %s
; RUN: llc -mtriple=amdgpu8.10-- < %s | FileCheck -check-prefix=GFX8 %s
; RUN: llc -mattr=+real-true16 -mtriple=amdgpu11.00-- < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
@@ -37,6 +38,32 @@ define amdgpu_gs void @main(<4 x i32> %arg, i32 %arg1) {
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ds_write2_b32 v2, v0, v1 offset0:7 offset1:8
;
+; GFX950-LABEL: main:
+; GFX950: ; %bb.0: ; %bb
+; GFX950-NEXT: s_mov_b64 s[2:3], exec
+; GFX950-NEXT: .LBB0_1: ; =>This Inner Loop Header: Depth=1
+; GFX950-NEXT: v_readfirstlane_b32 s4, v0
+; GFX950-NEXT: v_readfirstlane_b32 s5, v1
+; GFX950-NEXT: v_readfirstlane_b32 s6, v2
+; GFX950-NEXT: v_readfirstlane_b32 s7, v3
+; GFX950-NEXT: v_cmp_eq_u64_e32 vcc, s[4:5], v[0:1]
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], v[2:3]
+; GFX950-NEXT: s_and_b64 s[0:1], vcc, s[0:1]
+; GFX950-NEXT: s_and_saveexec_b64 s[0:1], s[0:1]
+; GFX950-NEXT: buffer_load_format_d16_xyz v[6:7], v4, s[4:7], 0 idxen
+; GFX950-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX950-NEXT: ; implicit-def: $vgpr4
+; GFX950-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX950-NEXT: s_cbranch_execnz .LBB0_1
+; GFX950-NEXT: ; %bb.2:
+; GFX950-NEXT: s_mov_b64 exec, s[2:3]
+; GFX950-NEXT: s_waitcnt vmcnt(0)
+; GFX950-NEXT: v_lshrrev_b32_e32 v0, 16, v6
+; GFX950-NEXT: v_and_b32_e32 v1, 0xffff, v7
+; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: ds_write2_b32 v2, v0, v1 offset0:7 offset1:8
+;
; GFX9-LABEL: main:
; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_mov_b64 s[2:3], exec
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
index 7e6ba8bde9fed..130273e822b07 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgpu10.10-- < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -mtriple=amdgpu9.50-- < %s | FileCheck -check-prefix=GFX950 %s
; RUN: llc -mtriple=amdgpu9.00-- < %s | FileCheck -check-prefix=GFX9 %s
; RUN: llc -mtriple=amdgpu8.10-- < %s | FileCheck -check-prefix=GFX8 %s
; RUN: llc -mattr=+real-true16 -mtriple=amdgpu11.00-- < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
@@ -34,6 +35,32 @@ define amdgpu_gs void @main(ptr addrspace(8) %arg, i32 %arg1) {
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ds_write2_b32 v2, v0, v1 offset0:7 offset1:8
;
+; GFX950-LABEL: main:
+; GFX950: ; %bb.0: ; %bb
+; GFX950-NEXT: s_mov_b64 s[2:3], exec
+; GFX950-NEXT: .LBB0_1: ; =>This Inner Loop Header: Depth=1
+; GFX950-NEXT: v_readfirstlane_b32 s4, v0
+; GFX950-NEXT: v_readfirstlane_b32 s5, v1
+; GFX950-NEXT: v_readfirstlane_b32 s6, v2
+; GFX950-NEXT: v_readfirstlane_b32 s7, v3
+; GFX950-NEXT: v_cmp_eq_u64_e32 vcc, s[4:5], v[0:1]
+; GFX950-NEXT: s_nop 0
+; GFX950-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], v[2:3]
+; GFX950-NEXT: s_and_b64 s[0:1], vcc, s[0:1]
+; GFX950-NEXT: s_and_saveexec_b64 s[0:1], s[0:1]
+; GFX950-NEXT: buffer_load_format_d16_xyz v[6:7], v4, s[4:7], 0 idxen
+; GFX950-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX950-NEXT: ; implicit-def: $vgpr4
+; GFX950-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX950-NEXT: s_cbranch_execnz .LBB0_1
+; GFX950-NEXT: ; %bb.2:
+; GFX950-NEXT: s_mov_b64 exec, s[2:3]
+; GFX950-NEXT: s_waitcnt vmcnt(0)
+; GFX950-NEXT: v_lshrrev_b32_e32 v0, 16, v6
+; GFX950-NEXT: v_and_b32_e32 v1, 0xffff, v7
+; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: ds_write2_b32 v2, v0, v1 offset0:7 offset1:8
+;
; GFX9-LABEL: main:
; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_mov_b64 s[2:3], exec
>From 4dde499dcb4433ce88b13b5fc105980e4ad90f96 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Fri, 17 Jul 2026 15:46:04 +0100
Subject: [PATCH 2/2] [AMDGPU] Fix computeKnownBitsForTargetNode for
AMDGPUISD::LDS
This was assuming a maximum LDS size of 64 KiB which is not true on all
targets.
---
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 3 ++-
.../AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll | 2 +-
.../AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll | 2 +-
3 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 4858009fecff5..8024893dccb85 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -6169,7 +6169,8 @@ void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
auto *GA = cast<GlobalAddressSDNode>(Op.getOperand(0).getNode());
Align Alignment = GA->getGlobal()->getPointerAlignment(DAG.getDataLayout());
- Known.Zero.setHighBits(16);
+ Known.Zero.setBitsFrom(
+ Log2_32_Ceil(Subtarget->getAddressableLocalMemorySize()));
Known.Zero.setLowBits(Log2(Alignment));
break;
}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
index 73691eb8382b8..9715d85ee6ed4 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
@@ -61,7 +61,7 @@ define amdgpu_gs void @main(<4 x i32> %arg, i32 %arg1) {
; GFX950-NEXT: s_waitcnt vmcnt(0)
; GFX950-NEXT: v_lshrrev_b32_e32 v0, 16, v6
; GFX950-NEXT: v_and_b32_e32 v1, 0xffff, v7
-; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: v_mov_b32_e32 v2, esgs_ring at abs32@lo
; GFX950-NEXT: ds_write2_b32 v2, v0, v1 offset0:7 offset1:8
;
; GFX9-LABEL: main:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
index 130273e822b07..3bbb1ed13ed74 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
@@ -58,7 +58,7 @@ define amdgpu_gs void @main(ptr addrspace(8) %arg, i32 %arg1) {
; GFX950-NEXT: s_waitcnt vmcnt(0)
; GFX950-NEXT: v_lshrrev_b32_e32 v0, 16, v6
; GFX950-NEXT: v_and_b32_e32 v1, 0xffff, v7
-; GFX950-NEXT: v_mov_b32_e32 v2, 0
+; GFX950-NEXT: v_mov_b32_e32 v2, esgs_ring at abs32@lo
; GFX950-NEXT: ds_write2_b32 v2, v0, v1 offset0:7 offset1:8
;
; GFX9-LABEL: main:
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