[llvm] [AMDGPU][TTI] Refine gfx9 packed FP32 SLP costs for pair formation and shuffles (PR #208572)

[Matt Arsenault via llvm-commits]

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@@ -1042,6 +1042,17 @@ InstructionCost GCNTTIImpl::getVectorInstrCost(
                                        VIC);
     }
 
+    // Gfx9 packed <2 x f32> pair formation for v_pk_*_f32: lanes must occupy an
+    // aligned VGPR pair. A load-fed insert can be allocated into its slot for
+    // free; a compute-fed insert typically needs an alignment move, so charge 1.
+    // f32-only on gfx9 targets with packed FP32 ops.
+    if (Opcode == Instruction::InsertElement && EltSize == 32 &&
+        ST->hasPackedFP32Ops() && ST->getGeneration() == AMDGPUSubtarget::GFX9)
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arsenm wrote:

avoid generation checks, I don't see the point here given it already checks hasPackedFP32Ops

https://github.com/llvm/llvm-project/pull/208572