[llvm] [Reland][X86] Remove redundant `cmp` before `adc` after `lzcnt` or `tzcnt` (PR #210069)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 17 06:41:58 PDT 2026
https://github.com/VachanVY updated https://github.com/llvm/llvm-project/pull/210069
>From 6facdb497b9bbfdf6b0a1bdd74030c48f5103afe Mon Sep 17 00:00:00 2001
From: Vachan V Y <vachanvy05 at gmail.com>
Date: Thu, 16 Jul 2026 19:52:16 +0530
Subject: [PATCH 1/2] [X86] pre commit tests
---
.../X86/remove-redundant-cmp-lzcnt-i64.ll | 78 +++++++
.../CodeGen/X86/remove-redundant-cmp-lzcnt.ll | 195 +++++++++++++++++
.../X86/remove-redundant-cmp-tzcnt-i64.ll | 76 +++++++
.../CodeGen/X86/remove-redundant-cmp-tzcnt.ll | 205 ++++++++++++++++++
4 files changed, 554 insertions(+)
create mode 100644 llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt-i64.ll
create mode 100644 llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt.ll
create mode 100644 llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt-i64.ll
create mode 100644 llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt.ll
diff --git a/llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt-i64.ll b/llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt-i64.ll
new file mode 100644
index 0000000000000..09571fa20b711
--- /dev/null
+++ b/llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt-i64.ll
@@ -0,0 +1,78 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi,+lzcnt | FileCheck %s
+
+define i64 @remove_redundant_cmp_ult_lzcnt_i64(i64 %0) {
+; CHECK-LABEL: remove_redundant_cmp_ult_lzcnt_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lzcntq %rdi, %rax
+; CHECK-NEXT: cmpq $1, %rdi
+; CHECK-NEXT: adcq $0, %rax
+; CHECK-NEXT: retq
+ %2 = tail call i64 @llvm.ctlz.i64(i64 %0, i1 false)
+ %3 = icmp ult i64 %0, 1
+ %4 = zext i1 %3 to i64
+ %5 = add nuw nsw i64 %2, %4
+ ret i64 %5
+}
+
+define i64 @remove_redundant_cmp_ugt_lzcnt_i64(i64 %0) {
+; CHECK-LABEL: remove_redundant_cmp_ugt_lzcnt_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lzcntq %rdi, %rax
+; CHECK-NEXT: cmpq $2, %rdi
+; CHECK-NEXT: sbbq $-1, %rax
+; CHECK-NEXT: retq
+ %2 = tail call i64 @llvm.ctlz.i64(i64 %0, i1 false)
+ %3 = icmp ugt i64 %0, 1
+ %4 = zext i1 %3 to i64
+ %5 = add nuw nsw i64 %2, %4
+ ret i64 %5
+}
+
+define i64 @remove_redundant_cmp_ne_lzcnt_i64(i64 %0) {
+; CHECK-LABEL: remove_redundant_cmp_ne_lzcnt_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lzcntq %rdi, %rcx
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: cmpq $1, %rdi
+; CHECK-NEXT: setne %al
+; CHECK-NEXT: addq %rcx, %rax
+; CHECK-NEXT: retq
+ %2 = tail call i64 @llvm.ctlz.i64(i64 %0, i1 false)
+ %3 = icmp ne i64 %0, 1
+ %4 = zext i1 %3 to i64
+ %5 = add nuw nsw i64 %2, %4
+ ret i64 %5
+}
+
+define i64 @remove_redundant_cmp_sge_lzcnt_i64(i64 %0) {
+; CHECK-LABEL: remove_redundant_cmp_sge_lzcnt_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lzcntq %rdi, %rcx
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: testq %rdi, %rdi
+; CHECK-NEXT: setg %al
+; CHECK-NEXT: addq %rcx, %rax
+; CHECK-NEXT: retq
+ %2 = tail call i64 @llvm.ctlz.i64(i64 %0, i1 false)
+ %3 = icmp sge i64 %0, 1
+ %4 = zext i1 %3 to i64
+ %5 = add nuw nsw i64 %2, %4
+ ret i64 %5
+}
+
+define i64 @remove_redundant_cmp_sle_lzcnt_i64(i64 %0) {
+; CHECK-LABEL: remove_redundant_cmp_sle_lzcnt_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lzcntq %rdi, %rcx
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: cmpq $2, %rdi
+; CHECK-NEXT: setl %al
+; CHECK-NEXT: addq %rcx, %rax
+; CHECK-NEXT: retq
+ %2 = tail call i64 @llvm.ctlz.i64(i64 %0, i1 false)
+ %3 = icmp sle i64 %0, 1
+ %4 = zext i1 %3 to i64
+ %5 = add nuw nsw i64 %2, %4
+ ret i64 %5
+}
diff --git a/llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt.ll b/llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt.ll
new file mode 100644
index 0000000000000..f7725897533b0
--- /dev/null
+++ b/llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt.ll
@@ -0,0 +1,195 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi,+lzcnt | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+bmi,+lzcnt | FileCheck %s --check-prefix=X86
+
+define i32 @remove_redundant_cmp_eq_lzcnt_i32(i32 %0) {
+; X64-LABEL: remove_redundant_cmp_eq_lzcnt_i32:
+; X64: # %bb.0:
+; X64-NEXT: lzcntl %edi, %eax
+; X64-NEXT: cmpl $1, %edi
+; X64-NEXT: adcl $0, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: remove_redundant_cmp_eq_lzcnt_i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: lzcntl %ecx, %eax
+; X86-NEXT: cmpl $1, %ecx
+; X86-NEXT: adcl $0, %eax
+; X86-NEXT: retl
+ %2 = tail call i32 @llvm.ctlz.i32(i32 %0, i1 false)
+ %3 = icmp eq i32 %0, 0
+ %4 = zext i1 %3 to i32
+ %5 = add nuw nsw i32 %2, %4
+ ret i32 %5
+}
+
+define i32 @remove_redundant_cmp_uge_lzcnt_i32(i32 %0) {
+; X64-LABEL: remove_redundant_cmp_uge_lzcnt_i32:
+; X64: # %bb.0:
+; X64-NEXT: lzcntl %edi, %eax
+; X64-NEXT: cmpl $1, %edi
+; X64-NEXT: sbbl $-1, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: remove_redundant_cmp_uge_lzcnt_i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: lzcntl %ecx, %eax
+; X86-NEXT: cmpl $1, %ecx
+; X86-NEXT: sbbl $-1, %eax
+; X86-NEXT: retl
+ %2 = tail call i32 @llvm.ctlz.i32(i32 %0, i1 false)
+ %3 = icmp uge i32 %0, 1
+ %4 = zext i1 %3 to i32
+ %5 = add nuw nsw i32 %2, %4
+ ret i32 %5
+}
+
+define i32 @remove_redundant_cmp_ule_lzcnt_i32(i32 %0) {
+; X64-LABEL: remove_redundant_cmp_ule_lzcnt_i32:
+; X64: # %bb.0:
+; X64-NEXT: lzcntl %edi, %eax
+; X64-NEXT: cmpl $2, %edi
+; X64-NEXT: adcl $0, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: remove_redundant_cmp_ule_lzcnt_i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: lzcntl %ecx, %eax
+; X86-NEXT: cmpl $2, %ecx
+; X86-NEXT: adcl $0, %eax
+; X86-NEXT: retl
+ %2 = tail call i32 @llvm.ctlz.i32(i32 %0, i1 false)
+ %3 = icmp ule i32 %0, 1
+ %4 = zext i1 %3 to i32
+ %5 = add nuw nsw i32 %2, %4
+ ret i32 %5
+}
+
+define i32 @remove_redundant_cmp_slt_lzcnt_i32(i32 %0) {
+; X64-LABEL: remove_redundant_cmp_slt_lzcnt_i32:
+; X64: # %bb.0:
+; X64-NEXT: lzcntl %edi, %ecx
+; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: testl %edi, %edi
+; X64-NEXT: setle %al
+; X64-NEXT: addl %ecx, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: remove_redundant_cmp_slt_lzcnt_i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: lzcntl %ecx, %edx
+; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: testl %ecx, %ecx
+; X86-NEXT: setle %al
+; X86-NEXT: addl %edx, %eax
+; X86-NEXT: retl
+ %2 = tail call i32 @llvm.ctlz.i32(i32 %0, i1 false)
+ %3 = icmp slt i32 %0, 1
+ %4 = zext i1 %3 to i32
+ %5 = add nuw nsw i32 %2, %4
+ ret i32 %5
+}
+
+define i32 @remove_redundant_cmp_sgt_lzcnt_i32(i32 %0) {
+; X64-LABEL: remove_redundant_cmp_sgt_lzcnt_i32:
+; X64: # %bb.0:
+; X64-NEXT: lzcntl %edi, %ecx
+; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: cmpl $2, %edi
+; X64-NEXT: setge %al
+; X64-NEXT: addl %ecx, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: remove_redundant_cmp_sgt_lzcnt_i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: lzcntl %ecx, %edx
+; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: cmpl $2, %ecx
+; X86-NEXT: setge %al
+; X86-NEXT: addl %edx, %eax
+; X86-NEXT: retl
+ %2 = tail call i32 @llvm.ctlz.i32(i32 %0, i1 false)
+ %3 = icmp sgt i32 %0, 1
+ %4 = zext i1 %3 to i32
+ %5 = add nuw nsw i32 %2, %4
+ ret i32 %5
+}
+
+define i16 @remove_redundant_cmp_lzcnt_i16(i16 %0) {
+; X64-LABEL: remove_redundant_cmp_lzcnt_i16:
+; X64: # %bb.0:
+; X64-NEXT: lzcntw %di, %ax
+; X64-NEXT: cmpw $1, %di
+; X64-NEXT: adcw $0, %ax
+; X64-NEXT: retq
+;
+; X86-LABEL: remove_redundant_cmp_lzcnt_i16:
+; X86: # %bb.0:
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: lzcntw %cx, %ax
+; X86-NEXT: cmpw $1, %cx
+; X86-NEXT: adcw $0, %ax
+; X86-NEXT: retl
+ %2 = tail call i16 @llvm.ctlz.i16(i16 %0, i1 false)
+ %3 = icmp eq i16 %0, 0
+ %4 = zext i1 %3 to i16
+ %5 = add nuw nsw i16 %2, %4
+ ret i16 %5
+}
+
+define i32 @remove_redundant_cmp_lzcnt_no_constant(i32 %0, i32 %1) {
+; X64-LABEL: remove_redundant_cmp_lzcnt_no_constant:
+; X64: # %bb.0:
+; X64-NEXT: lzcntl %edi, %ecx
+; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: cmpl %esi, %edi
+; X64-NEXT: sete %al
+; X64-NEXT: addl %ecx, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: remove_redundant_cmp_lzcnt_no_constant:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: lzcntl %ecx, %edx
+; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: cmpl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: sete %al
+; X86-NEXT: addl %edx, %eax
+; X86-NEXT: retl
+ %3 = tail call i32 @llvm.ctlz.i32(i32 %0, i1 false)
+ %4 = icmp eq i32 %0, %1
+ %5 = zext i1 %4 to i32
+ %6 = add nuw nsw i32 %3, %5
+ ret i32 %6
+}
+
+define i32 @remove_redundant_cmp_lzcnt_wrong_const(i32 %0) {
+; X64-LABEL: remove_redundant_cmp_lzcnt_wrong_const:
+; X64: # %bb.0:
+; X64-NEXT: lzcntl %edi, %ecx
+; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: cmpl $2, %edi
+; X64-NEXT: sete %al
+; X64-NEXT: addl %ecx, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: remove_redundant_cmp_lzcnt_wrong_const:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: lzcntl %ecx, %edx
+; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: cmpl $2, %ecx
+; X86-NEXT: sete %al
+; X86-NEXT: addl %edx, %eax
+; X86-NEXT: retl
+ %2 = tail call i32 @llvm.ctlz.i32(i32 %0, i1 false)
+ %3 = icmp eq i32 %0, 2
+ %4 = zext i1 %3 to i32
+ %5 = add nuw nsw i32 %2, %4
+ ret i32 %5
+}
diff --git a/llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt-i64.ll b/llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt-i64.ll
new file mode 100644
index 0000000000000..3b72de62bbdf2
--- /dev/null
+++ b/llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt-i64.ll
@@ -0,0 +1,76 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi,+lzcnt | FileCheck %s
+
+define i64 @remove_redundant_cmp_eq_tzcnt_i64(i64 %0) {
+; CHECK-LABEL: remove_redundant_cmp_eq_tzcnt_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tzcntq %rdi, %rax
+; CHECK-NEXT: cmpq $1, %rdi
+; CHECK-NEXT: adcq $0, %rax
+; CHECK-NEXT: retq
+ %2 = tail call i64 @llvm.cttz.i64(i64 %0, i1 false)
+ %3 = icmp eq i64 %0, 0
+ %4 = zext i1 %3 to i64
+ %5 = add nuw nsw i64 %2, %4
+ ret i64 %5
+}
+
+define i64 @remove_redundant_cmp_uge_tzcnt_i64(i64 %0) {
+; CHECK-LABEL: remove_redundant_cmp_uge_tzcnt_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tzcntq %rdi, %rax
+; CHECK-NEXT: cmpq $1, %rdi
+; CHECK-NEXT: sbbq $-1, %rax
+; CHECK-NEXT: retq
+ %2 = tail call i64 @llvm.cttz.i64(i64 %0, i1 false)
+ %3 = icmp uge i64 %0, 1
+ %4 = zext i1 %3 to i64
+ %5 = add nuw nsw i64 %2, %4
+ ret i64 %5
+}
+
+define i64 @remove_redundant_cmp_ule_tzcnt_i64(i64 %0) {
+; CHECK-LABEL: remove_redundant_cmp_ule_tzcnt_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tzcntq %rdi, %rax
+; CHECK-NEXT: cmpq $2, %rdi
+; CHECK-NEXT: adcq $0, %rax
+; CHECK-NEXT: retq
+ %2 = tail call i64 @llvm.cttz.i64(i64 %0, i1 false)
+ %3 = icmp ule i64 %0, 1
+ %4 = zext i1 %3 to i64
+ %5 = add nuw nsw i64 %2, %4
+ ret i64 %5
+}
+
+define i64 @remove_redundant_cmp_slt_tzcnt_i64(i64 %0) {
+; CHECK-LABEL: remove_redundant_cmp_slt_tzcnt_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tzcntq %rdi, %rcx
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: testq %rdi, %rdi
+; CHECK-NEXT: setle %al
+; CHECK-NEXT: addq %rcx, %rax
+; CHECK-NEXT: retq
+ %2 = tail call i64 @llvm.cttz.i64(i64 %0, i1 false)
+ %3 = icmp slt i64 %0, 1
+ %4 = zext i1 %3 to i64
+ %5 = add nuw nsw i64 %2, %4
+ ret i64 %5
+}
+
+define i64 @remove_redundant_cmp_sgt_tzcnt_i64(i64 %0) {
+; CHECK-LABEL: remove_redundant_cmp_sgt_tzcnt_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tzcntq %rdi, %rcx
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: cmpq $2, %rdi
+; CHECK-NEXT: setge %al
+; CHECK-NEXT: addq %rcx, %rax
+; CHECK-NEXT: retq
+ %2 = tail call i64 @llvm.cttz.i64(i64 %0, i1 false)
+ %3 = icmp sgt i64 %0, 1
+ %4 = zext i1 %3 to i64
+ %5 = add nuw nsw i64 %2, %4
+ ret i64 %5
+}
diff --git a/llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt.ll b/llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt.ll
new file mode 100644
index 0000000000000..d6eafb5da1119
--- /dev/null
+++ b/llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt.ll
@@ -0,0 +1,205 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi,+lzcnt | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+bmi,+lzcnt | FileCheck %s --check-prefix=X86
+
+define i32 @remove_redundant_cmp_ult_tzcnt_i32(i32 %0) {
+; X64-LABEL: remove_redundant_cmp_ult_tzcnt_i32:
+; X64: # %bb.0:
+; X64-NEXT: tzcntl %edi, %eax
+; X64-NEXT: cmpl $1, %edi
+; X64-NEXT: adcl $0, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: remove_redundant_cmp_ult_tzcnt_i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: tzcntl %ecx, %eax
+; X86-NEXT: cmpl $1, %ecx
+; X86-NEXT: adcl $0, %eax
+; X86-NEXT: retl
+ %2 = tail call i32 @llvm.cttz.i32(i32 %0, i1 false)
+ %3 = icmp ult i32 %0, 1
+ %4 = zext i1 %3 to i32
+ %5 = add nuw nsw i32 %2, %4
+ ret i32 %5
+}
+
+define i32 @remove_redundant_cmp_ugt_tzcnt_i32(i32 %0) {
+; X64-LABEL: remove_redundant_cmp_ugt_tzcnt_i32:
+; X64: # %bb.0:
+; X64-NEXT: tzcntl %edi, %eax
+; X64-NEXT: cmpl $2, %edi
+; X64-NEXT: sbbl $-1, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: remove_redundant_cmp_ugt_tzcnt_i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: tzcntl %ecx, %eax
+; X86-NEXT: cmpl $2, %ecx
+; X86-NEXT: sbbl $-1, %eax
+; X86-NEXT: retl
+ %2 = tail call i32 @llvm.cttz.i32(i32 %0, i1 false)
+ %3 = icmp ugt i32 %0, 1
+ %4 = zext i1 %3 to i32
+ %5 = add nuw nsw i32 %2, %4
+ ret i32 %5
+}
+
+define i32 @remove_redundant_cmp_ne_tzcnt_i32(i32 %0) {
+; X64-LABEL: remove_redundant_cmp_ne_tzcnt_i32:
+; X64: # %bb.0:
+; X64-NEXT: tzcntl %edi, %ecx
+; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: cmpl $1, %edi
+; X64-NEXT: setne %al
+; X64-NEXT: addl %ecx, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: remove_redundant_cmp_ne_tzcnt_i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: tzcntl %ecx, %edx
+; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: cmpl $1, %ecx
+; X86-NEXT: setne %al
+; X86-NEXT: addl %edx, %eax
+; X86-NEXT: retl
+ %2 = tail call i32 @llvm.cttz.i32(i32 %0, i1 false)
+ %3 = icmp ne i32 %0, 1
+ %4 = zext i1 %3 to i32
+ %5 = add nuw nsw i32 %2, %4
+ ret i32 %5
+}
+
+define i32 @remove_redundant_cmp_sge_tzcnt_i32(i32 %0) {
+; X64-LABEL: remove_redundant_cmp_sge_tzcnt_i32:
+; X64: # %bb.0:
+; X64-NEXT: tzcntl %edi, %ecx
+; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: testl %edi, %edi
+; X64-NEXT: setg %al
+; X64-NEXT: addl %ecx, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: remove_redundant_cmp_sge_tzcnt_i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: tzcntl %ecx, %edx
+; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: testl %ecx, %ecx
+; X86-NEXT: setg %al
+; X86-NEXT: addl %edx, %eax
+; X86-NEXT: retl
+ %2 = tail call i32 @llvm.cttz.i32(i32 %0, i1 false)
+ %3 = icmp sge i32 %0, 1
+ %4 = zext i1 %3 to i32
+ %5 = add nuw nsw i32 %2, %4
+ ret i32 %5
+}
+
+define i32 @remove_redundant_cmp_sle_tzcnt_i32(i32 %0) {
+; X64-LABEL: remove_redundant_cmp_sle_tzcnt_i32:
+; X64: # %bb.0:
+; X64-NEXT: tzcntl %edi, %ecx
+; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: cmpl $2, %edi
+; X64-NEXT: setl %al
+; X64-NEXT: addl %ecx, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: remove_redundant_cmp_sle_tzcnt_i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: tzcntl %ecx, %edx
+; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: cmpl $2, %ecx
+; X86-NEXT: setl %al
+; X86-NEXT: addl %edx, %eax
+; X86-NEXT: retl
+ %2 = tail call i32 @llvm.cttz.i32(i32 %0, i1 false)
+ %3 = icmp sle i32 %0, 1
+ %4 = zext i1 %3 to i32
+ %5 = add nuw nsw i32 %2, %4
+ ret i32 %5
+}
+
+define i16 @remove_redundant_cmp_tzcnt_i16(i16 %0) {
+; X64-LABEL: remove_redundant_cmp_tzcnt_i16:
+; X64: # %bb.0:
+; X64-NEXT: movl %edi, %eax
+; X64-NEXT: orl $65536, %eax # imm = 0x10000
+; X64-NEXT: tzcntl %eax, %eax
+; X64-NEXT: cmpw $1, %di
+; X64-NEXT: adcw $0, %ax
+; X64-NEXT: # kill: def $ax killed $ax killed $eax
+; X64-NEXT: retq
+;
+; X86-LABEL: remove_redundant_cmp_tzcnt_i16:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: orl $65536, %eax # imm = 0x10000
+; X86-NEXT: tzcntl %eax, %eax
+; X86-NEXT: cmpw $1, %cx
+; X86-NEXT: adcw $0, %ax
+; X86-NEXT: # kill: def $ax killed $ax killed $eax
+; X86-NEXT: retl
+ %2 = tail call i16 @llvm.cttz.i16(i16 %0, i1 false)
+ %3 = icmp eq i16 %0, 0
+ %4 = zext i1 %3 to i16
+ %5 = add nuw nsw i16 %2, %4
+ ret i16 %5
+}
+
+define i32 @remove_redundant_cmp_tzcnt_no_constant(i32 %0, i32 %1) {
+; X64-LABEL: remove_redundant_cmp_tzcnt_no_constant:
+; X64: # %bb.0:
+; X64-NEXT: tzcntl %edi, %ecx
+; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: cmpl %esi, %edi
+; X64-NEXT: sete %al
+; X64-NEXT: addl %ecx, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: remove_redundant_cmp_tzcnt_no_constant:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: tzcntl %ecx, %edx
+; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: cmpl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: sete %al
+; X86-NEXT: addl %edx, %eax
+; X86-NEXT: retl
+ %3 = tail call i32 @llvm.cttz.i32(i32 %0, i1 false)
+ %4 = icmp eq i32 %0, %1
+ %5 = zext i1 %4 to i32
+ %6 = add nuw nsw i32 %3, %5
+ ret i32 %6
+}
+
+define i32 @remove_redundant_cmp_tzcnt_wrong_const(i32 %0) {
+; X64-LABEL: remove_redundant_cmp_tzcnt_wrong_const:
+; X64: # %bb.0:
+; X64-NEXT: tzcntl %edi, %ecx
+; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: cmpl $2, %edi
+; X64-NEXT: sete %al
+; X64-NEXT: addl %ecx, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: remove_redundant_cmp_tzcnt_wrong_const:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: tzcntl %ecx, %edx
+; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: cmpl $2, %ecx
+; X86-NEXT: sete %al
+; X86-NEXT: addl %edx, %eax
+; X86-NEXT: retl
+ %2 = tail call i32 @llvm.cttz.i32(i32 %0, i1 false)
+ %3 = icmp eq i32 %0, 2
+ %4 = zext i1 %3 to i32
+ %5 = add nuw nsw i32 %2, %4
+ ret i32 %5
+}
>From b8bd3ad9effc9ed42c1deb8989f74de4789e5d8d Mon Sep 17 00:00:00 2001
From: Vachan V Y <vachanvy05 at gmail.com>
Date: Fri, 17 Jul 2026 19:05:46 +0530
Subject: [PATCH 2/2] [X86] optimization + CHECK line DIFF
---
llvm/lib/Target/X86/X86InstrInfo.cpp | 43 ++++++++++++++++++-
.../X86/remove-redundant-cmp-lzcnt-i64.ll | 1 -
.../CodeGen/X86/remove-redundant-cmp-lzcnt.ll | 15 ++-----
.../X86/remove-redundant-cmp-tzcnt-i64.ll | 2 -
.../CodeGen/X86/remove-redundant-cmp-tzcnt.ll | 5 +--
5 files changed, 46 insertions(+), 20 deletions(-)
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index cbbfeb84e5838..9c769f0db30f4 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -4998,6 +4998,27 @@ bool X86InstrInfo::isRedundantFlagInstr(const MachineInstr &FlagI,
}
}
+inline static bool isCmpRedundantAfterLTZCNT(Register SrcReg, Register SrcReg2,
+ int64_t ImmMask, int64_t ImmValue,
+ const MachineInstr &OI) {
+ switch (OI.getOpcode()) {
+ default:
+ return false;
+ case X86::LZCNT16rr:
+ case X86::LZCNT32rr:
+ case X86::LZCNT64rr:
+ case X86::TZCNT16rr:
+ case X86::TZCNT32rr:
+ case X86::TZCNT64rr: {
+ if (ImmMask != 0 && !SrcReg2.isValid() && ImmValue == 1 &&
+ OI.getOperand(1).isReg() && SrcReg == OI.getOperand(1).getReg()) {
+ return true;
+ }
+ return false;
+ }
+ }
+}
+
#define CASE_EVEX(OP) \
case X86::OP: \
case X86::OP##_EVEX:
@@ -5362,6 +5383,7 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
MachineInstr *MI = nullptr;
MachineInstr *Sub = nullptr;
MachineInstr *Movr0Inst = nullptr;
+ MachineInstr *LTZCNTInst = nullptr;
SmallVector<std::pair<MachineInstr *, unsigned>, 4> InstsToUpdate;
bool NoSignFlag = false;
bool ClearsOverflowFlag = false;
@@ -5444,6 +5466,12 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
break;
}
+ if (isCmpRedundantAfterLTZCNT(SrcReg, SrcReg2, CmpMask, CmpValue,
+ Inst)) {
+ LTZCNTInst = &Inst;
+ break;
+ }
+
// MOV32r0 is implemented with xor which clobbers condition code. It is
// safe to move up, if the definition to EFLAGS is dead and earlier
// instructions do not read or write EFLAGS.
@@ -5476,7 +5504,7 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
}
}
- if (MI || Sub)
+ if (MI || Sub || LTZCNTInst)
break;
// Reached begin of basic block. Continue in predecessor if there is
@@ -5619,6 +5647,19 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
ShouldUpdateCC = true;
}
+ if (LTZCNTInst) {
+ unsigned InstCode = Instr.getOpcode();
+ bool UsesOnlyCF = X86::isADC(InstCode) || X86::isSBB(InstCode) ||
+ X86::isRCL(InstCode) || X86::isRCR(InstCode) ||
+ OldCC == X86::COND_B || OldCC == X86::COND_AE;
+ if (!UsesOnlyCF)
+ return false;
+
+ MI = LTZCNTInst;
+ FlagsMayLiveOut = false;
+ break;
+ }
+
if (ShouldUpdateCC && ReplacementCC != OldCC) {
// Push the MachineInstr to OpsToUpdate.
// If it is safe to remove CmpInstr, the condition code of these
diff --git a/llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt-i64.ll b/llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt-i64.ll
index 09571fa20b711..2473c5fd6cb1c 100644
--- a/llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt-i64.ll
+++ b/llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt-i64.ll
@@ -5,7 +5,6 @@ define i64 @remove_redundant_cmp_ult_lzcnt_i64(i64 %0) {
; CHECK-LABEL: remove_redundant_cmp_ult_lzcnt_i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lzcntq %rdi, %rax
-; CHECK-NEXT: cmpq $1, %rdi
; CHECK-NEXT: adcq $0, %rax
; CHECK-NEXT: retq
%2 = tail call i64 @llvm.ctlz.i64(i64 %0, i1 false)
diff --git a/llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt.ll b/llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt.ll
index f7725897533b0..7658e7e96c93c 100644
--- a/llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt.ll
+++ b/llvm/test/CodeGen/X86/remove-redundant-cmp-lzcnt.ll
@@ -6,15 +6,12 @@ define i32 @remove_redundant_cmp_eq_lzcnt_i32(i32 %0) {
; X64-LABEL: remove_redundant_cmp_eq_lzcnt_i32:
; X64: # %bb.0:
; X64-NEXT: lzcntl %edi, %eax
-; X64-NEXT: cmpl $1, %edi
; X64-NEXT: adcl $0, %eax
; X64-NEXT: retq
;
; X86-LABEL: remove_redundant_cmp_eq_lzcnt_i32:
; X86: # %bb.0:
-; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: lzcntl %ecx, %eax
-; X86-NEXT: cmpl $1, %ecx
+; X86-NEXT: lzcntl {{[0-9]+}}(%esp), %eax
; X86-NEXT: adcl $0, %eax
; X86-NEXT: retl
%2 = tail call i32 @llvm.ctlz.i32(i32 %0, i1 false)
@@ -28,15 +25,12 @@ define i32 @remove_redundant_cmp_uge_lzcnt_i32(i32 %0) {
; X64-LABEL: remove_redundant_cmp_uge_lzcnt_i32:
; X64: # %bb.0:
; X64-NEXT: lzcntl %edi, %eax
-; X64-NEXT: cmpl $1, %edi
; X64-NEXT: sbbl $-1, %eax
; X64-NEXT: retq
;
; X86-LABEL: remove_redundant_cmp_uge_lzcnt_i32:
; X86: # %bb.0:
-; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: lzcntl %ecx, %eax
-; X86-NEXT: cmpl $1, %ecx
+; X86-NEXT: lzcntl {{[0-9]+}}(%esp), %eax
; X86-NEXT: sbbl $-1, %eax
; X86-NEXT: retl
%2 = tail call i32 @llvm.ctlz.i32(i32 %0, i1 false)
@@ -124,15 +118,12 @@ define i16 @remove_redundant_cmp_lzcnt_i16(i16 %0) {
; X64-LABEL: remove_redundant_cmp_lzcnt_i16:
; X64: # %bb.0:
; X64-NEXT: lzcntw %di, %ax
-; X64-NEXT: cmpw $1, %di
; X64-NEXT: adcw $0, %ax
; X64-NEXT: retq
;
; X86-LABEL: remove_redundant_cmp_lzcnt_i16:
; X86: # %bb.0:
-; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: lzcntw %cx, %ax
-; X86-NEXT: cmpw $1, %cx
+; X86-NEXT: lzcntw {{[0-9]+}}(%esp), %ax
; X86-NEXT: adcw $0, %ax
; X86-NEXT: retl
%2 = tail call i16 @llvm.ctlz.i16(i16 %0, i1 false)
diff --git a/llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt-i64.ll b/llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt-i64.ll
index 3b72de62bbdf2..a378156c639ef 100644
--- a/llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt-i64.ll
+++ b/llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt-i64.ll
@@ -5,7 +5,6 @@ define i64 @remove_redundant_cmp_eq_tzcnt_i64(i64 %0) {
; CHECK-LABEL: remove_redundant_cmp_eq_tzcnt_i64:
; CHECK: # %bb.0:
; CHECK-NEXT: tzcntq %rdi, %rax
-; CHECK-NEXT: cmpq $1, %rdi
; CHECK-NEXT: adcq $0, %rax
; CHECK-NEXT: retq
%2 = tail call i64 @llvm.cttz.i64(i64 %0, i1 false)
@@ -19,7 +18,6 @@ define i64 @remove_redundant_cmp_uge_tzcnt_i64(i64 %0) {
; CHECK-LABEL: remove_redundant_cmp_uge_tzcnt_i64:
; CHECK: # %bb.0:
; CHECK-NEXT: tzcntq %rdi, %rax
-; CHECK-NEXT: cmpq $1, %rdi
; CHECK-NEXT: sbbq $-1, %rax
; CHECK-NEXT: retq
%2 = tail call i64 @llvm.cttz.i64(i64 %0, i1 false)
diff --git a/llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt.ll b/llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt.ll
index d6eafb5da1119..b2eca56be3300 100644
--- a/llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt.ll
+++ b/llvm/test/CodeGen/X86/remove-redundant-cmp-tzcnt.ll
@@ -6,15 +6,12 @@ define i32 @remove_redundant_cmp_ult_tzcnt_i32(i32 %0) {
; X64-LABEL: remove_redundant_cmp_ult_tzcnt_i32:
; X64: # %bb.0:
; X64-NEXT: tzcntl %edi, %eax
-; X64-NEXT: cmpl $1, %edi
; X64-NEXT: adcl $0, %eax
; X64-NEXT: retq
;
; X86-LABEL: remove_redundant_cmp_ult_tzcnt_i32:
; X86: # %bb.0:
-; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: tzcntl %ecx, %eax
-; X86-NEXT: cmpl $1, %ecx
+; X86-NEXT: tzcntl {{[0-9]+}}(%esp), %eax
; X86-NEXT: adcl $0, %eax
; X86-NEXT: retl
%2 = tail call i32 @llvm.cttz.i32(i32 %0, i1 false)
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