[llvm] [SelectionDAG] Fold constant min/max vector reductions (PR #209190)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 17 05:12:53 PDT 2026
https://github.com/mygitljf updated https://github.com/llvm/llvm-project/pull/209190
>From feb25b7db006bc12c6c69bb10c73af0f1dd77076 Mon Sep 17 00:00:00 2001
From: mygitljf <2410316423 at qq.com>
Date: Mon, 13 Jul 2026 21:58:15 +0800
Subject: [PATCH 1/6] [SelectionDAG] Fold constant min/max vector reductions
---
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 21 ++++-
.../rvv/vecreduce-minmax-constant-fold.ll | 93 +++++++++++++++++++
2 files changed, 109 insertions(+), 5 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/rvv/vecreduce-minmax-constant-fold.ll
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 626803ed92a40..61bd3ea527a8f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -7130,6 +7130,10 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
case ISD::CTPOP:
case ISD::CTLS:
case ISD::VECREDUCE_ADD:
+ case ISD::VECREDUCE_SMAX:
+ case ISD::VECREDUCE_SMIN:
+ case ISD::VECREDUCE_UMAX:
+ case ISD::VECREDUCE_UMIN:
case ISD::STEP_VECTOR: {
SDValue Ops = {N1};
if (SDValue Fold = FoldConstantArithmetic(Opcode, DL, VT, Ops))
@@ -7802,19 +7806,26 @@ SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL,
if (Opcode == ISD::BITCAST)
return SDValue();
- // Constant fold VECREDUCE_ADD with a BUILD_VECTOR of integer constants.
- if (Opcode == ISD::VECREDUCE_ADD && ISD::isBuildVectorOfConstantSDNodes(N1.getNode())) {
+ // Constant fold integer vector reductions with constant BUILD_VECTORs.
+ if ((Opcode == ISD::VECREDUCE_ADD || Opcode == ISD::VECREDUCE_SMAX ||
+ Opcode == ISD::VECREDUCE_SMIN || Opcode == ISD::VECREDUCE_UMAX ||
+ Opcode == ISD::VECREDUCE_UMIN) &&
+ ISD::isBuildVectorOfConstantSDNodes(N1.getNode())) {
unsigned EltBits = N1.getValueType().getScalarSizeInBits();
- APInt Acc = APInt::getZero(EltBits);
+ std::optional<APInt> Acc;
+ unsigned BaseOpcode = ISD::getVecReduceBaseOpcode(Opcode);
for (SDValue Elt : N1->op_values()) {
if (Elt.getOpcode() == ISD::POISON)
return getPOISON(VT);
if (Elt.isUndef() || cast<ConstantSDNode>(Elt)->isOpaque())
return SDValue();
- Acc += cast<ConstantSDNode>(Elt)->getAPIntValue().trunc(EltBits);
+ APInt Value = cast<ConstantSDNode>(Elt)->getAPIntValue().trunc(EltBits);
+ Acc = Acc ? FoldValue(BaseOpcode, *Acc, Value) : Value;
+ assert(Acc && "Unexpected vector reduction opcode");
}
+ assert(Acc && "Expected non-empty BUILD_VECTOR");
EVT EltVT = N1.getValueType().getScalarType();
- return getAnyExtOrTrunc(getConstant(Acc, DL, EltVT), DL, VT);
+ return getAnyExtOrTrunc(getConstant(*Acc, DL, EltVT), DL, VT);
}
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vecreduce-minmax-constant-fold.ll b/llvm/test/CodeGen/RISCV/rvv/vecreduce-minmax-constant-fold.ll
new file mode 100644
index 0000000000000..57bbcf7920fc3
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vecreduce-minmax-constant-fold.ll
@@ -0,0 +1,93 @@
+; RUN: llc -mtriple=riscv64 -mattr=+v -global-isel=0 -verify-machineinstrs < %s | FileCheck %s
+
+define i64 @test_const_smax() {
+; CHECK-LABEL: test_const_smax:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a0, 127
+; CHECK-NEXT: ret
+ %r = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> <i64 -128, i64 -1, i64 0, i64 127>)
+ ret i64 %r
+}
+
+define i64 @test_const_smin() {
+; CHECK-LABEL: test_const_smin:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a0, -128
+; CHECK-NEXT: ret
+ %r = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> <i64 -128, i64 -1, i64 0, i64 127>)
+ ret i64 %r
+}
+
+define i64 @test_const_umax() {
+; CHECK-LABEL: test_const_umax:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: ret
+ %r = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> <i64 -128, i64 -1, i64 0, i64 127>)
+ ret i64 %r
+}
+
+define i64 @test_const_umin() {
+; CHECK-LABEL: test_const_umin:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a0, 0
+; CHECK-NEXT: ret
+ %r = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> <i64 -128, i64 -1, i64 0, i64 127>)
+ ret i64 %r
+}
+
+define i64 @test_const_smax_i8() {
+; CHECK-LABEL: test_const_smax_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a0, 127
+; CHECK-NEXT: ret
+ %r = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> <i8 -128, i8 -1, i8 0, i8 127>)
+ %ext = sext i8 %r to i64
+ ret i64 %ext
+}
+
+define i64 @test_const_smin_i8() {
+; CHECK-LABEL: test_const_smin_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a0, -128
+; CHECK-NEXT: ret
+ %r = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> <i8 -128, i8 -1, i8 0, i8 127>)
+ %ext = sext i8 %r to i64
+ ret i64 %ext
+}
+
+define i64 @test_const_umax_i8() {
+; CHECK-LABEL: test_const_umax_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a0, 255
+; CHECK-NEXT: ret
+ %r = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> <i8 -128, i8 -1, i8 0, i8 127>)
+ %ext = zext i8 %r to i64
+ ret i64 %ext
+}
+
+define i64 @test_const_umin_i8() {
+; CHECK-LABEL: test_const_umin_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a0, 0
+; CHECK-NEXT: ret
+ %r = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> <i8 -128, i8 -1, i8 0, i8 127>)
+ %ext = zext i8 %r to i64
+ ret i64 %ext
+}
+
+define i64 @test_nonconst(<4 x i64> %v) {
+; CHECK-LABEL: test_nonconst:
+; CHECK: vredmax.vs
+; CHECK: ret
+ %r = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> %v)
+ ret i64 %r
+}
+
+define i64 @test_poison() {
+; CHECK-LABEL: test_poison:
+; CHECK-NOT: vredmax.vs
+; CHECK: ret
+ %r = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> <i64 -128, i64 -1, i64 poison, i64 127>)
+ ret i64 %r
+}
>From 66b51e1b0e6862d650fac5161be22ef3568db110 Mon Sep 17 00:00:00 2001
From: mygitljf <2410316423 at qq.com>
Date: Tue, 14 Jul 2026 10:31:05 +0800
Subject: [PATCH 2/6] [RISCV] Simplify vector reduction test invocation
---
llvm/test/CodeGen/RISCV/rvv/vecreduce-minmax-constant-fold.ll | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vecreduce-minmax-constant-fold.ll b/llvm/test/CodeGen/RISCV/rvv/vecreduce-minmax-constant-fold.ll
index 57bbcf7920fc3..e6231e3eb7f8c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vecreduce-minmax-constant-fold.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vecreduce-minmax-constant-fold.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=riscv64 -mattr=+v -global-isel=0 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+v < %s | FileCheck %s
define i64 @test_const_smax() {
; CHECK-LABEL: test_const_smax:
>From 8a2948070b0a68ebbbd6941df58663b3ea217cb0 Mon Sep 17 00:00:00 2001
From: mygitljf <2410316423 at qq.com>
Date: Tue, 14 Jul 2026 17:23:31 +0800
Subject: [PATCH 3/6] [SelectionDAG] Share integer identity values
---
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 55 ++++++++++++++-----
1 file changed, 42 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 61bd3ea527a8f..bb8cb679f88fb 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -7483,6 +7483,28 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
return V;
}
+static std::optional<APInt> getIntegerIdentity(unsigned Opcode,
+ unsigned BitWidth) {
+ switch (Opcode) {
+ default:
+ return std::nullopt;
+ case ISD::ADD:
+ case ISD::OR:
+ case ISD::XOR:
+ case ISD::UMAX:
+ return APInt::getZero(BitWidth);
+ case ISD::MUL:
+ return APInt(BitWidth, 1);
+ case ISD::AND:
+ case ISD::UMIN:
+ return APInt::getAllOnes(BitWidth);
+ case ISD::SMAX:
+ return APInt::getSignedMinValue(BitWidth);
+ case ISD::SMIN:
+ return APInt::getSignedMaxValue(BitWidth);
+ }
+}
+
static std::optional<APInt> FoldValue(unsigned Opcode, const APInt &C1,
const APInt &C2) {
switch (Opcode) {
@@ -7812,20 +7834,22 @@ SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL,
Opcode == ISD::VECREDUCE_UMIN) &&
ISD::isBuildVectorOfConstantSDNodes(N1.getNode())) {
unsigned EltBits = N1.getValueType().getScalarSizeInBits();
- std::optional<APInt> Acc;
+ EVT EltVT = N1.getValueType().getScalarType();
unsigned BaseOpcode = ISD::getVecReduceBaseOpcode(Opcode);
+ std::optional<APInt> Identity = getIntegerIdentity(BaseOpcode, EltBits);
+ assert(Identity && "Unexpected vector reduction opcode");
+ APInt Acc = *Identity;
for (SDValue Elt : N1->op_values()) {
if (Elt.getOpcode() == ISD::POISON)
return getPOISON(VT);
if (Elt.isUndef() || cast<ConstantSDNode>(Elt)->isOpaque())
return SDValue();
APInt Value = cast<ConstantSDNode>(Elt)->getAPIntValue().trunc(EltBits);
- Acc = Acc ? FoldValue(BaseOpcode, *Acc, Value) : Value;
- assert(Acc && "Unexpected vector reduction opcode");
+ std::optional<APInt> Folded = FoldValue(BaseOpcode, Acc, Value);
+ assert(Folded && "Unexpected vector reduction opcode");
+ Acc = *Folded;
}
- assert(Acc && "Expected non-empty BUILD_VECTOR");
- EVT EltVT = N1.getValueType().getScalarType();
- return getAnyExtOrTrunc(getConstant(*Acc, DL, EltVT), DL, VT);
+ return getAnyExtOrTrunc(getConstant(Acc, DL, EltVT), DL, VT);
}
}
@@ -15077,16 +15101,21 @@ SDValue SelectionDAG::getIdentityElement(unsigned Opcode, const SDLoc &DL,
case ISD::OR:
case ISD::XOR:
case ISD::UMAX:
- return getConstant(0, DL, VT);
case ISD::MUL:
- return getConstant(1, DL, VT);
case ISD::AND:
- case ISD::UMIN:
- return getAllOnesConstant(DL, VT);
+ case ISD::UMIN: {
+ std::optional<APInt> Identity =
+ getIntegerIdentity(Opcode, VT.getScalarSizeInBits());
+ assert(Identity && "Unexpected integer identity opcode");
+ return getConstant(*Identity, DL, VT);
+ }
case ISD::SMAX:
- return getConstant(APInt::getSignedMinValue(VT.getSizeInBits()), DL, VT);
- case ISD::SMIN:
- return getConstant(APInt::getSignedMaxValue(VT.getSizeInBits()), DL, VT);
+ case ISD::SMIN: {
+ std::optional<APInt> Identity =
+ getIntegerIdentity(Opcode, VT.getSizeInBits());
+ assert(Identity && "Unexpected integer identity opcode");
+ return getConstant(*Identity, DL, VT);
+ }
case ISD::FADD:
// If flags allow, prefer positive zero since it's generally cheaper
// to materialize on most targets.
>From cc437b566375fc4ac303ecc2746431c2aafe9c82 Mon Sep 17 00:00:00 2001
From: mygitljf <2410316423 at qq.com>
Date: Tue, 14 Jul 2026 19:42:32 +0800
Subject: [PATCH 4/6] [SelectionDAG] Use scalar integer identities
---
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 63 ++++++++-----------
1 file changed, 27 insertions(+), 36 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index bb8cb679f88fb..d06d1ad14e542 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -7483,27 +7483,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
return V;
}
-static std::optional<APInt> getIntegerIdentity(unsigned Opcode,
- unsigned BitWidth) {
- switch (Opcode) {
- default:
- return std::nullopt;
- case ISD::ADD:
- case ISD::OR:
- case ISD::XOR:
- case ISD::UMAX:
- return APInt::getZero(BitWidth);
- case ISD::MUL:
- return APInt(BitWidth, 1);
- case ISD::AND:
- case ISD::UMIN:
- return APInt::getAllOnes(BitWidth);
- case ISD::SMAX:
- return APInt::getSignedMinValue(BitWidth);
- case ISD::SMIN:
- return APInt::getSignedMaxValue(BitWidth);
- }
-}
+static APInt getIntegerIdentity(unsigned Opcode, unsigned BitWidth);
static std::optional<APInt> FoldValue(unsigned Opcode, const APInt &C1,
const APInt &C2) {
@@ -7836,9 +7816,7 @@ SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL,
unsigned EltBits = N1.getValueType().getScalarSizeInBits();
EVT EltVT = N1.getValueType().getScalarType();
unsigned BaseOpcode = ISD::getVecReduceBaseOpcode(Opcode);
- std::optional<APInt> Identity = getIntegerIdentity(BaseOpcode, EltBits);
- assert(Identity && "Unexpected vector reduction opcode");
- APInt Acc = *Identity;
+ APInt Acc = getIntegerIdentity(BaseOpcode, EltBits);
for (SDValue Elt : N1->op_values()) {
if (Elt.getOpcode() == ISD::POISON)
return getPOISON(VT);
@@ -15092,6 +15070,27 @@ SDValue SelectionDAG::getTokenFactor(const SDLoc &DL,
return getNode(ISD::TokenFactor, DL, MVT::Other, Vals);
}
+static APInt getIntegerIdentity(unsigned Opcode, unsigned BitWidth) {
+ switch (Opcode) {
+ default:
+ llvm_unreachable("Unexpected integer identity opcode");
+ case ISD::ADD:
+ case ISD::OR:
+ case ISD::XOR:
+ case ISD::UMAX:
+ return APInt::getZero(BitWidth);
+ case ISD::MUL:
+ return APInt(BitWidth, 1);
+ case ISD::AND:
+ case ISD::UMIN:
+ return APInt::getAllOnes(BitWidth);
+ case ISD::SMAX:
+ return APInt::getSignedMinValue(BitWidth);
+ case ISD::SMIN:
+ return APInt::getSignedMaxValue(BitWidth);
+ }
+}
+
SDValue SelectionDAG::getIdentityElement(unsigned Opcode, const SDLoc &DL,
EVT VT, SDNodeFlags Flags) {
switch (Opcode) {
@@ -15103,19 +15102,11 @@ SDValue SelectionDAG::getIdentityElement(unsigned Opcode, const SDLoc &DL,
case ISD::UMAX:
case ISD::MUL:
case ISD::AND:
- case ISD::UMIN: {
- std::optional<APInt> Identity =
- getIntegerIdentity(Opcode, VT.getScalarSizeInBits());
- assert(Identity && "Unexpected integer identity opcode");
- return getConstant(*Identity, DL, VT);
- }
+ case ISD::UMIN:
case ISD::SMAX:
- case ISD::SMIN: {
- std::optional<APInt> Identity =
- getIntegerIdentity(Opcode, VT.getSizeInBits());
- assert(Identity && "Unexpected integer identity opcode");
- return getConstant(*Identity, DL, VT);
- }
+ case ISD::SMIN:
+ return getConstant(getIntegerIdentity(Opcode, VT.getScalarSizeInBits()), DL,
+ VT);
case ISD::FADD:
// If flags allow, prefer positive zero since it's generally cheaper
// to materialize on most targets.
>From c796a9d756b119ffab5448691f1ff1c50ed87c93 Mon Sep 17 00:00:00 2001
From: mygitljf <2410316423 at qq.com>
Date: Tue, 14 Jul 2026 20:16:59 +0800
Subject: [PATCH 5/6] [SelectionDAG] Polish vector reduction folding
---
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 2 +-
.../RISCV/rvv/vecreduce-minmax-constant-fold.ll | 12 ++++++++----
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index d06d1ad14e542..da0303e386228 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -7814,7 +7814,6 @@ SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL,
Opcode == ISD::VECREDUCE_UMIN) &&
ISD::isBuildVectorOfConstantSDNodes(N1.getNode())) {
unsigned EltBits = N1.getValueType().getScalarSizeInBits();
- EVT EltVT = N1.getValueType().getScalarType();
unsigned BaseOpcode = ISD::getVecReduceBaseOpcode(Opcode);
APInt Acc = getIntegerIdentity(BaseOpcode, EltBits);
for (SDValue Elt : N1->op_values()) {
@@ -7827,6 +7826,7 @@ SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL,
assert(Folded && "Unexpected vector reduction opcode");
Acc = *Folded;
}
+ EVT EltVT = N1.getValueType().getScalarType();
return getAnyExtOrTrunc(getConstant(Acc, DL, EltVT), DL, VT);
}
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vecreduce-minmax-constant-fold.ll b/llvm/test/CodeGen/RISCV/rvv/vecreduce-minmax-constant-fold.ll
index e6231e3eb7f8c..822e91026e823 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vecreduce-minmax-constant-fold.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vecreduce-minmax-constant-fold.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=riscv64 -mattr=+v < %s | FileCheck %s
define i64 @test_const_smax() {
@@ -78,16 +79,19 @@ define i64 @test_const_umin_i8() {
define i64 @test_nonconst(<4 x i64> %v) {
; CHECK-LABEL: test_nonconst:
-; CHECK: vredmax.vs
-; CHECK: ret
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vredmax.vs v8, v8, v8
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
%r = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> %v)
ret i64 %r
}
define i64 @test_poison() {
; CHECK-LABEL: test_poison:
-; CHECK-NOT: vredmax.vs
-; CHECK: ret
+; CHECK: # %bb.0:
+; CHECK-NEXT: ret
%r = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> <i64 -128, i64 -1, i64 poison, i64 127>)
ret i64 %r
}
>From eaa969d6eede5cfeacee16b4f99914c009110286 Mon Sep 17 00:00:00 2001
From: mygitljf <2410316423 at qq.com>
Date: Fri, 17 Jul 2026 15:56:12 +0800
Subject: [PATCH 6/6] [SelectionDAG] Move integer identity helper
---
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 42 +++++++++----------
1 file changed, 20 insertions(+), 22 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index da0303e386228..b865c07c9f1e8 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -7483,7 +7483,26 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
return V;
}
-static APInt getIntegerIdentity(unsigned Opcode, unsigned BitWidth);
+static APInt getIntegerIdentity(unsigned Opcode, unsigned BitWidth) {
+ switch (Opcode) {
+ default:
+ llvm_unreachable("Unexpected integer identity opcode");
+ case ISD::ADD:
+ case ISD::OR:
+ case ISD::XOR:
+ case ISD::UMAX:
+ return APInt::getZero(BitWidth);
+ case ISD::MUL:
+ return APInt(BitWidth, 1);
+ case ISD::AND:
+ case ISD::UMIN:
+ return APInt::getAllOnes(BitWidth);
+ case ISD::SMAX:
+ return APInt::getSignedMinValue(BitWidth);
+ case ISD::SMIN:
+ return APInt::getSignedMaxValue(BitWidth);
+ }
+}
static std::optional<APInt> FoldValue(unsigned Opcode, const APInt &C1,
const APInt &C2) {
@@ -15070,27 +15089,6 @@ SDValue SelectionDAG::getTokenFactor(const SDLoc &DL,
return getNode(ISD::TokenFactor, DL, MVT::Other, Vals);
}
-static APInt getIntegerIdentity(unsigned Opcode, unsigned BitWidth) {
- switch (Opcode) {
- default:
- llvm_unreachable("Unexpected integer identity opcode");
- case ISD::ADD:
- case ISD::OR:
- case ISD::XOR:
- case ISD::UMAX:
- return APInt::getZero(BitWidth);
- case ISD::MUL:
- return APInt(BitWidth, 1);
- case ISD::AND:
- case ISD::UMIN:
- return APInt::getAllOnes(BitWidth);
- case ISD::SMAX:
- return APInt::getSignedMinValue(BitWidth);
- case ISD::SMIN:
- return APInt::getSignedMaxValue(BitWidth);
- }
-}
-
SDValue SelectionDAG::getIdentityElement(unsigned Opcode, const SDLoc &DL,
EVT VT, SDNodeFlags Flags) {
switch (Opcode) {
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