[llvm] 2a006df - [AArch64][GlobalISel] Add sign bits for G_VASHR (#210269)

[via llvm-commits]

Author: Joel Walker
Date: 2026-07-17T12:49:00+02:00
New Revision: 2a006dff821342c1726fd3137f804186851a26bb

URL: https://github.com/llvm/llvm-project/commit/2a006dff821342c1726fd3137f804186851a26bb
DIFF: https://github.com/llvm/llvm-project/commit/2a006dff821342c1726fd3137f804186851a26bb.diff

LOG: [AArch64][GlobalISel] Add sign bits for G_VASHR (#210269)

Ports the `AArch64ISD::VASHR` case from
`ComputeNumSignBitsForTargetNode` to the GlobalISel hook: an arithmetic
right shift by K adds K copies of the sign bit, so the result has
`min(SignBits(Src) + K, ScalarSizeInBits)` sign bits. `G_VASHR`'s shift
amount is always an immediate in `[1, ElementBits]`.

Follow-up to #198314, which added the `G_FCM*` cases.

Assisted by Claude (Anthropic).

Added: 
    llvm/test/CodeGen/AArch64/GlobalISel/knownbits-vashr.mir

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index c2956226e4a92..46d1a08079423 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -42,6 +42,7 @@
 #include "llvm/CodeGen/Analysis.h"
 #include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/ComplexDeinterleavingPass.h"
+#include "llvm/CodeGen/GlobalISel/GISelValueTracking.h"
 #include "llvm/CodeGen/GlobalISel/Utils.h"
 #include "llvm/CodeGen/ISDOpcodes.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
@@ -3099,6 +3100,13 @@ unsigned AArch64TargetLowering::computeNumSignBitsForTargetInstr(
     LLT VT = MRI.getType(R);
     return VT.getScalarSizeInBits();
   }
+  case AArch64::G_VASHR: {
+    unsigned Tmp = Analysis.computeNumSignBits(MI->getOperand(1).getReg(),
+                                               DemandedElts, Depth + 1);
+    LLT VT = MRI.getType(R);
+    return std::min<uint64_t>(Tmp + MI->getOperand(2).getImm(),
+                              VT.getScalarSizeInBits());
+  }
   default:
     return 1;
   }

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-vashr.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-vashr.mir
new file mode 100644
index 0000000000000..436e03ef1a065
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-vashr.mir
@@ -0,0 +1,57 @@
+# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=aarch64 -passes="print<gisel-value-tracking>" -filetype=null %s 2>&1 | FileCheck %s
+
+---
+name: VASHR
+body: |
+  bb.1:
+    liveins: $q0
+  ; CHECK-LABEL: name: @VASHR
+  ; CHECK-NEXT: %0:fpr KnownBits:???????????????? SignBits:1
+  ; CHECK-NEXT: %1:fpr KnownBits:???????????????? SignBits:4
+    %0:fpr(<8 x i16>) = COPY $q0
+    %1:fpr(<8 x i16>) = G_VASHR %0, 3
+    $q0 = COPY %1:fpr(<8 x i16>)
+...
+---
+name: VASHR_clamp
+body: |
+  bb.1:
+    liveins: $q0
+  ; CHECK-LABEL: name: @VASHR_clamp
+  ; CHECK-NEXT: %0:fpr KnownBits:???????? SignBits:1
+  ; CHECK-NEXT: %1:fpr KnownBits:???????? SignBits:8
+    %0:fpr(<16 x i8>) = COPY $q0
+    %1:fpr(<16 x i8>) = G_VASHR %0, 8
+    $q0 = COPY %1:fpr(<16 x i8>)
+...
+---
+name: VASHR_chain
+body: |
+  bb.1:
+    liveins: $q0
+  ; CHECK-LABEL: name: @VASHR_chain
+  ; CHECK-NEXT: %0:fpr KnownBits:???????????????? SignBits:1
+  ; CHECK-NEXT: %1:fpr KnownBits:???????????????? SignBits:4
+  ; CHECK-NEXT: %2:fpr KnownBits:???????????????? SignBits:9
+    %0:fpr(<8 x i16>) = COPY $q0
+    %1:fpr(<8 x i16>) = G_VASHR %0, 3
+    %2:fpr(<8 x i16>) = G_VASHR %1, 5
+    $q0 = COPY %2:fpr(<8 x i16>)
+...
+---
+name: VASHR_fcmeq
+body: |
+  bb.1:
+    liveins: $q0, $q1
+  ; CHECK-LABEL: name: @VASHR_fcmeq
+  ; CHECK-NEXT: %0:fpr KnownBits:???????????????????????????????? SignBits:1
+  ; CHECK-NEXT: %1:fpr KnownBits:???????????????????????????????? SignBits:1
+  ; CHECK-NEXT: %2:fpr KnownBits:???????????????????????????????? SignBits:32
+  ; CHECK-NEXT: %3:fpr KnownBits:???????????????????????????????? SignBits:32
+    %0:fpr(<4 x f32>) = COPY $q0
+    %1:fpr(<4 x f32>) = COPY $q1
+    %2:fpr(<4 x i32>) = G_FCMEQ %0:fpr, %1:fpr(<4 x f32>)
+    %3:fpr(<4 x i32>) = G_VASHR %2, 5
+    $q0 = COPY %3:fpr(<4 x i32>)
+...