[llvm] [WIP][X86] combineShiftRightLogical - fold srl(vecreduce_umax(x),bw-1) as MOVMSK signbit reduction (PR #210281)

[Simon Pilgrim via llvm-commits]

RKSimon wrote:

Converted to draft while I see if I can find a compromise vectorcombine patch

https://github.com/llvm/llvm-project/pull/210281