[llvm] [AMDGPU] Using feature to define vmem cacheline size (PR #207884)

[Matt Arsenault via llvm-commits]

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@@ -2149,6 +2158,7 @@ def FeatureISAVersion12 : FeatureSet<
    FeatureRealTrue16Insts,
    FeatureMTBUFInsts,
    FeatureFormattedMUBUFInsts,
+   FeatureDataCacheLineSize128
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arsenm wrote:

Right, but the cache line size property is independent of whether there is a prefetch instruction. This is conflating the two. The reported size for the prefetch insertion should be cachelinesize + whether there is a useful prefetch instruction 

https://github.com/llvm/llvm-project/pull/207884