[llvm] [X86] Lower vector integer division and remainder through float division (PR #205263)

[Adam Scott via llvm-commits]

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@@ -50431,6 +50441,155 @@ static SDValue combineMulToPMADD52(SDNode *N, const SDLoc &DL,
   return SDValue();
 }
 
+// x86 has no vector integer divide instructions. Lower vector
+// UDIV/SDIV/UREM/SREM through float division instead of scalarizing into N
+// scalar hardware divides.
+static SDValue combineIntDivRem(SDNode *N, SelectionDAG &DAG,
+                                TargetLowering::DAGCombinerInfo &DCI,
+                                const X86Subtarget &Subtarget) {
+  EVT VT = N->getValueType(0);
+  SDLoc DL(N);
+
+  // Run before the legalizer expands the division.
+  if (!VT.isVector() || !Subtarget.hasSSE2() || !DCI.isBeforeLegalizeOps())
+    return SDValue();
+
+  // Don't introduce a trapping FP divide under strict FP.
+  if (DAG.getMachineFunction().getFunction().hasFnAttribute(
+          Attribute::StrictFP))
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as4230 wrote:

You're right about i64 since the FP ops all carry SAE so I'll move it into the <=i32 branch.

The <=i32 case Im less sure about. We could add a branch so strictfp gets the fold too but that doesnt make the non-strictfp path x86-specific. If we applied SAE to every case instead then shapes like v8i16 -> v8f32 (256-bit) would widen ymm -> zmm on the divide for no reason since SAE on the divide only exists at 512-bit. So its either strictfp-only and mostly still generic or its everywhere and adds width we dont need. That said, if you want the strictfp <=i32 handling, say the word and Ill add it.

https://github.com/llvm/llvm-project/pull/205263