[llvm] [RISCV][P-ext] Add packed sign and zero extend intrinsics (PR #208685)

[Craig Topper via llvm-commits]

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@@ -6457,6 +6457,23 @@ static SDValue lowerVECTOR_SHUFFLEAsPUnzip(ShuffleVectorSDNode *SVN,
   return DAG.getNode(Opc, DL, VT, V1, V2);
 }
 
+// Match the shuffle mask <0, N, 2, N+2, ...>: even result lanes take the even
+// source lanes (operand 0) and odd result lanes come from the second operand.
+// XformToShuffleWithZero forms this from `(and src, low-half-mask)` with a zero
+// second operand, which is a packed zero-extend, i.e. RISCVISD::PPAIRE(src, 0).
+// Undef lanes (e.g. from widening the 32-bit view to a legal 64-bit type on
+// RV64) always match, since PPAIRE refines them.
+static bool isPackedZExtShuffleMask(ArrayRef<int> Mask) {
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topperc wrote:

This is really PairEvenShuffleMask right?

https://github.com/llvm/llvm-project/pull/208685