[llvm] [RISCV][P-ext] Add packed sign and zero extend intrinsics (PR #208685)

[Craig Topper via llvm-commits]

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@@ -6527,6 +6544,15 @@ SDValue RISCVTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
   if (Subtarget.hasStdExtP() && !Subtarget.hasVInstructions()) {
     ArrayRef<int> Mask = SVN->getMask();
 
+    // shuffle(src, zero, <0, N, 2, N+2, ...>) is a packed zero-extend:
+    // PPAIRE(src, 0). XformToShuffleWithZero forms this from an `and` with a
+    // low-half mask (see isVectorClearMaskLegal).
+    if (ISD::isConstantSplatVectorAllZeros(V2.getNode()) &&
+        isPackedZExtShuffleMask(Mask))
+      return DAG.getNode(RISCVISD::PPAIRE, DL, VT, V1,
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topperc wrote:

There's a lot of overlap with this and the shuffle matching from https://github.com/llvm/llvm-project/pull/210040/

https://github.com/llvm/llvm-project/pull/208685