[llvm] [AMDGPU][GlobalISel] Support lowering preloaded kernel arguments (PR #205049)
Keshav Vinayak Jha via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 16 21:06:24 PDT 2026
https://github.com/keshavvinayak01 updated https://github.com/llvm/llvm-project/pull/205049
>From 166c5bb30450d811c763c3fd4f9281a2bcb89d95 Mon Sep 17 00:00:00 2001
From: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
Date: Mon, 22 Jun 2026 13:23:45 +0530
Subject: [PATCH 1/6] Handle implicit hidden argument preloading for kernels
Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
---
llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp | 346 +++++++++++++++---
llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h | 5 +-
.../AMDGPU/GlobalISel/preload-kernargs.ll | 100 +++++
.../CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll | 16 +-
4 files changed, 406 insertions(+), 61 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/preload-kernargs.ll
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
index ca541c234ba0d..b3331d76df7f0 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
@@ -20,6 +20,7 @@
#include "llvm/CodeGen/Analysis.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
+#include "llvm/CodeGen/GlobalISel/Utils.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/PseudoSourceValueManager.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
@@ -296,6 +297,198 @@ struct AMDGPUOutgoingArgHandler : public AMDGPUOutgoingValueHandler {
assignValueToAddress(ValVReg, Addr, MemTy, MPO, VA);
}
};
+
+// Return the virtual register and type for a preloaded physical SGPR live-in.
+static std::pair<Register, LLT> getPreloadedLiveIn(MachineIRBuilder &B,
+ MCRegister PhysReg,
+ const SIRegisterInfo &TRI) {
+ MachineFunction &MF = B.getMF();
+ const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
+ const TargetRegisterClass *RC = TRI.getPhysRegBaseClass(PhysReg);
+ assert(RC && "expected a register class for preload SGPR");
+ LLT RegTy = LLT::scalar(TRI.getRegSizeInBits(*RC).getFixedValue());
+ return {getFunctionLiveInPhysReg(MF, *TII, PhysReg, *RC, B.getDL(), RegTy),
+ RegTy};
+}
+
+// Convert raw SGPR preload bits to the type expected by the formal argument.
+static Register adjustPreloadedArgType(MachineIRBuilder &B, Register Src,
+ LLT SrcTy, LLT DstTy) {
+ if (SrcTy == DstTy)
+ return Src;
+
+ LLT IntDstTy = DstTy.isPointer() ? LLT::scalar(DstTy.getSizeInBits()) : DstTy;
+ if (SrcTy.getSizeInBits() != IntDstTy.getSizeInBits())
+ Src = B.buildAnyExtOrTrunc(IntDstTy, Src).getReg(0);
+ else if (SrcTy != IntDstTy)
+ Src = B.buildBitcast(IntDstTy, Src).getReg(0);
+
+ if (DstTy.isPointer())
+ return B.buildIntToPtr(DstTy, Src).getReg(0);
+
+ return Src;
+}
+
+// Materialize a preloaded kernarg from its assigned SGPRs into DstReg.
+static void lowerPreloadedKernArg(MachineIRBuilder &B, Register DstReg,
+ LLT DstTy, uint64_t Offset, Align Alignment,
+ ArrayRef<MCRegister> PreloadRegs,
+ const SIRegisterInfo &TRI) {
+ assert(!PreloadRegs.empty());
+
+ // Kernarg preloads are assigned in 32-bit SGPR units.
+ const LLT S32 = LLT::scalar(32);
+
+ Register Value;
+ LLT ValueTy;
+ const bool IsPackedSubDword = DstTy.getSizeInBits() < 32 && Alignment < 4;
+
+ if (PreloadRegs.size() == 1) {
+ auto [LiveIn, LiveInTy] = getPreloadedLiveIn(B, PreloadRegs[0], TRI);
+ if (IsPackedSubDword) {
+ // Extract sub-dword preloads from their containing 32-bit SGPR word.
+ Register Raw = B.buildCopy(S32, LiveIn).getReg(0);
+ uint64_t OffsetDiff = Offset - alignDown(Offset, 4);
+ Register ShiftAmt = B.buildConstant(S32, OffsetDiff * 8).getReg(0);
+ Value = B.buildLShr(S32, Raw, ShiftAmt).getReg(0);
+ ValueTy = S32;
+ } else {
+ // A single preload entry may be a 32-bit SGPR or a wider SGPR tuple.
+ ValueTy = LiveInTy;
+ Value = B.buildCopy(ValueTy, LiveIn).getReg(0);
+ }
+ } else {
+ assert(!IsPackedSubDword && "packed sub-dword preload should use one SGPR");
+ // Reconstruct wider preloads from separate 32-bit SGPR entries.
+ SmallVector<Register, 4> Regs;
+ Regs.reserve(PreloadRegs.size());
+ for (MCRegister Reg : PreloadRegs) {
+ Register LiveIn = getPreloadedLiveIn(B, Reg, TRI).first;
+ Regs.push_back(B.buildCopy(S32, LiveIn).getReg(0));
+ }
+
+ ValueTy = LLT::scalar(PreloadRegs.size() * 32);
+ Value = B.buildMergeLikeInstr(ValueTy, Regs).getReg(0);
+ }
+
+ Register Adjusted = adjustPreloadedArgType(B, Value, ValueTy, DstTy);
+ B.buildCopy(DstReg, Adjusted);
+}
+
+// CCValAssign records an MVT, so round odd-sized split argument parts to the
+// simple memory type used for kernarg layout.
+static MVT getLocVTForSplitArg(const TargetLowering &TLI, const DataLayout &DL,
+ Type *Ty, LLVMContext &Ctx) {
+ EVT LocVT = TLI.getValueType(DL, Ty, true);
+
+ if (LocVT.isVector() && LocVT.getVectorNumElements() == 1)
+ LocVT = LocVT.getScalarType();
+
+ if (LocVT.isVector() && !LocVT.isPow2VectorType())
+ LocVT = LocVT.getPow2VectorType(Ctx);
+ else if (!LocVT.isSimple() && !LocVT.isVector())
+ LocVT = LocVT.getRoundIntegerType(Ctx);
+
+ assert(LocVT.isSimple());
+ return LocVT.getSimpleVT();
+}
+
+// Assign SGPRs for the contiguous sequence of kernel argument parts marked for
+// kernarg preload.
+static void allocatePreloadKernArgSGPRs(
+ CCState &CCInfo, ArrayRef<CallLowering::ArgInfo> SplitArgs,
+ ArrayRef<CCValAssign> ArgLocs, MachineFunction &MF,
+ const GCNSubtarget &Subtarget, const SIRegisterInfo &TRI,
+ SIMachineFunctionInfo &Info) {
+ assert(SplitArgs.size() == ArgLocs.size());
+
+ const Function &F = MF.getFunction();
+ const DataLayout &DL = F.getDataLayout();
+ unsigned LastExplicitArgOffset = Subtarget.getExplicitKernelArgOffset();
+ GCNUserSGPRUsageInfo &SGPRInfo = Info.getUserSGPRInfo();
+ bool InPreloadSequence = true;
+ unsigned InIdx = 0;
+ bool AlignedForImplicitArgs = false;
+ unsigned ImplicitArgOffset = 0;
+
+ for (const Argument &Arg : F.args()) {
+ // Preload assignment follows the original argument order. Each original
+ // argument may already have been split into one or more lowered parts.
+ const bool IsByRef = Arg.hasByRefAttr();
+ Type *ArgTy = IsByRef ? Arg.getParamByRefType() : Arg.getType();
+ if (DL.getTypeAllocSize(ArgTy) == 0)
+ continue;
+
+ // Hardware preloads a contiguous prefix of the kernarg segment. Once a
+ // non-preloaded argument is reached, no later argument can be preloaded.
+ if (!InPreloadSequence || !Arg.hasInRegAttr())
+ break;
+
+ unsigned ArgIdx = Arg.getArgNo();
+ if (InIdx < SplitArgs.size() && SplitArgs[InIdx].OrigArgIndex != ArgIdx)
+ break;
+
+ for (; InIdx < SplitArgs.size() && SplitArgs[InIdx].OrigArgIndex == ArgIdx;
+ ++InIdx) {
+ const CCValAssign &ArgLoc = ArgLocs[InIdx];
+ assert(ArgLoc.isMemLoc());
+ const Align KernelArgBaseAlign = Align(16);
+ unsigned ArgOffset = ArgLoc.getLocMemOffset();
+ Align Alignment = commonAlignment(KernelArgBaseAlign, ArgOffset);
+ unsigned NumAllocSGPRs =
+ alignTo(ArgLoc.getLocVT().getFixedSizeInBits(), 32) / 32;
+
+ if (Arg.hasAttribute("amdgpu-hidden-argument")) {
+ // Hidden arguments are laid out after the explicit kernargs, aligned to
+ // the ABI-required implicit argument block boundary.
+ if (!AlignedForImplicitArgs) {
+ ImplicitArgOffset =
+ alignTo(LastExplicitArgOffset,
+ Subtarget.getAlignmentForImplicitArgPtr()) -
+ LastExplicitArgOffset;
+ AlignedForImplicitArgs = true;
+ }
+ ArgOffset += ImplicitArgOffset;
+ }
+
+ if (ArgLoc.getLocVT().getStoreSize() < 4 && Alignment < 4) {
+ // Packed sub-dword values share the previous 32-bit SGPR. The extract
+ // happens later when materializing the argument value.
+ assert(InIdx >= 1 && "No previous SGPR");
+ Info.getArgInfo().PreloadKernArgs[InIdx].Regs.push_back(
+ Info.getArgInfo().PreloadKernArgs[InIdx - 1].Regs[0]);
+ continue;
+ }
+
+ // Padding between the last preloaded byte and this argument still
+ // consumes preload SGPR slots because the hardware preload sequence is
+ // contiguous.
+ unsigned Padding = ArgOffset - LastExplicitArgOffset;
+ unsigned PaddingSGPRs = alignTo(Padding, 4) / 4;
+ if (PaddingSGPRs + NumAllocSGPRs > SGPRInfo.getNumFreeUserSGPRs()) {
+ InPreloadSequence = false;
+ break;
+ }
+
+ const TargetRegisterClass *RC =
+ TRI.getSGPRClassForBitWidth(NumAllocSGPRs * 32);
+ SmallVectorImpl<MCRegister> *PreloadRegs =
+ Info.addPreloadedKernArg(TRI, RC, NumAllocSGPRs, InIdx, PaddingSGPRs);
+
+ // Record each assigned physical SGPR as a live-in and reserve it from the
+ // calling convention allocator.
+ if (PreloadRegs->size() > 1)
+ RC = &AMDGPU::SGPR_32RegClass;
+ for (MCRegister Reg : *PreloadRegs) {
+ assert(Reg);
+ MF.addLiveIn(Reg, RC);
+ CCInfo.AllocateReg(Reg);
+ }
+
+ LastExplicitArgOffset = NumAllocSGPRs * 4 + ArgOffset;
+ }
+ }
+}
} // anonymous namespace
AMDGPUCallLowering::AMDGPUCallLowering(const TargetLowering &TLI)
@@ -451,46 +644,59 @@ void AMDGPUCallLowering::lowerParameterPtr(Register DstReg, MachineIRBuilder &B,
B.buildPtrAdd(DstReg, KernArgSegmentVReg, OffsetReg);
}
-void AMDGPUCallLowering::lowerParameter(MachineIRBuilder &B, ArgInfo &OrigArg,
- uint64_t Offset,
- Align Alignment) const {
+bool AMDGPUCallLowering::lowerParameter(MachineIRBuilder &B, ArgInfo &Arg,
+ const CCValAssign &ArgLoc,
+ Align Alignment,
+ unsigned InputArgIndex) const {
MachineFunction &MF = B.getMF();
const Function &F = MF.getFunction();
const DataLayout &DL = F.getDataLayout();
+ const Argument *IRArg = dyn_cast_if_present<Argument>(Arg.OrigValue);
+ const bool IsHiddenArg =
+ IRArg && IRArg->hasAttribute("amdgpu-hidden-argument");
+ const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
+ const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>();
+ const SIRegisterInfo *TRI = Subtarget.getRegisterInfo();
const SITargetLowering &TLI = *getTLI<SITargetLowering>();
MachinePointerInfo PtrInfo = TLI.getKernargSegmentPtrInfo(MF);
LLT PtrTy = LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64);
+ LLT ArgTy = getLLTForType(*Arg.Ty, DL);
+ if (Arg.Flags[0].isPointer()) {
+ // Compensate for losing pointeriness in splitValueTypes.
+ LLT PtrTy = LLT::pointer(Arg.Flags[0].getPointerAddrSpace(),
+ ArgTy.getScalarSizeInBits());
+ ArgTy =
+ ArgTy.isVector() ? LLT::vector(ArgTy.getElementCount(), PtrTy) : PtrTy;
+ }
+
+ assert(Arg.Regs.size() == 1);
+
+ uint64_t Offset = ArgLoc.getLocMemOffset();
+ auto PreloadArg = Info->getArgInfo().PreloadKernArgs.find(InputArgIndex);
+ if (PreloadArg != Info->getArgInfo().PreloadKernArgs.end()) {
+ lowerPreloadedKernArg(B, Arg.Regs[0], ArgTy, Offset, Alignment,
+ PreloadArg->getSecond().Regs, *TRI);
+ return true;
+ }
- SmallVector<ArgInfo, 32> SplitArgs;
- SmallVector<TypeSize> FieldOffsets;
- splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv(), &FieldOffsets);
-
- unsigned Idx = 0;
- for (ArgInfo &SplitArg : SplitArgs) {
- Register PtrReg = B.getMRI()->createGenericVirtualRegister(PtrTy);
- lowerParameterPtr(PtrReg, B, Offset + FieldOffsets[Idx]);
-
- LLT ArgTy = getLLTForType(*SplitArg.Ty, DL);
- if (SplitArg.Flags[0].isPointer()) {
- // Compensate for losing pointeriness in splitValueTypes.
- LLT PtrTy = LLT::pointer(SplitArg.Flags[0].getPointerAddrSpace(),
- ArgTy.getScalarSizeInBits());
- ArgTy = ArgTy.isVector() ? LLT::vector(ArgTy.getElementCount(), PtrTy)
- : PtrTy;
- }
+ if (IsHiddenArg) {
+ F.getContext().diagnose(DiagnosticInfoUnsupported(
+ F, "hidden argument in kernel signature was not preloaded"));
+ return false;
+ }
- MachineMemOperand *MMO = MF.getMachineMemOperand(
- PtrInfo,
- MachineMemOperand::MOLoad | MachineMemOperand::MODereferenceable |
- MachineMemOperand::MOInvariant,
- ArgTy, commonAlignment(Alignment, FieldOffsets[Idx]));
+ Register PtrReg = B.getMRI()->createGenericVirtualRegister(PtrTy);
+ lowerParameterPtr(PtrReg, B, Offset);
- assert(SplitArg.Regs.size() == 1);
+ MachineMemOperand *MMO = MF.getMachineMemOperand(
+ PtrInfo,
+ MachineMemOperand::MOLoad | MachineMemOperand::MODereferenceable |
+ MachineMemOperand::MOInvariant,
+ ArgTy, Alignment);
- B.buildLoad(SplitArg.Regs[0], PtrReg, *MMO);
- ++Idx;
- }
+ B.buildLoad(Arg.Regs[0], PtrReg, *MMO);
+ return true;
}
// Allocate special inputs passed in user SGPRs.
@@ -568,19 +774,14 @@ bool AMDGPUCallLowering::lowerFormalArgumentsKernel(
allocateHSAUserSGPRs(CCInfo, B, MF, *TRI, *Info);
- unsigned i = 0;
- const Align KernArgBaseAlign(16);
+ SmallVector<ArgInfo, 16> SplitArgs;
+ SmallVector<Align, 16> SplitArgAlignments;
+
+ unsigned VRegIdx = 0;
const unsigned BaseOffset = Subtarget->getExplicitKernelArgOffset();
uint64_t ExplicitArgOffset = 0;
- // TODO: Align down to dword alignment and extract bits for extending loads.
- for (auto &Arg : F.args()) {
- // TODO: Add support for kernarg preload.
- if (Arg.hasAttribute("amdgpu-hidden-argument")) {
- LLVM_DEBUG(dbgs() << "Preloading hidden arguments is not supported\n");
- return false;
- }
-
+ for (const Argument &Arg : F.args()) {
const bool IsByRef = Arg.hasByRefAttr();
Type *ArgTy = IsByRef ? Arg.getParamByRefType() : Arg.getType();
unsigned AllocSize = DL.getTypeAllocSize(ArgTy);
@@ -592,33 +793,84 @@ bool AMDGPUCallLowering::lowerFormalArgumentsKernel(
uint64_t ArgOffset = alignTo(ExplicitArgOffset, ABIAlign) + BaseOffset;
ExplicitArgOffset = alignTo(ExplicitArgOffset, ABIAlign) + AllocSize;
+ Align ArgBaseAlign = commonAlignment(Align(16), ArgOffset);
+
+ ArgInfo OrigArg(VRegs[VRegIdx], Arg, Arg.getArgNo());
+ const unsigned OrigArgIdx = Arg.getArgNo() + AttributeList::FirstArgIndex;
+ setArgFlags(OrigArg, OrigArgIdx, DL, F);
+
+ SmallVector<ArgInfo, 32> ArgSplitArgs;
+ SmallVector<TypeSize> FieldOffsets;
+ splitToValueTypes(OrigArg, ArgSplitArgs, DL, F.getCallingConv(),
+ &FieldOffsets);
+
+ for (unsigned SplitIdx = 0, NumSplitArgs = ArgSplitArgs.size();
+ SplitIdx != NumSplitArgs; ++SplitIdx) {
+ unsigned InputArgIndex = SplitArgs.size();
+ ArgSplitArgs[SplitIdx].OrigValue = &Arg;
+ MVT LocVT = getLocVTForSplitArg(TLI, DL, ArgSplitArgs[SplitIdx].Ty,
+ F.getContext());
+ CCInfo.addLoc(CCValAssign::getCustomMem(
+ InputArgIndex, LocVT,
+ ArgOffset + FieldOffsets[SplitIdx].getFixedValue(), LocVT,
+ CCValAssign::Full));
+ SplitArgAlignments.push_back(
+ commonAlignment(ArgBaseAlign, FieldOffsets[SplitIdx]));
+ SplitArgs.push_back(ArgSplitArgs[SplitIdx]);
+ }
+
+ ++VRegIdx;
+ }
+
+ if (Subtarget->hasKernargPreload())
+ allocatePreloadKernArgSGPRs(CCInfo, SplitArgs, ArgLocs, MF, *Subtarget,
+ *TRI, *Info);
+
+ unsigned i = 0;
+ unsigned InputArgIndex = 0;
+
+ // TODO: Align down to dword alignment and extract bits for extending loads.
+ for (auto &Arg : F.args()) {
+ const bool IsByRef = Arg.hasByRefAttr();
+ Type *ArgTy = IsByRef ? Arg.getParamByRefType() : Arg.getType();
+ unsigned AllocSize = DL.getTypeAllocSize(ArgTy);
+ if (AllocSize == 0)
+ continue;
+
+ unsigned FirstInputArgIndex = InputArgIndex;
+ while (InputArgIndex < SplitArgs.size() &&
+ SplitArgs[InputArgIndex].OrigArgIndex == Arg.getArgNo())
+ ++InputArgIndex;
+ unsigned NumInputParts = InputArgIndex - FirstInputArgIndex;
if (Arg.use_empty()) {
++i;
continue;
}
- Align Alignment = commonAlignment(KernArgBaseAlign, ArgOffset);
-
if (IsByRef) {
unsigned ByRefAS = cast<PointerType>(Arg.getType())->getAddressSpace();
assert(VRegs[i].size() == 1 &&
"expected only one register for byval pointers");
if (ByRefAS == AMDGPUAS::CONSTANT_ADDRESS) {
- lowerParameterPtr(VRegs[i][0], B, ArgOffset);
+ lowerParameterPtr(VRegs[i][0], B,
+ ArgLocs[FirstInputArgIndex].getLocMemOffset());
} else {
const LLT ConstPtrTy = LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64);
Register PtrReg = MRI.createGenericVirtualRegister(ConstPtrTy);
- lowerParameterPtr(PtrReg, B, ArgOffset);
+ lowerParameterPtr(PtrReg, B,
+ ArgLocs[FirstInputArgIndex].getLocMemOffset());
B.buildAddrSpaceCast(VRegs[i][0], PtrReg);
}
} else {
- ArgInfo OrigArg(VRegs[i], Arg, i);
- const unsigned OrigArgIdx = i + AttributeList::FirstArgIndex;
- setArgFlags(OrigArg, OrigArgIdx, DL, F);
- lowerParameter(B, OrigArg, ArgOffset, Alignment);
+ for (unsigned Part = 0; Part != NumInputParts; ++Part) {
+ unsigned InputArgIndex = FirstInputArgIndex + Part;
+ if (!lowerParameter(B, SplitArgs[InputArgIndex], ArgLocs[InputArgIndex],
+ SplitArgAlignments[InputArgIndex], InputArgIndex))
+ return false;
+ }
}
++i;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h
index 239300c1469b9..b775db64554f7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h
@@ -26,8 +26,9 @@ class AMDGPUCallLowering final : public CallLowering {
void lowerParameterPtr(Register DstReg, MachineIRBuilder &B,
uint64_t Offset) const;
- void lowerParameter(MachineIRBuilder &B, ArgInfo &AI, uint64_t Offset,
- Align Alignment) const;
+ bool lowerParameter(MachineIRBuilder &B, ArgInfo &AI,
+ const CCValAssign &ArgLoc, Align Alignment,
+ unsigned InputArgIndex) const;
bool canLowerReturn(MachineFunction &MF, CallingConv::ID CallConv,
SmallVectorImpl<BaseArgInfo> &Outs,
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/preload-kernargs.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/preload-kernargs.ll
new file mode 100644
index 0000000000000..18ba715537465
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/preload-kernargs.ll
@@ -0,0 +1,100 @@
+; RUN: llc -verify-machineinstrs -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn--amdhsa -mcpu=gfx90a -stop-after=irtranslator -o - < %s | FileCheck -check-prefix=MIR %s
+; RUN: llc -verify-machineinstrs -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn--amdhsa -mcpu=gfx90a -o - < %s | FileCheck -check-prefix=ASM %s
+; RUN: llc -verify-machineinstrs -O1 -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -o - < %s | FileCheck -check-prefix=ISSUE %s
+
+define amdgpu_kernel void @explicit_i32_inreg(i32 inreg %x,
+ ptr addrspace(1) %out) #1 {
+; MIR-LABEL: name: explicit_i32_inreg
+; MIR: firstKernArgPreloadReg
+; MIR: numKernargPreloadSGPRs: 1
+; MIR: body:
+; MIR: [[X:%[0-9]+]]:_(s32) = COPY %{{[0-9]+}}
+; MIR-NOT: [[X]]:_(s32) = G_LOAD
+; ASM-LABEL: explicit_i32_inreg:
+; ASM: .amdhsa_user_sgpr_kernarg_preload_length 1
+ store i32 %x, ptr addrspace(1) %out, align 4
+ ret void
+}
+
+define amdgpu_kernel void @explicit_i64_inreg(i64 inreg %x,
+ ptr addrspace(1) %out) #1 {
+; MIR-LABEL: name: explicit_i64_inreg
+; MIR: firstKernArgPreloadReg
+; MIR: numKernargPreloadSGPRs: 2
+; MIR: body:
+; MIR: [[X:%[0-9]+]]:_(s64) = COPY %{{[0-9]+}}
+; MIR-NOT: [[X]]:_(s64) = G_LOAD
+; ASM-LABEL: explicit_i64_inreg:
+; ASM: .amdhsa_user_sgpr_kernarg_preload_length 2
+ store i64 %x, ptr addrspace(1) %out, align 8
+ ret void
+}
+
+define amdgpu_kernel void @explicit_ptr_inreg(ptr addrspace(1) inreg %p,
+ ptr addrspace(1) %out) #1 {
+; MIR-LABEL: name: explicit_ptr_inreg
+; MIR: firstKernArgPreloadReg
+; MIR: numKernargPreloadSGPRs: 2
+; MIR: body:
+; MIR: [[PINT:%[0-9]+]]:_(s64) = COPY %{{[0-9]+}}
+; MIR: [[P:%[0-9]+]]:_(p1) = G_INTTOPTR [[PINT]](s64)
+; MIR-NOT: [[P]]:_(p1) = G_LOAD
+; ASM-LABEL: explicit_ptr_inreg:
+; ASM: .amdhsa_user_sgpr_kernarg_preload_length 2
+ store ptr addrspace(1) %p, ptr addrspace(1) %out, align 8
+ ret void
+}
+
+define amdgpu_kernel void @packed_i16_inreg(i16 inreg %a, i16 inreg %b,
+ ptr addrspace(1) %out) #1 {
+; MIR-LABEL: name: packed_i16_inreg
+; MIR: firstKernArgPreloadReg
+; MIR: numKernargPreloadSGPRs: 1
+; MIR: body:
+; MIR: [[PACKED:%[0-9]+]]:_(s32) = COPY %{{[0-9]+}}
+; MIR: [[SHIFT:%[0-9]+]]:_(s32) = G_LSHR [[PACKED]], %{{[0-9]+}}(s32)
+; MIR: [[B:%[0-9]+]]:_(s16) = G_TRUNC [[SHIFT]](s32)
+; MIR-NOT: [[B]]:_(s16) = G_LOAD
+; ASM-LABEL: packed_i16_inreg:
+; ASM: .amdhsa_user_sgpr_kernarg_preload_length 1
+ store i16 %b, ptr addrspace(1) %out, align 2
+ ret void
+}
+
+define amdgpu_kernel void @preload_block_count_x(
+ ptr addrspace(1) inreg %out,
+ i32 inreg "amdgpu-hidden-argument" %_hidden_block_count_x) #0 {
+; MIR-LABEL: name: preload_block_count_x
+; MIR: firstKernArgPreloadReg
+; MIR: numKernargPreloadSGPRs: 3
+; MIR: body:
+; MIR: {{%[0-9]+}}:_(p1) = G_INTTOPTR {{%[0-9]+}}(s64)
+; MIR: {{%[0-9]+}}:_(s32) = COPY %{{[0-9]+}}
+; ASM-LABEL: preload_block_count_x:
+; ASM: .amdhsa_user_sgpr_kernarg_preload_length 3
+ store i32 %_hidden_block_count_x, ptr addrspace(1) %out, align 4
+ ret void
+}
+
+define amdgpu_kernel void @_Z15hipsmith_kernelv() local_unnamed_addr #0 {
+entry:
+; ISSUE-LABEL: _Z15hipsmith_kernelv:
+; ISSUE: .amdhsa_user_sgpr_kernarg_preload_length 1
+ %0 = tail call dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
+ %1 = load i32, ptr addrspace(4) %0, align 4
+ %.not.i.not = icmp eq i32 %1, 0
+ br i1 %.not.i.not, label %lor.end.i, label %common.ret1
+
+common.ret1:
+ ret void
+
+lor.end.i:
+ store ptr null, ptr inttoptr (i64 32 to ptr), align 32
+ br label %common.ret1
+}
+
+declare noundef align 4 ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() #2
+
+attributes #0 = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-no-wwm" }
+attributes #1 = { "target-cpu"="gfx90a" }
+attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
index 08dccdf5872d0..4db018812a8fe 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
@@ -84,24 +84,20 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_s(i32 inreg %src, ptr %out) #1 {
; GISEL-REAL16-LABEL: sat_pk4_i4_i8_f32_s:
; GISEL-REAL16: ; %bb.0:
; GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GISEL-REAL16-NEXT: s_clause 0x1
-; GISEL-REAL16-NEXT: s_load_b32 s2, s[4:5], 0x0 nv
; GISEL-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8 nv
+; GISEL-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, s8
; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
-; GISEL-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, s2
; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
; GISEL-REAL16-NEXT: s_endpgm
;
; GISEL-FAKE16-LABEL: sat_pk4_i4_i8_f32_s:
; GISEL-FAKE16: ; %bb.0:
; GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GISEL-FAKE16-NEXT: s_clause 0x1
-; GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x0 nv
; GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8 nv
+; GISEL-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v0, s8
; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GISEL-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v0, s2
; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1]
; GISEL-FAKE16-NEXT: s_endpgm
%cvt = call i16 @llvm.amdgcn.sat.pk4.i4.i8(i32 %src) #0
@@ -231,24 +227,20 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_s(i32 inreg %src, ptr %out) #1 {
; GISEL-REAL16-LABEL: sat_pk4_u4_u8_f32_s:
; GISEL-REAL16: ; %bb.0:
; GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GISEL-REAL16-NEXT: s_clause 0x1
-; GISEL-REAL16-NEXT: s_load_b32 s2, s[4:5], 0x0 nv
; GISEL-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8 nv
+; GISEL-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, s8
; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
-; GISEL-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, s2
; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
; GISEL-REAL16-NEXT: s_endpgm
;
; GISEL-FAKE16-LABEL: sat_pk4_u4_u8_f32_s:
; GISEL-FAKE16: ; %bb.0:
; GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GISEL-FAKE16-NEXT: s_clause 0x1
-; GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x0 nv
; GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8 nv
+; GISEL-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v0, s8
; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GISEL-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v0, s2
; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1]
; GISEL-FAKE16-NEXT: s_endpgm
%cvt = call i16 @llvm.amdgcn.sat.pk4.u4.u8(i32 %src) #0
>From 4e2d8d4159fb0271cd86dfc7484ce61ed3dec8d1 Mon Sep 17 00:00:00 2001
From: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
Date: Tue, 23 Jun 2026 22:33:05 +0530
Subject: [PATCH 2/6] AMDGPU: Add GlobalISel kernarg preload coverage
Add full-pipeline GlobalISel run lines to the existing kernarg preload tests and move MIR coverage into a dedicated IRTranslator test.
Also handle vector destinations when adjusting preloaded argument types.
Co-authored-by: GPT-5 Codex <noreply at openai.com>
Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
---
llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp | 7 +-
.../irtranslator-preload-kernargs.ll | 104 +++
.../AMDGPU/GlobalISel/preload-kernargs.ll | 100 ---
.../AMDGPU/preload-implicit-kernargs.ll | 436 +++++++++++++
llvm/test/CodeGen/AMDGPU/preload-kernargs.ll | 593 ++++++++++++++++++
5 files changed, 1139 insertions(+), 101 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-preload-kernargs.ll
delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/preload-kernargs.ll
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
index b3331d76df7f0..92e90a516e02c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
@@ -317,7 +317,9 @@ static Register adjustPreloadedArgType(MachineIRBuilder &B, Register Src,
if (SrcTy == DstTy)
return Src;
- LLT IntDstTy = DstTy.isPointer() ? LLT::scalar(DstTy.getSizeInBits()) : DstTy;
+ LLT IntDstTy = (DstTy.isPointer() || DstTy.isVector())
+ ? LLT::scalar(DstTy.getSizeInBits())
+ : DstTy;
if (SrcTy.getSizeInBits() != IntDstTy.getSizeInBits())
Src = B.buildAnyExtOrTrunc(IntDstTy, Src).getReg(0);
else if (SrcTy != IntDstTy)
@@ -326,6 +328,9 @@ static Register adjustPreloadedArgType(MachineIRBuilder &B, Register Src,
if (DstTy.isPointer())
return B.buildIntToPtr(DstTy, Src).getReg(0);
+ if (DstTy.isVector())
+ return B.buildBitcast(DstTy, Src).getReg(0);
+
return Src;
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-preload-kernargs.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-preload-kernargs.ll
new file mode 100644
index 0000000000000..70541447e49e9
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-preload-kernargs.ll
@@ -0,0 +1,104 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -stop-after=irtranslator -o - < %s | FileCheck -check-prefix=GFX90A %s
+
+define amdgpu_kernel void @preload_i32_inreg(i32 inreg %x, ptr addrspace(1) %out) #0 {
+ ; GFX90A-LABEL: name: preload_i32_inreg
+ ; GFX90A: bb.1 (%ir-block.0):
+ ; GFX90A-NEXT: liveins: $sgpr6, $sgpr4_sgpr5
+ ; GFX90A-NEXT: {{ $}}
+ ; GFX90A-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr6
+ ; GFX90A-NEXT: [[COPY1:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
+ ; GFX90A-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]]
+ ; GFX90A-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
+ ; GFX90A-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
+ ; GFX90A-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; GFX90A-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw nusw inbounds G_PTR_ADD [[INT]], [[C]](s64)
+ ; GFX90A-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from %ir.out.kernarg.offset, addrspace 4)
+ ; GFX90A-NEXT: G_STORE [[COPY3]](s32), [[LOAD]](p1) :: (store (s32) into %ir.out.load, addrspace 1)
+ ; GFX90A-NEXT: S_ENDPGM 0
+ store i32 %x, ptr addrspace(1) %out, align 4
+ ret void
+}
+
+define amdgpu_kernel void @preload_i64_inreg(i64 inreg %x, ptr addrspace(1) %out) #0 {
+ ; GFX90A-LABEL: name: preload_i64_inreg
+ ; GFX90A: bb.1 (%ir-block.0):
+ ; GFX90A-NEXT: liveins: $sgpr4_sgpr5, $sgpr6_sgpr7
+ ; GFX90A-NEXT: {{ $}}
+ ; GFX90A-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr6_sgpr7
+ ; GFX90A-NEXT: [[COPY1:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
+ ; GFX90A-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]]
+ ; GFX90A-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY2]](s64)
+ ; GFX90A-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
+ ; GFX90A-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; GFX90A-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw nusw inbounds G_PTR_ADD [[INT]], [[C]](s64)
+ ; GFX90A-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from %ir.out.kernarg.offset, addrspace 4)
+ ; GFX90A-NEXT: G_STORE [[COPY3]](s64), [[LOAD]](p1) :: (store (s64) into %ir.out.load, addrspace 1)
+ ; GFX90A-NEXT: S_ENDPGM 0
+ store i64 %x, ptr addrspace(1) %out, align 8
+ ret void
+}
+
+define amdgpu_kernel void @preload_ptr_inreg(ptr addrspace(1) inreg %p, ptr addrspace(1) %out) #0 {
+ ; GFX90A-LABEL: name: preload_ptr_inreg
+ ; GFX90A: bb.1 (%ir-block.0):
+ ; GFX90A-NEXT: liveins: $sgpr4_sgpr5, $sgpr6_sgpr7
+ ; GFX90A-NEXT: {{ $}}
+ ; GFX90A-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr6_sgpr7
+ ; GFX90A-NEXT: [[COPY1:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
+ ; GFX90A-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]]
+ ; GFX90A-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[COPY2]](s64)
+ ; GFX90A-NEXT: [[COPY3:%[0-9]+]]:_(p1) = COPY [[INTTOPTR]](p1)
+ ; GFX90A-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
+ ; GFX90A-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; GFX90A-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw nusw inbounds G_PTR_ADD [[INT]], [[C]](s64)
+ ; GFX90A-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from %ir.out.kernarg.offset, addrspace 4)
+ ; GFX90A-NEXT: G_STORE [[COPY3]](p1), [[LOAD]](p1) :: (store (p1) into %ir.out.load, addrspace 1)
+ ; GFX90A-NEXT: S_ENDPGM 0
+ store ptr addrspace(1) %p, ptr addrspace(1) %out, align 8
+ ret void
+}
+
+define amdgpu_kernel void @preload_packed_i16_inreg(i16 inreg %a, i16 inreg %b, ptr addrspace(1) %out) #0 {
+ ; GFX90A-LABEL: name: preload_packed_i16_inreg
+ ; GFX90A: bb.1 (%ir-block.0):
+ ; GFX90A-NEXT: liveins: $sgpr6, $sgpr4_sgpr5
+ ; GFX90A-NEXT: {{ $}}
+ ; GFX90A-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr6
+ ; GFX90A-NEXT: [[COPY1:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
+ ; GFX90A-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]]
+ ; GFX90A-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; GFX90A-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C]](s32)
+ ; GFX90A-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
+ ; GFX90A-NEXT: [[COPY3:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
+ ; GFX90A-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
+ ; GFX90A-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; GFX90A-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw nusw inbounds G_PTR_ADD [[INT]], [[C1]](s64)
+ ; GFX90A-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from %ir.out.kernarg.offset, addrspace 4)
+ ; GFX90A-NEXT: G_STORE [[COPY3]](s16), [[LOAD]](p1) :: (store (s16) into %ir.out.load, addrspace 1)
+ ; GFX90A-NEXT: S_ENDPGM 0
+ store i16 %b, ptr addrspace(1) %out, align 2
+ ret void
+}
+
+define amdgpu_kernel void @preload_hidden_block_count_x(ptr addrspace(1) inreg %out, i32 inreg "amdgpu-hidden-argument" %_hidden_block_count_x) #0 {
+ ; GFX90A-LABEL: name: preload_hidden_block_count_x
+ ; GFX90A: bb.1 (%ir-block.0):
+ ; GFX90A-NEXT: liveins: $sgpr8, $sgpr4_sgpr5, $sgpr6_sgpr7
+ ; GFX90A-NEXT: {{ $}}
+ ; GFX90A-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr8
+ ; GFX90A-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr6_sgpr7
+ ; GFX90A-NEXT: [[COPY2:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
+ ; GFX90A-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]]
+ ; GFX90A-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[COPY3]](s64)
+ ; GFX90A-NEXT: [[COPY4:%[0-9]+]]:_(p1) = COPY [[INTTOPTR]](p1)
+ ; GFX90A-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]]
+ ; GFX90A-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
+ ; GFX90A-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
+ ; GFX90A-NEXT: G_STORE [[COPY6]](s32), [[COPY4]](p1) :: (store (s32) into %ir.out, addrspace 1)
+ ; GFX90A-NEXT: S_ENDPGM 0
+ store i32 %_hidden_block_count_x, ptr addrspace(1) %out, align 4
+ ret void
+}
+
+attributes #0 = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-no-wwm" "target-cpu"="gfx90a" }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/preload-kernargs.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/preload-kernargs.ll
deleted file mode 100644
index 18ba715537465..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/preload-kernargs.ll
+++ /dev/null
@@ -1,100 +0,0 @@
-; RUN: llc -verify-machineinstrs -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn--amdhsa -mcpu=gfx90a -stop-after=irtranslator -o - < %s | FileCheck -check-prefix=MIR %s
-; RUN: llc -verify-machineinstrs -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn--amdhsa -mcpu=gfx90a -o - < %s | FileCheck -check-prefix=ASM %s
-; RUN: llc -verify-machineinstrs -O1 -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -o - < %s | FileCheck -check-prefix=ISSUE %s
-
-define amdgpu_kernel void @explicit_i32_inreg(i32 inreg %x,
- ptr addrspace(1) %out) #1 {
-; MIR-LABEL: name: explicit_i32_inreg
-; MIR: firstKernArgPreloadReg
-; MIR: numKernargPreloadSGPRs: 1
-; MIR: body:
-; MIR: [[X:%[0-9]+]]:_(s32) = COPY %{{[0-9]+}}
-; MIR-NOT: [[X]]:_(s32) = G_LOAD
-; ASM-LABEL: explicit_i32_inreg:
-; ASM: .amdhsa_user_sgpr_kernarg_preload_length 1
- store i32 %x, ptr addrspace(1) %out, align 4
- ret void
-}
-
-define amdgpu_kernel void @explicit_i64_inreg(i64 inreg %x,
- ptr addrspace(1) %out) #1 {
-; MIR-LABEL: name: explicit_i64_inreg
-; MIR: firstKernArgPreloadReg
-; MIR: numKernargPreloadSGPRs: 2
-; MIR: body:
-; MIR: [[X:%[0-9]+]]:_(s64) = COPY %{{[0-9]+}}
-; MIR-NOT: [[X]]:_(s64) = G_LOAD
-; ASM-LABEL: explicit_i64_inreg:
-; ASM: .amdhsa_user_sgpr_kernarg_preload_length 2
- store i64 %x, ptr addrspace(1) %out, align 8
- ret void
-}
-
-define amdgpu_kernel void @explicit_ptr_inreg(ptr addrspace(1) inreg %p,
- ptr addrspace(1) %out) #1 {
-; MIR-LABEL: name: explicit_ptr_inreg
-; MIR: firstKernArgPreloadReg
-; MIR: numKernargPreloadSGPRs: 2
-; MIR: body:
-; MIR: [[PINT:%[0-9]+]]:_(s64) = COPY %{{[0-9]+}}
-; MIR: [[P:%[0-9]+]]:_(p1) = G_INTTOPTR [[PINT]](s64)
-; MIR-NOT: [[P]]:_(p1) = G_LOAD
-; ASM-LABEL: explicit_ptr_inreg:
-; ASM: .amdhsa_user_sgpr_kernarg_preload_length 2
- store ptr addrspace(1) %p, ptr addrspace(1) %out, align 8
- ret void
-}
-
-define amdgpu_kernel void @packed_i16_inreg(i16 inreg %a, i16 inreg %b,
- ptr addrspace(1) %out) #1 {
-; MIR-LABEL: name: packed_i16_inreg
-; MIR: firstKernArgPreloadReg
-; MIR: numKernargPreloadSGPRs: 1
-; MIR: body:
-; MIR: [[PACKED:%[0-9]+]]:_(s32) = COPY %{{[0-9]+}}
-; MIR: [[SHIFT:%[0-9]+]]:_(s32) = G_LSHR [[PACKED]], %{{[0-9]+}}(s32)
-; MIR: [[B:%[0-9]+]]:_(s16) = G_TRUNC [[SHIFT]](s32)
-; MIR-NOT: [[B]]:_(s16) = G_LOAD
-; ASM-LABEL: packed_i16_inreg:
-; ASM: .amdhsa_user_sgpr_kernarg_preload_length 1
- store i16 %b, ptr addrspace(1) %out, align 2
- ret void
-}
-
-define amdgpu_kernel void @preload_block_count_x(
- ptr addrspace(1) inreg %out,
- i32 inreg "amdgpu-hidden-argument" %_hidden_block_count_x) #0 {
-; MIR-LABEL: name: preload_block_count_x
-; MIR: firstKernArgPreloadReg
-; MIR: numKernargPreloadSGPRs: 3
-; MIR: body:
-; MIR: {{%[0-9]+}}:_(p1) = G_INTTOPTR {{%[0-9]+}}(s64)
-; MIR: {{%[0-9]+}}:_(s32) = COPY %{{[0-9]+}}
-; ASM-LABEL: preload_block_count_x:
-; ASM: .amdhsa_user_sgpr_kernarg_preload_length 3
- store i32 %_hidden_block_count_x, ptr addrspace(1) %out, align 4
- ret void
-}
-
-define amdgpu_kernel void @_Z15hipsmith_kernelv() local_unnamed_addr #0 {
-entry:
-; ISSUE-LABEL: _Z15hipsmith_kernelv:
-; ISSUE: .amdhsa_user_sgpr_kernarg_preload_length 1
- %0 = tail call dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
- %1 = load i32, ptr addrspace(4) %0, align 4
- %.not.i.not = icmp eq i32 %1, 0
- br i1 %.not.i.not, label %lor.end.i, label %common.ret1
-
-common.ret1:
- ret void
-
-lor.end.i:
- store ptr null, ptr inttoptr (i64 32 to ptr), align 32
- br label %common.ret1
-}
-
-declare noundef align 4 ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() #2
-
-attributes #0 = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-no-wwm" }
-attributes #1 = { "target-cpu"="gfx90a" }
-attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
diff --git a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
index 344d1f5d0b854..bbadf150e1e14 100644
--- a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
+++ b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
@@ -1,6 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX942 %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX90a %s
+; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefixes=GISEL-GFX90A %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16 %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16 %s
@@ -33,6 +34,20 @@ define amdgpu_kernel void @preload_block_count_x(ptr addrspace(1) inreg %out) #0
; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: preload_block_count_x:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_load_dword s10, s[4:5], 0x8
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB0_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB0_0:
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: preload_block_count_x:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -75,6 +90,20 @@ define amdgpu_kernel void @preload_unused_arg_block_count_x(ptr addrspace(1) inr
; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: preload_unused_arg_block_count_x:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_load_dword s12, s[4:5], 0x10
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB1_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB1_0:
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s12
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: preload_unused_arg_block_count_x:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -118,6 +147,21 @@ define amdgpu_kernel void @no_free_sgprs_block_count_x(ptr addrspace(1) inreg %o
; GFX90a-NEXT: global_store_dword v0, v1, s[14:15]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: no_free_sgprs_block_count_x:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[14:15], s[8:9], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB2_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB2_0:
+; GISEL-GFX90A-NEXT: s_load_dword s0, s[8:9], 0x28
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[14:15]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: no_free_sgprs_block_count_x:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -151,6 +195,16 @@ define amdgpu_kernel void @no_inreg_block_count_x(ptr addrspace(1) %out) #0 {
; GFX90a-NEXT: global_store_dword v0, v1, s[0:1]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: no_inreg_block_count_x:
+; GISEL-GFX90A: ; %bb.0:
+; GISEL-GFX90A-NEXT: s_load_dword s2, s[4:5], 0x8
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s2
+; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[0:1]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: no_inreg_block_count_x:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -189,6 +243,16 @@ define amdgpu_kernel void @mixed_inreg_block_count_x(ptr addrspace(1) %out, i32
; GFX90a-NEXT: global_store_dword v0, v1, s[0:1]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: mixed_inreg_block_count_x:
+; GISEL-GFX90A: ; %bb.0:
+; GISEL-GFX90A-NEXT: s_load_dword s2, s[4:5], 0x10
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s2
+; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[0:1]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: mixed_inreg_block_count_x:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -236,6 +300,21 @@ define amdgpu_kernel void @incorrect_type_i64_block_count_x(ptr addrspace(1) inr
; GFX90a-NEXT: global_store_dwordx2 v0, v[2:3], s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: incorrect_type_i64_block_count_x:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB5_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB5_0:
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, 0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
+; GISEL-GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: incorrect_type_i64_block_count_x:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -282,6 +361,21 @@ define amdgpu_kernel void @incorrect_type_i16_block_count_x(ptr addrspace(1) inr
; GFX90a-NEXT: global_store_short v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: incorrect_type_i16_block_count_x:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB6_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB6_0:
+; GISEL-GFX90A-NEXT: s_load_dword s0, s[4:5], 0x8
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-FAKE16-LABEL: incorrect_type_i16_block_count_x:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -333,6 +427,19 @@ define amdgpu_kernel void @preload_block_count_y(ptr addrspace(1) inreg %out) #0
; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: preload_block_count_y:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB7_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB7_0:
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s11
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: preload_block_count_y:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -377,6 +484,21 @@ define amdgpu_kernel void @random_incorrect_offset(ptr addrspace(1) inreg %out)
; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: random_incorrect_offset:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB8_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB8_0:
+; GISEL-GFX90A-NEXT: s_load_dword s0, s[4:5], 0xa
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: random_incorrect_offset:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -422,6 +544,20 @@ define amdgpu_kernel void @preload_block_count_z(ptr addrspace(1) inreg %out) #0
; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: preload_block_count_z:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_load_dword s12, s[4:5], 0x10
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB9_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB9_0:
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s12
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: preload_block_count_z:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -469,6 +605,22 @@ define amdgpu_kernel void @preload_block_count_x_imparg_align_ptr_i8(ptr addrspa
; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: preload_block_count_x_imparg_align_ptr_i8:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_load_dword s12, s[4:5], 0x10
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB10_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB10_0:
+; GISEL-GFX90A-NEXT: s_and_b32 s0, s10, 0xff
+; GISEL-GFX90A-NEXT: s_add_i32 s0, s12, s0
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: preload_block_count_x_imparg_align_ptr_i8:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -520,6 +672,25 @@ define amdgpu_kernel void @preload_block_count_xyz(ptr addrspace(1) inreg %out)
; GFX90a-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: preload_block_count_xyz:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_load_dword s12, s[4:5], 0x10
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB11_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB11_0:
+; GISEL-GFX90A-NEXT: s_mov_b32 s0, s10
+; GISEL-GFX90A-NEXT: s_mov_b32 s2, s12
+; GISEL-GFX90A-NEXT: s_mov_b32 s1, s11
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, s1
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, s2
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GISEL-GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: preload_block_count_xyz:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -572,6 +743,21 @@ define amdgpu_kernel void @preload_workgroup_size_x(ptr addrspace(1) inreg %out)
; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: preload_workgroup_size_x:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB12_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB12_0:
+; GISEL-GFX90A-NEXT: s_and_b32 s0, s13, 0xffff
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: preload_workgroup_size_x:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -619,6 +805,21 @@ define amdgpu_kernel void @preload_workgroup_size_y(ptr addrspace(1) inreg %out)
; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: preload_workgroup_size_y:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB13_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB13_0:
+; GISEL-GFX90A-NEXT: s_lshr_b32 s0, s13, 16
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: preload_workgroup_size_y:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -668,6 +869,22 @@ define amdgpu_kernel void @preload_workgroup_size_z(ptr addrspace(1) inreg %out)
; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: preload_workgroup_size_z:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
+; GISEL-GFX90A-NEXT: s_load_dword s14, s[4:5], 0x18
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB14_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB14_0:
+; GISEL-GFX90A-NEXT: s_and_b32 s0, s14, 0xffff
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: preload_workgroup_size_z:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -725,6 +942,26 @@ define amdgpu_kernel void @preload_workgroup_size_xyz(ptr addrspace(1) inreg %ou
; GFX90a-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: preload_workgroup_size_xyz:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
+; GISEL-GFX90A-NEXT: s_load_dword s14, s[4:5], 0x18
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB15_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB15_0:
+; GISEL-GFX90A-NEXT: s_and_b32 s0, s13, 0xffff
+; GISEL-GFX90A-NEXT: s_lshr_b32 s1, s13, 16
+; GISEL-GFX90A-NEXT: s_and_b32 s2, s14, 0xffff
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, s1
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, s2
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GISEL-GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: preload_workgroup_size_xyz:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -785,6 +1022,22 @@ define amdgpu_kernel void @preload_remainder_x(ptr addrspace(1) inreg %out) #0 {
; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: preload_remainder_x:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
+; GISEL-GFX90A-NEXT: s_load_dword s14, s[4:5], 0x18
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB16_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB16_0:
+; GISEL-GFX90A-NEXT: s_lshr_b32 s0, s14, 16
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: preload_remainder_x:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -832,6 +1085,20 @@ define amdgpu_kernel void @preloadremainder_y(ptr addrspace(1) inreg %out) #0 {
; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: preloadremainder_y:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB17_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB17_0:
+; GISEL-GFX90A-NEXT: s_and_b32 s0, s15, 0xffff
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: preloadremainder_y:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -879,6 +1146,20 @@ define amdgpu_kernel void @preloadremainder_z(ptr addrspace(1) inreg %out) #0 {
; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: preloadremainder_z:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB18_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB18_0:
+; GISEL-GFX90A-NEXT: s_lshr_b32 s0, s15, 16
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: preloadremainder_z:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -934,6 +1215,24 @@ define amdgpu_kernel void @preloadremainder_xyz(ptr addrspace(1) inreg %out) #0
; GFX90a-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: preloadremainder_xyz:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB19_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB19_0:
+; GISEL-GFX90A-NEXT: s_lshr_b32 s0, s14, 16
+; GISEL-GFX90A-NEXT: s_lshr_b32 s2, s15, 16
+; GISEL-GFX90A-NEXT: s_and_b32 s1, s15, 0xffff
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, s1
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, s2
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GISEL-GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: preloadremainder_xyz:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -992,6 +1291,22 @@ define amdgpu_kernel void @no_free_sgprs_preloadremainder_z(ptr addrspace(1) inr
; GFX90a-NEXT: global_store_dword v0, v1, s[14:15]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: no_free_sgprs_preloadremainder_z:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[14:15], s[8:9], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB20_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB20_0:
+; GISEL-GFX90A-NEXT: s_load_dword s0, s[8:9], 0x1c
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_lshr_b32 s0, s0, 16
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[14:15]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: no_free_sgprs_preloadremainder_z:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -1041,6 +1356,21 @@ define amdgpu_kernel void @preload_block_max_user_sgprs(ptr addrspace(1) inreg %
; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: preload_block_max_user_sgprs:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB21_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB21_0:
+; GISEL-GFX90A-NEXT: s_load_dword s0, s[4:5], 0x28
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: preload_block_max_user_sgprs:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -1090,6 +1420,24 @@ define amdgpu_kernel void @preload_block_count_z_workgroup_size_z_remainder_z(pt
; GFX90a-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: preload_block_count_z_workgroup_size_z_remainder_z:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB22_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB22_0:
+; GISEL-GFX90A-NEXT: s_mov_b32 s0, s14
+; GISEL-GFX90A-NEXT: s_lshr_b32 s14, s15, 16
+; GISEL-GFX90A-NEXT: s_and_b32 s13, s0, 0xffff
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s12
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, s13
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, s14
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GISEL-GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: preload_block_count_z_workgroup_size_z_remainder_z:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -1115,4 +1463,92 @@ define amdgpu_kernel void @preload_block_count_z_workgroup_size_z_remainder_z(pt
ret void
}
+define amdgpu_kernel void @preload_block_count_x_no_explicit_args() local_unnamed_addr #0 {
+; GFX942-LABEL: preload_block_count_x_no_explicit_args:
+; GFX942: ; %bb.3:
+; GFX942-NEXT: s_load_dword s2, s[0:1], 0x0
+; GFX942-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-NEXT: s_branch .LBB23_0
+; GFX942-NEXT: .p2align 8
+; GFX942-NEXT: ; %bb.4:
+; GFX942-NEXT: .LBB23_0: ; %entry
+; GFX942-NEXT: s_cmp_lg_u32 s2, 0
+; GFX942-NEXT: s_cbranch_scc0 .LBB23_2
+; GFX942-NEXT: ; %bb.1: ; %ret
+; GFX942-NEXT: s_endpgm
+; GFX942-NEXT: .LBB23_2: ; %store
+; GFX942-NEXT: v_mov_b64_e32 v[0:1], 0
+; GFX942-NEXT: v_mov_b64_e32 v[2:3], 32
+; GFX942-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; GFX942-NEXT: s_endpgm
+;
+; GFX90a-LABEL: preload_block_count_x_no_explicit_args:
+; GFX90a: ; %bb.3:
+; GFX90a-NEXT: s_load_dword s8, s[4:5], 0x0
+; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-NEXT: s_branch .LBB23_0
+; GFX90a-NEXT: .p2align 8
+; GFX90a-NEXT: ; %bb.4:
+; GFX90a-NEXT: .LBB23_0: ; %entry
+; GFX90a-NEXT: s_add_u32 flat_scratch_lo, s6, s12
+; GFX90a-NEXT: s_addc_u32 flat_scratch_hi, s7, 0
+; GFX90a-NEXT: s_cmp_lg_u32 s8, 0
+; GFX90a-NEXT: s_cbranch_scc0 .LBB23_2
+; GFX90a-NEXT: ; %bb.1: ; %ret
+; GFX90a-NEXT: s_endpgm
+; GFX90a-NEXT: .LBB23_2: ; %store
+; GFX90a-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-NEXT: v_mov_b32_e32 v1, v0
+; GFX90a-NEXT: v_mov_b32_e32 v2, 32
+; GFX90a-NEXT: v_mov_b32_e32 v3, 0
+; GFX90a-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; GFX90a-NEXT: s_endpgm
+;
+; GISEL-GFX90A-LABEL: preload_block_count_x_no_explicit_args:
+; GISEL-GFX90A: ; %bb.3:
+; GISEL-GFX90A-NEXT: s_load_dword s8, s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB23_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.4:
+; GISEL-GFX90A-NEXT: .LBB23_0: ; %entry
+; GISEL-GFX90A-NEXT: s_add_u32 flat_scratch_lo, s6, s12
+; GISEL-GFX90A-NEXT: s_addc_u32 flat_scratch_hi, s7, 0
+; GISEL-GFX90A-NEXT: s_cmp_lg_u32 s8, 0
+; GISEL-GFX90A-NEXT: s_cbranch_scc0 .LBB23_2
+; GISEL-GFX90A-NEXT: ; %bb.1: ; %ret
+; GISEL-GFX90A-NEXT: s_endpgm
+; GISEL-GFX90A-NEXT: .LBB23_2: ; %store
+; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[0:1], 0, 0
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, 32
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GISEL-GFX90A-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
+; GFX1250-LABEL: preload_block_count_x_no_explicit_args:
+; GFX1250: ; %bb.0: ; %entry
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1250-NEXT: s_cbranch_scc0 .LBB23_2
+; GFX1250-NEXT: ; %bb.1: ; %ret
+; GFX1250-NEXT: s_endpgm
+; GFX1250-NEXT: .LBB23_2: ; %store
+; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 0
+; GFX1250-NEXT: v_mov_b64_e32 v[2:3], 32
+; GFX1250-NEXT: flat_store_b64 v[2:3], v[0:1]
+; GFX1250-NEXT: s_endpgm
+entry:
+ %imp_arg_ptr = tail call dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
+ %load = load i32, ptr addrspace(4) %imp_arg_ptr, align 4
+ %is_zero = icmp eq i32 %load, 0
+ br i1 %is_zero, label %store, label %ret
+
+store:
+ store ptr null, ptr inttoptr (i64 32 to ptr), align 32
+ br label %ret
+
+ret:
+ ret void
+}
+
attributes #0 = { "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }
diff --git a/llvm/test/CodeGen/AMDGPU/preload-kernargs.ll b/llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
index 70d08930e3b9c..7833f163ead4d 100644
--- a/llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
+++ b/llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
@@ -1,6 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX942 %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX90a %s
+; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefixes=GISEL-GFX90A %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250 %s
define amdgpu_kernel void @ptr1_i8(ptr addrspace(1) inreg %out, i8 inreg %arg0) #0 {
@@ -34,6 +35,21 @@ define amdgpu_kernel void @ptr1_i8(ptr addrspace(1) inreg %out, i8 inreg %arg0)
; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: ptr1_i8:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_load_dword s10, s[4:5], 0x8
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB0_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB0_0:
+; GISEL-GFX90A-NEXT: s_and_b32 s0, s10, 0xff
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: ptr1_i8:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -78,6 +94,21 @@ define amdgpu_kernel void @ptr1_i8_zext_arg(ptr addrspace(1) inreg %out, i8 zero
; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: ptr1_i8_zext_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_load_dword s10, s[4:5], 0x8
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB1_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB1_0:
+; GISEL-GFX90A-NEXT: s_and_b32 s0, s10, 0xff
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: ptr1_i8_zext_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -122,6 +153,21 @@ define amdgpu_kernel void @ptr1_i16_preload_arg(ptr addrspace(1) inreg %out, i16
; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: ptr1_i16_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_load_dword s10, s[4:5], 0x8
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB2_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB2_0:
+; GISEL-GFX90A-NEXT: s_and_b32 s0, s10, 0xffff
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: ptr1_i16_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -164,6 +210,20 @@ define amdgpu_kernel void @ptr1_i32_preload_arg(ptr addrspace(1) inreg %out, i32
; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: ptr1_i32_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_load_dword s10, s[4:5], 0x8
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB3_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB3_0:
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: ptr1_i32_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -207,6 +267,21 @@ define amdgpu_kernel void @i32_ptr1_i32_preload_arg(i32 inreg %arg0, ptr addrspa
; GFX90a-NEXT: global_store_dword v0, v1, s[10:11]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: i32_ptr1_i32_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_load_dword s12, s[4:5], 0x10
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB4_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB4_0:
+; GISEL-GFX90A-NEXT: s_add_i32 s0, s8, s12
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[10:11]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: i32_ptr1_i32_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -255,6 +330,23 @@ define amdgpu_kernel void @ptr1_i16_i16_preload_arg(ptr addrspace(1) inreg %out,
; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: ptr1_i16_i16_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_load_dword s10, s[4:5], 0x8
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB5_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB5_0:
+; GISEL-GFX90A-NEXT: s_lshr_b32 s0, s10, 16
+; GISEL-GFX90A-NEXT: s_and_b32 s1, s10, 0xffff
+; GISEL-GFX90A-NEXT: s_add_i32 s0, s1, s0
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: ptr1_i16_i16_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -301,6 +393,20 @@ define amdgpu_kernel void @ptr1_v2i8_preload_arg(ptr addrspace(1) inreg %out, <2
; GFX90a-NEXT: global_store_short v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: ptr1_v2i8_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_load_dword s10, s[4:5], 0x8
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB6_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB6_0:
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: ptr1_v2i8_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -351,6 +457,25 @@ define amdgpu_kernel void @byref_preload_arg(ptr addrspace(1) inreg %out, ptr ad
; GFX90a-NEXT: s_waitcnt vmcnt(0)
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: byref_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB7_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB7_0:
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x100
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, 0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, s0
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, s1
+; GISEL-GFX90A-NEXT: global_store_dword v0, v1, s[8:9]
+; GISEL-GFX90A-NEXT: s_waitcnt vmcnt(0)
+; GISEL-GFX90A-NEXT: global_store_dword v0, v2, s[8:9]
+; GISEL-GFX90A-NEXT: s_waitcnt vmcnt(0)
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: byref_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -411,6 +536,25 @@ define amdgpu_kernel void @byref_staggered_preload_arg(ptr addrspace(1) inreg %o
; GFX90a-NEXT: s_waitcnt vmcnt(0)
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: byref_staggered_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB8_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB8_0:
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x100
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, 0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, s0
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, s1
+; GISEL-GFX90A-NEXT: global_store_dword v0, v1, s[8:9]
+; GISEL-GFX90A-NEXT: s_waitcnt vmcnt(0)
+; GISEL-GFX90A-NEXT: global_store_dword v0, v2, s[8:9]
+; GISEL-GFX90A-NEXT: s_waitcnt vmcnt(0)
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: byref_staggered_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -480,6 +624,25 @@ define amdgpu_kernel void @v8i32_arg(ptr addrspace(1) nocapture inreg %out, <8 x
; GFX90a-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: v8i32_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB9_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB9_0:
+; GISEL-GFX90A-NEXT: s_load_dwordx8 s[12:19], s[4:5], 0x20
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[12:13], s[12:13] op_sel:[0,1]
+; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[2:3], s[14:15], s[14:15] op_sel:[0,1]
+; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[4:5], s[16:17], s[16:17] op_sel:[0,1]
+; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[6:7], s[18:19], s[18:19] op_sel:[0,1]
+; GISEL-GFX90A-NEXT: global_store_dwordx4 v8, v[0:3], s[8:9]
+; GISEL-GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[8:9] offset:16
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: v8i32_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -528,6 +691,24 @@ define amdgpu_kernel void @v3i16_preload_arg(ptr addrspace(1) nocapture inreg %o
; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: v3i16_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB10_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB10_0:
+; GISEL-GFX90A-NEXT: s_lshr_b32 s0, s10, 16
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9] offset:2
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s11
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9] offset:4
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: v3i16_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -574,6 +755,21 @@ define amdgpu_kernel void @v3i32_preload_arg(ptr addrspace(1) nocapture inreg %o
; GFX90a-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: v3i32_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB11_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB11_0:
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s12
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, s13
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, s14
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GISEL-GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: v3i32_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -618,6 +814,21 @@ define amdgpu_kernel void @v3f32_preload_arg(ptr addrspace(1) nocapture inreg %o
; GFX90a-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: v3f32_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB12_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB12_0:
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s12
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, s13
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, s14
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GISEL-GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: v3f32_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -675,6 +886,31 @@ define amdgpu_kernel void @v5i8_preload_arg(ptr addrspace(1) nocapture inreg %ou
; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: v5i8_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB13_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB13_0:
+; GISEL-GFX90A-NEXT: s_and_b32 s1, 0xffff, s10
+; GISEL-GFX90A-NEXT: s_lshr_b32 s1, s1, 8
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: s_lshr_b32 s0, s10, 16
+; GISEL-GFX90A-NEXT: global_store_byte v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s1
+; GISEL-GFX90A-NEXT: s_lshr_b32 s2, s10, 24
+; GISEL-GFX90A-NEXT: global_store_byte v1, v0, s[8:9] offset:1
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: global_store_byte v1, v0, s[8:9] offset:2
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s2
+; GISEL-GFX90A-NEXT: global_store_byte v1, v0, s[8:9] offset:3
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s11
+; GISEL-GFX90A-NEXT: global_store_byte v1, v0, s[8:9] offset:4
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: v5i8_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -747,6 +983,28 @@ define amdgpu_kernel void @v5f64_arg(ptr addrspace(1) nocapture inreg %out, <5 x
; GFX90a-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: v5f64_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB14_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB14_0:
+; GISEL-GFX90A-NEXT: s_load_dwordx8 s[12:19], s[4:5], 0x40
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x60
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v8, 0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[12:13], s[12:13] op_sel:[0,1]
+; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[2:3], s[14:15], s[14:15] op_sel:[0,1]
+; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[4:5], s[16:17], s[16:17] op_sel:[0,1]
+; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[6:7], s[18:19], s[18:19] op_sel:[0,1]
+; GISEL-GFX90A-NEXT: global_store_dwordx4 v8, v[0:3], s[8:9]
+; GISEL-GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[8:9] offset:16
+; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
+; GISEL-GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[8:9] offset:32
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: v5f64_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -827,6 +1085,19 @@ define amdgpu_kernel void @v8i8_preload_arg(ptr addrspace(1) inreg %out, <8 x i8
; GFX90a-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: v8i8_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB15_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB15_0:
+; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[10:11], s[10:11] op_sel:[0,1]
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, 0
+; GISEL-GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: v8i8_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -873,6 +1144,19 @@ define amdgpu_kernel void @i64_kernel_preload_arg(ptr addrspace(1) inreg %out, i
; GFX90a-NEXT: global_store_dwordx2 v0, v[2:3], s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: i64_kernel_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB16_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB16_0:
+; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[10:11], s[10:11] op_sel:[0,1]
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, 0
+; GISEL-GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: i64_kernel_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -912,6 +1196,19 @@ define amdgpu_kernel void @f64_kernel_preload_arg(ptr addrspace(1) inreg %out, d
; GFX90a-NEXT: global_store_dwordx2 v0, v[2:3], s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: f64_kernel_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB17_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB17_0:
+; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[10:11], s[10:11] op_sel:[0,1]
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, 0
+; GISEL-GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: f64_kernel_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -952,6 +1249,20 @@ define amdgpu_kernel void @half_kernel_preload_arg(ptr addrspace(1) inreg %out,
; GFX90a-NEXT: global_store_short v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: half_kernel_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_load_dword s10, s[4:5], 0x8
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB18_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB18_0:
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: half_kernel_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -991,6 +1302,20 @@ define amdgpu_kernel void @bfloat_kernel_preload_arg(ptr addrspace(1) inreg %out
; GFX90a-NEXT: global_store_short v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: bfloat_kernel_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_load_dword s10, s[4:5], 0x8
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB19_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB19_0:
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: bfloat_kernel_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -1030,6 +1355,20 @@ define amdgpu_kernel void @v2bfloat_kernel_preload_arg(ptr addrspace(1) inreg %o
; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: v2bfloat_kernel_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_load_dword s10, s[4:5], 0x8
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB20_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB20_0:
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: v2bfloat_kernel_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -1072,6 +1411,24 @@ define amdgpu_kernel void @v3bfloat_kernel_preload_arg(ptr addrspace(1) inreg %o
; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: v3bfloat_kernel_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB21_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB21_0:
+; GISEL-GFX90A-NEXT: s_lshr_b32 s0, s10, 16
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9] offset:2
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s11
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9] offset:4
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: v3bfloat_kernel_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -1118,6 +1475,21 @@ define amdgpu_kernel void @v6bfloat_kernel_preload_arg(ptr addrspace(1) inreg %o
; GFX90a-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: v6bfloat_kernel_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB22_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB22_0:
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s12
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, s13
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, s14
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GISEL-GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: v6bfloat_kernel_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -1171,6 +1543,38 @@ define amdgpu_kernel void @half_v7bfloat_kernel_preload_arg(ptr addrspace(1) inr
; GFX90a-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: half_v7bfloat_kernel_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB23_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB23_0:
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x20
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: s_lshr_b32 s2, s12, 16
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s12
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[0:1]
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s2
+; GISEL-GFX90A-NEXT: s_lshr_b32 s3, s13, 16
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[0:1] offset:2
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s13
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[0:1] offset:4
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s3
+; GISEL-GFX90A-NEXT: s_lshr_b32 s6, s14, 16
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[0:1] offset:6
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s14
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[0:1] offset:8
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s6
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[0:1] offset:10
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s15
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[0:1] offset:12
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: half_v7bfloat_kernel_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -1218,6 +1622,21 @@ define amdgpu_kernel void @i1_kernel_preload_arg(ptr addrspace(1) inreg %out, i1
; GFX90a-NEXT: global_store_byte v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: i1_kernel_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_load_dword s10, s[4:5], 0x8
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB24_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB24_0:
+; GISEL-GFX90A-NEXT: s_and_b32 s0, s10, 1
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_byte v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: i1_kernel_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -1265,6 +1684,20 @@ define amdgpu_kernel void @fp128_kernel_preload_arg(ptr addrspace(1) inreg %out,
; GFX90a-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: fp128_kernel_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB25_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB25_0:
+; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[12:13], s[12:13] op_sel:[0,1]
+; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[2:3], s[14:15], s[14:15] op_sel:[0,1]
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v4, 0
+; GISEL-GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: fp128_kernel_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -1325,6 +1758,38 @@ define amdgpu_kernel void @v7i8_kernel_preload_arg(ptr addrspace(1) inreg %out,
; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: v7i8_kernel_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB26_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB26_0:
+; GISEL-GFX90A-NEXT: s_and_b32 s2, 0xffff, s10
+; GISEL-GFX90A-NEXT: s_lshr_b32 s2, s2, 8
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: s_lshr_b32 s0, s10, 16
+; GISEL-GFX90A-NEXT: global_store_byte v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s2
+; GISEL-GFX90A-NEXT: s_lshr_b32 s3, s10, 24
+; GISEL-GFX90A-NEXT: global_store_byte v1, v0, s[8:9] offset:1
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: s_and_b32 s4, 0xffff, s11
+; GISEL-GFX90A-NEXT: global_store_byte v1, v0, s[8:9] offset:2
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s3
+; GISEL-GFX90A-NEXT: s_lshr_b32 s4, s4, 8
+; GISEL-GFX90A-NEXT: global_store_byte v1, v0, s[8:9] offset:3
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s11
+; GISEL-GFX90A-NEXT: s_lshr_b32 s1, s11, 16
+; GISEL-GFX90A-NEXT: global_store_byte v1, v0, s[8:9] offset:4
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s4
+; GISEL-GFX90A-NEXT: global_store_byte v1, v0, s[8:9] offset:5
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s1
+; GISEL-GFX90A-NEXT: global_store_byte v1, v0, s[8:9] offset:6
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: v7i8_kernel_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -1380,6 +1845,34 @@ define amdgpu_kernel void @v7half_kernel_preload_arg(ptr addrspace(1) inreg %out
; GFX90a-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: v7half_kernel_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB27_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB27_0:
+; GISEL-GFX90A-NEXT: s_lshr_b32 s0, s12, 16
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s12
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: s_lshr_b32 s1, s13, 16
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9] offset:2
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s13
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9] offset:4
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s1
+; GISEL-GFX90A-NEXT: s_lshr_b32 s2, s14, 16
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9] offset:6
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s14
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9] offset:8
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s2
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9] offset:10
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s15
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9] offset:12
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: v7half_kernel_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -1427,6 +1920,22 @@ define amdgpu_kernel void @i16_i32_kernel_preload_arg(ptr addrspace(1) inreg %ou
; GFX90a-NEXT: global_store_dword v0, v1, s[12:13]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: i16_i32_kernel_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB28_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB28_0:
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s11
+; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[12:13]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: i16_i32_kernel_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -1479,6 +1988,25 @@ define amdgpu_kernel void @i16_v3i32_kernel_preload_arg(ptr addrspace(1) inreg %
; GFX90a-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: i16_v3i32_kernel_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB29_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB29_0:
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x20
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v3, 0
+; GISEL-GFX90A-NEXT: global_store_short v3, v0, s[8:9]
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s12
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, s13
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, s14
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: i16_v3i32_kernel_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -1525,6 +2053,23 @@ define amdgpu_kernel void @i16_i16_kernel_preload_arg(ptr addrspace(1) inreg %ou
; GFX90a-NEXT: global_store_short_d16_hi v0, v1, s[12:13]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: i16_i16_kernel_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB30_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB30_0:
+; GISEL-GFX90A-NEXT: s_lshr_b32 s0, s10, 16
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[12:13]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: i16_i16_kernel_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -1579,6 +2124,23 @@ define amdgpu_kernel void @i16_v2i8_kernel_preload_arg(ptr addrspace(1) inreg %o
; GFX90a-NEXT: global_store_short v0, v1, s[12:13]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: i16_v2i8_kernel_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB31_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB31_0:
+; GISEL-GFX90A-NEXT: s_lshr_b32 s0, s10, 16
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[12:13]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: i16_v2i8_kernel_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -1629,6 +2191,23 @@ define amdgpu_kernel void @i32_ptr1_i32_staggered_preload_arg(i32 inreg %arg0, p
; GFX90a-NEXT: global_store_dword v0, v1, s[0:1]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: i32_ptr1_i32_staggered_preload_arg:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dword s8, s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB32_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB32_0:
+; GISEL-GFX90A-NEXT: s_load_dword s2, s[4:5], 0x10
+; GISEL-GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_add_i32 s2, s8, s2
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s2
+; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[0:1]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: i32_ptr1_i32_staggered_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -1674,6 +2253,20 @@ define amdgpu_kernel void @ptr1_i8_trailing_unused(ptr addrspace(1) inreg %out,
; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
; GFX90a-NEXT: s_endpgm
;
+; GISEL-GFX90A-LABEL: ptr1_i8_trailing_unused:
+; GISEL-GFX90A: ; %bb.1:
+; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GISEL-GFX90A-NEXT: s_branch .LBB33_0
+; GISEL-GFX90A-NEXT: .p2align 8
+; GISEL-GFX90A-NEXT: ; %bb.2:
+; GISEL-GFX90A-NEXT: .LBB33_0:
+; GISEL-GFX90A-NEXT: s_and_b32 s0, s10, 0xff
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
+; GISEL-GFX90A-NEXT: s_endpgm
+;
; GFX1250-LABEL: ptr1_i8_trailing_unused:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
>From bffd4af987e9fb0ff33e70680d02a431aa8b8394 Mon Sep 17 00:00:00 2001
From: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
Date: Mon, 29 Jun 2026 14:54:18 +0530
Subject: [PATCH 3/6] [AMDGPU][GlobalISel] Fix kernarg preload size accounting
GlobalISel records CCValAssign locations using legal MVTs, which can round odd-sized arguments such as i192 up to i256. Kernarg preload accounting needs to use the original kernarg byte layout instead, or the preload sequence can stop before an argument that actually fits in the preload SGPR budget.
Use the split argument's allocation size for preload SGPR accounting and drop unreachable preload-lowering branches. Add GlobalISel coverage for the existing kernarg preload tests and IRTranslator edge cases for v1 arguments and zero-sized arguments.
Co-authored-by: GPT-5 <noreply at openai.com>
Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
---
llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp | 13 +-
.../irtranslator-preload-kernargs.ll | 38 +
.../AMDGPU/preload-implicit-kernargs.ll | 3149 ++++++-----
llvm/test/CodeGen/AMDGPU/preload-kernargs.ll | 4774 ++++++++++-------
4 files changed, 4748 insertions(+), 3226 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
index 92e90a516e02c..4b76a06a7f22d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
@@ -322,8 +322,6 @@ static Register adjustPreloadedArgType(MachineIRBuilder &B, Register Src,
: DstTy;
if (SrcTy.getSizeInBits() != IntDstTy.getSizeInBits())
Src = B.buildAnyExtOrTrunc(IntDstTy, Src).getReg(0);
- else if (SrcTy != IntDstTy)
- Src = B.buildBitcast(IntDstTy, Src).getReg(0);
if (DstTy.isPointer())
return B.buildIntToPtr(DstTy, Src).getReg(0);
@@ -429,19 +427,18 @@ static void allocatePreloadKernArgSGPRs(
if (!InPreloadSequence || !Arg.hasInRegAttr())
break;
- unsigned ArgIdx = Arg.getArgNo();
- if (InIdx < SplitArgs.size() && SplitArgs[InIdx].OrigArgIndex != ArgIdx)
- break;
-
- for (; InIdx < SplitArgs.size() && SplitArgs[InIdx].OrigArgIndex == ArgIdx;
+ for (unsigned ArgIdx = Arg.getArgNo();
+ InIdx < SplitArgs.size() && SplitArgs[InIdx].OrigArgIndex == ArgIdx;
++InIdx) {
const CCValAssign &ArgLoc = ArgLocs[InIdx];
assert(ArgLoc.isMemLoc());
const Align KernelArgBaseAlign = Align(16);
unsigned ArgOffset = ArgLoc.getLocMemOffset();
Align Alignment = commonAlignment(KernelArgBaseAlign, ArgOffset);
+ // CCValAssign may need a rounded legal MVT, but preload SGPR accounting
+ // must follow the original kernarg byte layout.
unsigned NumAllocSGPRs =
- alignTo(ArgLoc.getLocVT().getFixedSizeInBits(), 32) / 32;
+ alignTo(DL.getTypeAllocSize(SplitArgs[InIdx].Ty), 4) / 4;
if (Arg.hasAttribute("amdgpu-hidden-argument")) {
// Hidden arguments are laid out after the explicit kernargs, aligned to
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-preload-kernargs.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-preload-kernargs.ll
index 70541447e49e9..961e78d425a56 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-preload-kernargs.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-preload-kernargs.ll
@@ -101,4 +101,42 @@ define amdgpu_kernel void @preload_hidden_block_count_x(ptr addrspace(1) inreg %
ret void
}
+define amdgpu_kernel void @preload_v1i32_inreg(<1 x i32> inreg %x, ptr addrspace(1) %out) #0 {
+ ; GFX90A-LABEL: name: preload_v1i32_inreg
+ ; GFX90A: bb.1 (%ir-block.0):
+ ; GFX90A-NEXT: liveins: $sgpr6, $sgpr4_sgpr5
+ ; GFX90A-NEXT: {{ $}}
+ ; GFX90A-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr6
+ ; GFX90A-NEXT: [[COPY1:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
+ ; GFX90A-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]]
+ ; GFX90A-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
+ ; GFX90A-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
+ ; GFX90A-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; GFX90A-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw nusw inbounds G_PTR_ADD [[INT]], [[C]](s64)
+ ; GFX90A-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from %ir.out.kernarg.offset, addrspace 4)
+ ; GFX90A-NEXT: G_STORE [[COPY3]](s32), [[LOAD]](p1) :: (store (s32) into %ir.out.load, addrspace 1)
+ ; GFX90A-NEXT: S_ENDPGM 0
+ store <1 x i32> %x, ptr addrspace(1) %out, align 4
+ ret void
+}
+
+define amdgpu_kernel void @preload_skip_empty_struct_inreg({} inreg %empty, i32 inreg %x, ptr addrspace(1) %out) #0 {
+ ; GFX90A-LABEL: name: preload_skip_empty_struct_inreg
+ ; GFX90A: bb.1 (%ir-block.0):
+ ; GFX90A-NEXT: liveins: $sgpr6, $sgpr4_sgpr5
+ ; GFX90A-NEXT: {{ $}}
+ ; GFX90A-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr6
+ ; GFX90A-NEXT: [[COPY1:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
+ ; GFX90A-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]]
+ ; GFX90A-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
+ ; GFX90A-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
+ ; GFX90A-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; GFX90A-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw nusw inbounds G_PTR_ADD [[INT]], [[C]](s64)
+ ; GFX90A-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from %ir.out.kernarg.offset, addrspace 4)
+ ; GFX90A-NEXT: G_STORE [[COPY3]](s32), [[LOAD]](p1) :: (store (s32) into %ir.out.load, addrspace 1)
+ ; GFX90A-NEXT: S_ENDPGM 0
+ store i32 %x, ptr addrspace(1) %out, align 4
+ ret void
+}
+
attributes #0 = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-no-wwm" "target-cpu"="gfx90a" }
diff --git a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
index bbadf150e1e14..b58757ddfba93 100644
--- a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
+++ b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
@@ -1,59 +1,83 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX942 %s
-; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX90a %s
-; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefixes=GISEL-GFX90A %s
-; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16 %s
-; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16 %s
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX942,GFX942-SDAG %s
+; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX942,GFX942-GISEL %s
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX90a,GFX90a-SDAG %s
+; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX90a,GFX90a-GISEL %s
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16,GFX1250-SDAG,GFX1250-FAKE16-SDAG %s
+; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16,GFX1250-GISEL,GFX1250-FAKE16-GISEL %s
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16,GFX1250-SDAG,GFX1250-REAL16-SDAG %s
+; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16,GFX1250-GISEL,GFX1250-REAL16-GISEL %s
define amdgpu_kernel void @preload_block_count_x(ptr addrspace(1) inreg %out) #0 {
-; GFX942-LABEL: preload_block_count_x:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dword s4, s[0:1], 0x8
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB0_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB0_0:
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s4
-; GFX942-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: preload_block_count_x:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x8
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB0_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB0_0:
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s10
-; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: preload_block_count_x:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_load_dword s10, s[4:5], 0x8
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB0_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB0_0:
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: preload_block_count_x:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
-; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: preload_block_count_x:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dword s4, s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB0_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB0_0:
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s4
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: preload_block_count_x:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dword s4, s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB0_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB0_0:
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: preload_block_count_x:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_load_dword s10, s[4:5], 0x8
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB0_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB0_0:
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s10
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: preload_block_count_x:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_load_dword s10, s[4:5], 0x8
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB0_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB0_0:
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s10
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_dword v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: preload_block_count_x:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: preload_block_count_x:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, 0
+; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
%imp_arg_ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
%load = load i32, ptr addrspace(4) %imp_arg_ptr
store i32 %load, ptr addrspace(1) %out
@@ -61,55 +85,77 @@ define amdgpu_kernel void @preload_block_count_x(ptr addrspace(1) inreg %out) #0
}
define amdgpu_kernel void @preload_unused_arg_block_count_x(ptr addrspace(1) inreg %out, i32 inreg) #0 {
-; GFX942-LABEL: preload_unused_arg_block_count_x:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
-; GFX942-NEXT: s_load_dword s6, s[0:1], 0x10
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB1_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB1_0:
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s6
-; GFX942-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: preload_unused_arg_block_count_x:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GFX90a-NEXT: s_load_dword s12, s[4:5], 0x10
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB1_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB1_0:
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s12
-; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: preload_unused_arg_block_count_x:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_load_dword s12, s[4:5], 0x10
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB1_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB1_0:
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s12
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: preload_unused_arg_block_count_x:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s6
-; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: preload_unused_arg_block_count_x:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_load_dword s6, s[0:1], 0x10
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB1_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB1_0:
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s6
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: preload_unused_arg_block_count_x:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_load_dword s6, s[0:1], 0x10
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB1_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB1_0:
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: preload_unused_arg_block_count_x:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_load_dword s12, s[4:5], 0x10
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB1_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB1_0:
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s12
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: preload_unused_arg_block_count_x:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_load_dword s12, s[4:5], 0x10
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB1_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB1_0:
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s12
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_dword v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: preload_unused_arg_block_count_x:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s6
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: preload_unused_arg_block_count_x:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, 0
+; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
%imp_arg_ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
%load = load i32, ptr addrspace(4) %imp_arg_ptr
store i32 %load, ptr addrspace(1) %out
@@ -117,57 +163,79 @@ define amdgpu_kernel void @preload_unused_arg_block_count_x(ptr addrspace(1) inr
}
define amdgpu_kernel void @no_free_sgprs_block_count_x(ptr addrspace(1) inreg %out, i256 inreg) {
-; GFX942-LABEL: no_free_sgprs_block_count_x:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB2_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB2_0:
-; GFX942-NEXT: s_load_dword s0, s[4:5], 0x28
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v1, s0
-; GFX942-NEXT: global_store_dword v0, v1, s[8:9]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: no_free_sgprs_block_count_x:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx2 s[14:15], s[8:9], 0x0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB2_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB2_0:
-; GFX90a-NEXT: s_load_dword s0, s[8:9], 0x28
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: v_mov_b32_e32 v1, s0
-; GFX90a-NEXT: global_store_dword v0, v1, s[14:15]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: no_free_sgprs_block_count_x:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[14:15], s[8:9], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB2_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB2_0:
-; GISEL-GFX90A-NEXT: s_load_dword s0, s[8:9], 0x28
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[14:15]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: no_free_sgprs_block_count_x:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s18
-; GFX1250-NEXT: global_store_b32 v0, v1, s[8:9]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: no_free_sgprs_block_count_x:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB2_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB2_0:
+; GFX942-SDAG-NEXT: s_load_dword s0, s[4:5], 0x28
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[8:9]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: no_free_sgprs_block_count_x:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB2_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB2_0:
+; GFX942-GISEL-NEXT: s_load_dword s0, s[4:5], 0x28
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX942-GISEL-NEXT: global_store_dword v1, v0, s[8:9]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: no_free_sgprs_block_count_x:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[14:15], s[8:9], 0x0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB2_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB2_0:
+; GFX90a-SDAG-NEXT: s_load_dword s0, s[8:9], 0x28
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[14:15]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: no_free_sgprs_block_count_x:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[14:15], s[8:9], 0x0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB2_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB2_0:
+; GFX90a-GISEL-NEXT: s_load_dword s0, s[8:9], 0x28
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: global_store_dword v1, v0, s[14:15]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: no_free_sgprs_block_count_x:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s18
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[8:9]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: no_free_sgprs_block_count_x:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s18 :: v_dual_mov_b32 v1, 0
+; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[8:9]
+; GFX1250-GISEL-NEXT: s_endpgm
%imp_arg_ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
%load = load i32, ptr addrspace(4) %imp_arg_ptr
store i32 %load, ptr addrspace(1) %out
@@ -175,44 +243,63 @@ define amdgpu_kernel void @no_free_sgprs_block_count_x(ptr addrspace(1) inreg %o
}
define amdgpu_kernel void @no_inreg_block_count_x(ptr addrspace(1) %out) #0 {
-; GFX942-LABEL: no_inreg_block_count_x:
-; GFX942: ; %bb.0:
-; GFX942-NEXT: s_load_dword s4, s[0:1], 0x8
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v1, s4
-; GFX942-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: no_inreg_block_count_x:
-; GFX90a: ; %bb.0:
-; GFX90a-NEXT: s_load_dword s2, s[4:5], 0x8
-; GFX90a-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: v_mov_b32_e32 v1, s2
-; GFX90a-NEXT: global_store_dword v0, v1, s[0:1]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: no_inreg_block_count_x:
-; GISEL-GFX90A: ; %bb.0:
-; GISEL-GFX90A-NEXT: s_load_dword s2, s[4:5], 0x8
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: no_inreg_block_count_x:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b96 s[0:2], s[0:1], 0x0 nv
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: no_inreg_block_count_x:
+; GFX942-SDAG: ; %bb.0:
+; GFX942-SDAG-NEXT: s_load_dword s4, s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s4
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: no_inreg_block_count_x:
+; GFX942-GISEL: ; %bb.0:
+; GFX942-GISEL-NEXT: s_load_dword s4, s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: no_inreg_block_count_x:
+; GFX90a-SDAG: ; %bb.0:
+; GFX90a-SDAG-NEXT: s_load_dword s2, s[4:5], 0x8
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s2
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: no_inreg_block_count_x:
+; GFX90a-GISEL: ; %bb.0:
+; GFX90a-GISEL-NEXT: s_load_dword s2, s[4:5], 0x8
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX90a-GISEL-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: no_inreg_block_count_x:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_load_b96 s[0:2], s[0:1], 0x0 nv
+; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: no_inreg_block_count_x:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_load_b96 s[0:2], s[0:1], 0x0 nv
+; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
+; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX1250-GISEL-NEXT: s_endpgm
%imp_arg_ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
%load = load i32, ptr addrspace(4) %imp_arg_ptr
store i32 %load, ptr addrspace(1) %out
@@ -223,46 +310,67 @@ define amdgpu_kernel void @no_inreg_block_count_x(ptr addrspace(1) %out) #0 {
; args are inreg (preloaded).
define amdgpu_kernel void @mixed_inreg_block_count_x(ptr addrspace(1) %out, i32 inreg) #0 {
-; GFX942-LABEL: mixed_inreg_block_count_x:
-; GFX942: ; %bb.0:
-; GFX942-NEXT: s_load_dword s4, s[0:1], 0x10
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v1, s4
-; GFX942-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: mixed_inreg_block_count_x:
-; GFX90a: ; %bb.0:
-; GFX90a-NEXT: s_load_dword s2, s[4:5], 0x10
-; GFX90a-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: v_mov_b32_e32 v1, s2
-; GFX90a-NEXT: global_store_dword v0, v1, s[0:1]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: mixed_inreg_block_count_x:
-; GISEL-GFX90A: ; %bb.0:
-; GISEL-GFX90A-NEXT: s_load_dword s2, s[4:5], 0x10
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: mixed_inreg_block_count_x:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: s_load_b32 s4, s[0:1], 0x10 nv
-; GFX1250-NEXT: s_load_b64 s[2:3], s[0:1], 0x0 nv
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
-; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: mixed_inreg_block_count_x:
+; GFX942-SDAG: ; %bb.0:
+; GFX942-SDAG-NEXT: s_load_dword s4, s[0:1], 0x10
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s4
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: mixed_inreg_block_count_x:
+; GFX942-GISEL: ; %bb.0:
+; GFX942-GISEL-NEXT: s_load_dword s4, s[0:1], 0x10
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: mixed_inreg_block_count_x:
+; GFX90a-SDAG: ; %bb.0:
+; GFX90a-SDAG-NEXT: s_load_dword s2, s[4:5], 0x10
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s2
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: mixed_inreg_block_count_x:
+; GFX90a-GISEL: ; %bb.0:
+; GFX90a-GISEL-NEXT: s_load_dword s2, s[4:5], 0x10
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX90a-GISEL-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: mixed_inreg_block_count_x:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_clause 0x1
+; GFX1250-SDAG-NEXT: s_load_b32 s4, s[0:1], 0x10 nv
+; GFX1250-SDAG-NEXT: s_load_b64 s[2:3], s[0:1], 0x0 nv
+; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: mixed_inreg_block_count_x:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_clause 0x1
+; GFX1250-GISEL-NEXT: s_load_b32 s4, s[0:1], 0x10 nv
+; GFX1250-GISEL-NEXT: s_load_b64 s[2:3], s[0:1], 0x0 nv
+; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s4
+; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
%imp_arg_ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
%load = load i32, ptr addrspace(4) %imp_arg_ptr
store i32 %load, ptr addrspace(1) %out
@@ -270,50 +378,65 @@ define amdgpu_kernel void @mixed_inreg_block_count_x(ptr addrspace(1) %out, i32
}
define amdgpu_kernel void @incorrect_type_i64_block_count_x(ptr addrspace(1) inreg %out) #0 {
-; GFX942-LABEL: incorrect_type_i64_block_count_x:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB5_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB5_0:
-; GFX942-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x8
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX942-NEXT: global_store_dwordx2 v0, v[2:3], s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: incorrect_type_i64_block_count_x:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB5_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB5_0:
-; GFX90a-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: v_pk_mov_b32 v[2:3], s[0:1], s[0:1] op_sel:[0,1]
-; GFX90a-NEXT: global_store_dwordx2 v0, v[2:3], s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: incorrect_type_i64_block_count_x:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB5_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB5_0:
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, 0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
-; GISEL-GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: incorrect_type_i64_block_count_x:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB5_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB5_0:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x8
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX942-SDAG-NEXT: global_store_dwordx2 v0, v[2:3], s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: incorrect_type_i64_block_count_x:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB5_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB5_0:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x8
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
+; GFX942-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: incorrect_type_i64_block_count_x:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB5_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB5_0:
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: v_pk_mov_b32 v[2:3], s[0:1], s[0:1] op_sel:[0,1]
+; GFX90a-SDAG-NEXT: global_store_dwordx2 v0, v[2:3], s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: incorrect_type_i64_block_count_x:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB5_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB5_0:
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
+; GFX90a-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
;
; GFX1250-LABEL: incorrect_type_i64_block_count_x:
; GFX1250: ; %bb.0:
@@ -331,68 +454,102 @@ define amdgpu_kernel void @incorrect_type_i64_block_count_x(ptr addrspace(1) inr
}
define amdgpu_kernel void @incorrect_type_i16_block_count_x(ptr addrspace(1) inreg %out) #0 {
-; GFX942-LABEL: incorrect_type_i16_block_count_x:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB6_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB6_0:
-; GFX942-NEXT: s_load_dword s0, s[0:1], 0x8
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v1, s0
-; GFX942-NEXT: global_store_short v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: incorrect_type_i16_block_count_x:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB6_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB6_0:
-; GFX90a-NEXT: s_load_dword s0, s[4:5], 0x8
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: v_mov_b32_e32 v1, s0
-; GFX90a-NEXT: global_store_short v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: incorrect_type_i16_block_count_x:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB6_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB6_0:
-; GISEL-GFX90A-NEXT: s_load_dword s0, s[4:5], 0x8
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-FAKE16-LABEL: incorrect_type_i16_block_count_x:
-; GFX1250-FAKE16: ; %bb.0:
-; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v0, 0
-; GFX1250-FAKE16-NEXT: global_load_u16 v1, v0, s[0:1] offset:8 nv
-; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-FAKE16-NEXT: global_store_b16 v0, v1, s[2:3]
-; GFX1250-FAKE16-NEXT: s_endpgm
-;
-; GFX1250-REAL16-LABEL: incorrect_type_i16_block_count_x:
-; GFX1250-REAL16: ; %bb.0:
-; GFX1250-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-REAL16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-REAL16-NEXT: global_load_u16 v0, v1, s[0:1] offset:8 nv
-; GFX1250-REAL16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-REAL16-NEXT: global_store_b16 v1, v0, s[2:3]
-; GFX1250-REAL16-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: incorrect_type_i16_block_count_x:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB6_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB6_0:
+; GFX942-SDAG-NEXT: s_load_dword s0, s[0:1], 0x8
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX942-SDAG-NEXT: global_store_short v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: incorrect_type_i16_block_count_x:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB6_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB6_0:
+; GFX942-GISEL-NEXT: s_load_dword s0, s[0:1], 0x8
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: incorrect_type_i16_block_count_x:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB6_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB6_0:
+; GFX90a-SDAG-NEXT: s_load_dword s0, s[4:5], 0x8
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX90a-SDAG-NEXT: global_store_short v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: incorrect_type_i16_block_count_x:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB6_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB6_0:
+; GFX90a-GISEL-NEXT: s_load_dword s0, s[4:5], 0x8
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-FAKE16-SDAG-LABEL: incorrect_type_i16_block_count_x:
+; GFX1250-FAKE16-SDAG: ; %bb.0:
+; GFX1250-FAKE16-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-FAKE16-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX1250-FAKE16-SDAG-NEXT: global_load_u16 v1, v0, s[0:1] offset:8 nv
+; GFX1250-FAKE16-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250-FAKE16-SDAG-NEXT: global_store_b16 v0, v1, s[2:3]
+; GFX1250-FAKE16-SDAG-NEXT: s_endpgm
+;
+; GFX1250-FAKE16-GISEL-LABEL: incorrect_type_i16_block_count_x:
+; GFX1250-FAKE16-GISEL: ; %bb.0:
+; GFX1250-FAKE16-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-FAKE16-GISEL-NEXT: s_load_u16 s0, s[0:1], 0x8 nv
+; GFX1250-FAKE16-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s0
+; GFX1250-FAKE16-GISEL-NEXT: global_store_b16 v1, v0, s[2:3]
+; GFX1250-FAKE16-GISEL-NEXT: s_endpgm
+;
+; GFX1250-REAL16-SDAG-LABEL: incorrect_type_i16_block_count_x:
+; GFX1250-REAL16-SDAG: ; %bb.0:
+; GFX1250-REAL16-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-REAL16-SDAG-NEXT: v_mov_b32_e32 v1, 0
+; GFX1250-REAL16-SDAG-NEXT: global_load_u16 v0, v1, s[0:1] offset:8 nv
+; GFX1250-REAL16-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250-REAL16-SDAG-NEXT: global_store_b16 v1, v0, s[2:3]
+; GFX1250-REAL16-SDAG-NEXT: s_endpgm
+;
+; GFX1250-REAL16-GISEL-LABEL: incorrect_type_i16_block_count_x:
+; GFX1250-REAL16-GISEL: ; %bb.0:
+; GFX1250-REAL16-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-REAL16-GISEL-NEXT: s_load_u16 s0, s[0:1], 0x8 nv
+; GFX1250-REAL16-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1250-REAL16-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-GISEL-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX1250-REAL16-GISEL-NEXT: global_store_b16 v1, v0, s[2:3]
+; GFX1250-REAL16-GISEL-NEXT: s_endpgm
%imp_arg_ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
%load = load i16, ptr addrspace(4) %imp_arg_ptr
store i16 %load, ptr addrspace(1) %out
@@ -400,52 +557,73 @@ define amdgpu_kernel void @incorrect_type_i16_block_count_x(ptr addrspace(1) inr
}
define amdgpu_kernel void @preload_block_count_y(ptr addrspace(1) inreg %out) #0 {
-; GFX942-LABEL: preload_block_count_y:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB7_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB7_0:
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s5
-; GFX942-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: preload_block_count_y:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB7_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB7_0:
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s11
-; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: preload_block_count_y:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB7_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB7_0:
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s11
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: preload_block_count_y:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s5
-; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: preload_block_count_y:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB7_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB7_0:
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s5
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: preload_block_count_y:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB7_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB7_0:
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: preload_block_count_y:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB7_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB7_0:
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s11
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: preload_block_count_y:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB7_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB7_0:
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s11
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_dword v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: preload_block_count_y:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s5
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: preload_block_count_y:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s5 :: v_dual_mov_b32 v1, 0
+; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
%imp_arg_ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
%gep = getelementptr i8, ptr addrspace(4) %imp_arg_ptr, i32 4
%load = load i32, ptr addrspace(4) %gep
@@ -454,59 +632,83 @@ define amdgpu_kernel void @preload_block_count_y(ptr addrspace(1) inreg %out) #0
}
define amdgpu_kernel void @random_incorrect_offset(ptr addrspace(1) inreg %out) #0 {
-; GFX942-LABEL: random_incorrect_offset:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB8_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB8_0:
-; GFX942-NEXT: s_load_dword s0, s[0:1], 0xa
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v1, s0
-; GFX942-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: random_incorrect_offset:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB8_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB8_0:
-; GFX90a-NEXT: s_load_dword s0, s[4:5], 0xa
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: v_mov_b32_e32 v1, s0
-; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: random_incorrect_offset:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB8_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB8_0:
-; GISEL-GFX90A-NEXT: s_load_dword s0, s[4:5], 0xa
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: random_incorrect_offset:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b32 s0, s[0:1], 0xa nv
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
-; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: random_incorrect_offset:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB8_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB8_0:
+; GFX942-SDAG-NEXT: s_load_dword s0, s[0:1], 0xa
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: random_incorrect_offset:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB8_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB8_0:
+; GFX942-GISEL-NEXT: s_load_dword s0, s[0:1], 0xa
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX942-GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: random_incorrect_offset:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB8_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB8_0:
+; GFX90a-SDAG-NEXT: s_load_dword s0, s[4:5], 0xa
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: random_incorrect_offset:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB8_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB8_0:
+; GFX90a-GISEL-NEXT: s_load_dword s0, s[4:5], 0xa
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: global_store_dword v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: random_incorrect_offset:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_load_b32 s0, s[0:1], 0xa nv
+; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: random_incorrect_offset:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_load_b32 s0, s[0:1], 0xa nv
+; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s0
+; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
%imp_arg_ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
%gep = getelementptr i8, ptr addrspace(4) %imp_arg_ptr, i32 2
%load = load i32, ptr addrspace(4) %gep
@@ -515,55 +717,77 @@ define amdgpu_kernel void @random_incorrect_offset(ptr addrspace(1) inreg %out)
}
define amdgpu_kernel void @preload_block_count_z(ptr addrspace(1) inreg %out) #0 {
-; GFX942-LABEL: preload_block_count_z:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
-; GFX942-NEXT: s_load_dword s6, s[0:1], 0x10
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB9_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB9_0:
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s6
-; GFX942-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: preload_block_count_z:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GFX90a-NEXT: s_load_dword s12, s[4:5], 0x10
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB9_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB9_0:
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s12
-; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: preload_block_count_z:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_load_dword s12, s[4:5], 0x10
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB9_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB9_0:
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s12
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: preload_block_count_z:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s6
-; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: preload_block_count_z:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_load_dword s6, s[0:1], 0x10
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB9_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB9_0:
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s6
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: preload_block_count_z:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_load_dword s6, s[0:1], 0x10
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB9_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB9_0:
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: preload_block_count_z:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_load_dword s12, s[4:5], 0x10
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB9_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB9_0:
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s12
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: preload_block_count_z:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_load_dword s12, s[4:5], 0x10
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB9_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB9_0:
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s12
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_dword v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: preload_block_count_z:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s6
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: preload_block_count_z:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, 0
+; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
%imp_arg_ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
%gep = getelementptr i8, ptr addrspace(4) %imp_arg_ptr, i32 8
%load = load i32, ptr addrspace(4) %gep
@@ -572,64 +796,92 @@ define amdgpu_kernel void @preload_block_count_z(ptr addrspace(1) inreg %out) #0
}
define amdgpu_kernel void @preload_block_count_x_imparg_align_ptr_i8(ptr addrspace(1) inreg %out, i8 inreg %val) #0 {
-; GFX942-LABEL: preload_block_count_x_imparg_align_ptr_i8:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
-; GFX942-NEXT: s_load_dword s6, s[0:1], 0x10
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB10_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB10_0:
-; GFX942-NEXT: s_and_b32 s0, s4, 0xff
-; GFX942-NEXT: s_add_i32 s0, s6, s0
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s0
-; GFX942-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: preload_block_count_x_imparg_align_ptr_i8:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GFX90a-NEXT: s_load_dword s12, s[4:5], 0x10
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB10_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB10_0:
-; GFX90a-NEXT: s_and_b32 s0, s10, 0xff
-; GFX90a-NEXT: s_add_i32 s0, s12, s0
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s0
-; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: preload_block_count_x_imparg_align_ptr_i8:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_load_dword s12, s[4:5], 0x10
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB10_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB10_0:
-; GISEL-GFX90A-NEXT: s_and_b32 s0, s10, 0xff
-; GISEL-GFX90A-NEXT: s_add_i32 s0, s12, s0
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: preload_block_count_x_imparg_align_ptr_i8:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_and_b32 s0, s4, 0xff
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_add_co_i32 s0, s6, s0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
-; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: preload_block_count_x_imparg_align_ptr_i8:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_load_dword s6, s[0:1], 0x10
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB10_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB10_0:
+; GFX942-SDAG-NEXT: s_and_b32 s0, s4, 0xff
+; GFX942-SDAG-NEXT: s_add_i32 s0, s6, s0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: preload_block_count_x_imparg_align_ptr_i8:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_load_dword s6, s[0:1], 0x10
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB10_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB10_0:
+; GFX942-GISEL-NEXT: s_and_b32 s0, s4, 0xff
+; GFX942-GISEL-NEXT: s_add_i32 s0, s6, s0
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: preload_block_count_x_imparg_align_ptr_i8:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_load_dword s12, s[4:5], 0x10
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB10_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB10_0:
+; GFX90a-SDAG-NEXT: s_and_b32 s0, s10, 0xff
+; GFX90a-SDAG-NEXT: s_add_i32 s0, s12, s0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: preload_block_count_x_imparg_align_ptr_i8:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_load_dword s12, s[4:5], 0x10
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB10_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB10_0:
+; GFX90a-GISEL-NEXT: s_and_b32 s0, s10, 0xff
+; GFX90a-GISEL-NEXT: s_add_i32 s0, s12, s0
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_dword v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: preload_block_count_x_imparg_align_ptr_i8:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_and_b32 s0, s4, 0xff
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1250-SDAG-NEXT: s_add_co_i32 s0, s6, s0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: preload_block_count_x_imparg_align_ptr_i8:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_and_b32 s0, s4, 0xff
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1250-GISEL-NEXT: s_add_co_i32 s0, s6, s0
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
%imp_arg_ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
%load = load i32, ptr addrspace(4) %imp_arg_ptr
%ext = zext i8 %val to i32
@@ -639,65 +891,90 @@ define amdgpu_kernel void @preload_block_count_x_imparg_align_ptr_i8(ptr addrspa
}
define amdgpu_kernel void @preload_block_count_xyz(ptr addrspace(1) inreg %out) #0 {
-; GFX942-LABEL: preload_block_count_xyz:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
-; GFX942-NEXT: s_load_dword s6, s[0:1], 0x10
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB11_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB11_0:
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, s4
-; GFX942-NEXT: v_mov_b32_e32 v1, s5
-; GFX942-NEXT: v_mov_b32_e32 v2, s6
-; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: preload_block_count_xyz:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GFX90a-NEXT: s_load_dword s12, s[4:5], 0x10
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB11_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB11_0:
-; GFX90a-NEXT: v_mov_b32_e32 v3, 0
-; GFX90a-NEXT: v_mov_b32_e32 v0, s10
-; GFX90a-NEXT: v_mov_b32_e32 v1, s11
-; GFX90a-NEXT: v_mov_b32_e32 v2, s12
-; GFX90a-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: preload_block_count_xyz:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_load_dword s12, s[4:5], 0x10
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB11_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB11_0:
-; GISEL-GFX90A-NEXT: s_mov_b32 s0, s10
-; GISEL-GFX90A-NEXT: s_mov_b32 s2, s12
-; GISEL-GFX90A-NEXT: s_mov_b32 s1, s11
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, s1
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, s2
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v3, 0
-; GISEL-GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: preload_block_count_xyz:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s4
-; GFX1250-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v2, s6
-; GFX1250-NEXT: global_store_b96 v3, v[0:2], s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: preload_block_count_xyz:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_load_dword s6, s[0:1], 0x10
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB11_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB11_0:
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s5
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, s6
+; GFX942-SDAG-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: preload_block_count_xyz:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_load_dword s6, s[0:1], 0x10
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB11_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB11_0:
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v2, s6
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: preload_block_count_xyz:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_load_dword s12, s[4:5], 0x10
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB11_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB11_0:
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v3, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, s10
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s11
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v2, s12
+; GFX90a-SDAG-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: preload_block_count_xyz:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_load_dword s12, s[4:5], 0x10
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB11_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB11_0:
+; GFX90a-GISEL-NEXT: s_mov_b32 s0, s10
+; GFX90a-GISEL-NEXT: s_mov_b32 s2, s12
+; GFX90a-GISEL-NEXT: s_mov_b32 s1, s11
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX90a-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: preload_block_count_xyz:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s4
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v2, s6
+; GFX1250-SDAG-NEXT: global_store_b96 v3, v[0:2], s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: preload_block_count_xyz:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, 0
+; GFX1250-GISEL-NEXT: global_store_b96 v3, v[0:2], s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
%imp_arg_ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
%gep_x = getelementptr i8, ptr addrspace(4) %imp_arg_ptr, i32 0
%load_x = load i32, ptr addrspace(4) %gep_x
@@ -713,59 +990,83 @@ define amdgpu_kernel void @preload_block_count_xyz(ptr addrspace(1) inreg %out)
}
define amdgpu_kernel void @preload_workgroup_size_x(ptr addrspace(1) inreg %out) #0 {
-; GFX942-LABEL: preload_workgroup_size_x:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB12_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB12_0:
-; GFX942-NEXT: s_and_b32 s0, s7, 0xffff
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s0
-; GFX942-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: preload_workgroup_size_x:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GFX90a-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB12_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB12_0:
-; GFX90a-NEXT: s_and_b32 s0, s13, 0xffff
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s0
-; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: preload_workgroup_size_x:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB12_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB12_0:
-; GISEL-GFX90A-NEXT: s_and_b32 s0, s13, 0xffff
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: preload_workgroup_size_x:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_and_b32 s0, s7, 0xffff
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
-; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: preload_workgroup_size_x:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB12_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB12_0:
+; GFX942-SDAG-NEXT: s_and_b32 s0, s7, 0xffff
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: preload_workgroup_size_x:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB12_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB12_0:
+; GFX942-GISEL-NEXT: s_and_b32 s0, s7, 0xffff
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: preload_workgroup_size_x:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB12_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB12_0:
+; GFX90a-SDAG-NEXT: s_and_b32 s0, s13, 0xffff
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: preload_workgroup_size_x:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB12_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB12_0:
+; GFX90a-GISEL-NEXT: s_and_b32 s0, s13, 0xffff
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_dword v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: preload_workgroup_size_x:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_and_b32 s0, s7, 0xffff
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: preload_workgroup_size_x:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_and_b32 s0, s7, 0xffff
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s0
+; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
%imp_arg_ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
%gep = getelementptr i8, ptr addrspace(4) %imp_arg_ptr, i32 12
%load = load i16, ptr addrspace(4) %gep
@@ -775,59 +1076,83 @@ define amdgpu_kernel void @preload_workgroup_size_x(ptr addrspace(1) inreg %out)
}
define amdgpu_kernel void @preload_workgroup_size_y(ptr addrspace(1) inreg %out) #0 {
-; GFX942-LABEL: preload_workgroup_size_y:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB13_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB13_0:
-; GFX942-NEXT: s_lshr_b32 s0, s7, 16
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s0
-; GFX942-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: preload_workgroup_size_y:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GFX90a-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB13_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB13_0:
-; GFX90a-NEXT: s_lshr_b32 s0, s13, 16
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s0
-; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: preload_workgroup_size_y:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB13_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB13_0:
-; GISEL-GFX90A-NEXT: s_lshr_b32 s0, s13, 16
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: preload_workgroup_size_y:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_lshr_b32 s0, s7, 16
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
-; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: preload_workgroup_size_y:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB13_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB13_0:
+; GFX942-SDAG-NEXT: s_lshr_b32 s0, s7, 16
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: preload_workgroup_size_y:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB13_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB13_0:
+; GFX942-GISEL-NEXT: s_lshr_b32 s0, s7, 16
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: preload_workgroup_size_y:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB13_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB13_0:
+; GFX90a-SDAG-NEXT: s_lshr_b32 s0, s13, 16
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: preload_workgroup_size_y:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB13_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB13_0:
+; GFX90a-GISEL-NEXT: s_lshr_b32 s0, s13, 16
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_dword v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: preload_workgroup_size_y:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_lshr_b32 s0, s7, 16
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: preload_workgroup_size_y:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_lshr_b32 s0, s7, 16
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s0
+; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
%imp_arg_ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
%gep = getelementptr i8, ptr addrspace(4) %imp_arg_ptr, i32 14
%load = load i16, ptr addrspace(4) %gep
@@ -837,62 +1162,87 @@ define amdgpu_kernel void @preload_workgroup_size_y(ptr addrspace(1) inreg %out)
}
define amdgpu_kernel void @preload_workgroup_size_z(ptr addrspace(1) inreg %out) #0 {
-; GFX942-LABEL: preload_workgroup_size_z:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
-; GFX942-NEXT: s_load_dword s8, s[0:1], 0x18
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB14_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB14_0:
-; GFX942-NEXT: s_and_b32 s0, s8, 0xffff
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s0
-; GFX942-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: preload_workgroup_size_z:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GFX90a-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
-; GFX90a-NEXT: s_load_dword s14, s[4:5], 0x18
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB14_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB14_0:
-; GFX90a-NEXT: s_and_b32 s0, s14, 0xffff
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s0
-; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: preload_workgroup_size_z:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
-; GISEL-GFX90A-NEXT: s_load_dword s14, s[4:5], 0x18
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB14_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB14_0:
-; GISEL-GFX90A-NEXT: s_and_b32 s0, s14, 0xffff
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: preload_workgroup_size_z:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_and_b32 s0, s8, 0xffff
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
-; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: preload_workgroup_size_z:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_load_dword s8, s[0:1], 0x18
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB14_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB14_0:
+; GFX942-SDAG-NEXT: s_and_b32 s0, s8, 0xffff
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: preload_workgroup_size_z:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_load_dword s8, s[0:1], 0x18
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB14_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB14_0:
+; GFX942-GISEL-NEXT: s_and_b32 s0, s8, 0xffff
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: preload_workgroup_size_z:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
+; GFX90a-SDAG-NEXT: s_load_dword s14, s[4:5], 0x18
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB14_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB14_0:
+; GFX90a-SDAG-NEXT: s_and_b32 s0, s14, 0xffff
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: preload_workgroup_size_z:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
+; GFX90a-GISEL-NEXT: s_load_dword s14, s[4:5], 0x18
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB14_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB14_0:
+; GFX90a-GISEL-NEXT: s_and_b32 s0, s14, 0xffff
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_dword v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: preload_workgroup_size_z:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_and_b32 s0, s8, 0xffff
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: preload_workgroup_size_z:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_and_b32 s0, s8, 0xffff
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s0
+; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
%imp_arg_ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
%gep = getelementptr i8, ptr addrspace(4) %imp_arg_ptr, i32 16
%load = load i16, ptr addrspace(4) %gep
@@ -902,76 +1252,107 @@ define amdgpu_kernel void @preload_workgroup_size_z(ptr addrspace(1) inreg %out)
}
define amdgpu_kernel void @preload_workgroup_size_xyz(ptr addrspace(1) inreg %out) #0 {
-; GFX942-LABEL: preload_workgroup_size_xyz:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
-; GFX942-NEXT: s_load_dword s8, s[0:1], 0x18
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB15_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB15_0:
-; GFX942-NEXT: s_lshr_b32 s0, s7, 16
-; GFX942-NEXT: s_and_b32 s1, s7, 0xffff
-; GFX942-NEXT: s_and_b32 s4, s8, 0xffff
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, s1
-; GFX942-NEXT: v_mov_b32_e32 v1, s0
-; GFX942-NEXT: v_mov_b32_e32 v2, s4
-; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: preload_workgroup_size_xyz:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GFX90a-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
-; GFX90a-NEXT: s_load_dword s14, s[4:5], 0x18
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB15_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB15_0:
-; GFX90a-NEXT: s_lshr_b32 s0, s13, 16
-; GFX90a-NEXT: s_and_b32 s1, s13, 0xffff
-; GFX90a-NEXT: s_and_b32 s2, s14, 0xffff
-; GFX90a-NEXT: v_mov_b32_e32 v3, 0
-; GFX90a-NEXT: v_mov_b32_e32 v0, s1
-; GFX90a-NEXT: v_mov_b32_e32 v1, s0
-; GFX90a-NEXT: v_mov_b32_e32 v2, s2
-; GFX90a-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: preload_workgroup_size_xyz:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
-; GISEL-GFX90A-NEXT: s_load_dword s14, s[4:5], 0x18
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB15_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB15_0:
-; GISEL-GFX90A-NEXT: s_and_b32 s0, s13, 0xffff
-; GISEL-GFX90A-NEXT: s_lshr_b32 s1, s13, 16
-; GISEL-GFX90A-NEXT: s_and_b32 s2, s14, 0xffff
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, s1
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, s2
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v3, 0
-; GISEL-GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: preload_workgroup_size_xyz:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_lshr_b32 s0, s7, 16
-; GFX1250-NEXT: s_and_b32 s1, s7, 0xffff
-; GFX1250-NEXT: s_and_b32 s4, s8, 0xffff
-; GFX1250-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s1
-; GFX1250-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s4
-; GFX1250-NEXT: global_store_b96 v3, v[0:2], s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: preload_workgroup_size_xyz:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_load_dword s8, s[0:1], 0x18
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB15_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB15_0:
+; GFX942-SDAG-NEXT: s_lshr_b32 s0, s7, 16
+; GFX942-SDAG-NEXT: s_and_b32 s1, s7, 0xffff
+; GFX942-SDAG-NEXT: s_and_b32 s4, s8, 0xffff
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, s1
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, s4
+; GFX942-SDAG-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: preload_workgroup_size_xyz:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_load_dword s8, s[0:1], 0x18
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB15_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB15_0:
+; GFX942-GISEL-NEXT: s_and_b32 s4, s7, 0xffff
+; GFX942-GISEL-NEXT: s_lshr_b32 s5, s7, 16
+; GFX942-GISEL-NEXT: s_and_b32 s6, s8, 0xffff
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v2, s6
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: preload_workgroup_size_xyz:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
+; GFX90a-SDAG-NEXT: s_load_dword s14, s[4:5], 0x18
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB15_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB15_0:
+; GFX90a-SDAG-NEXT: s_lshr_b32 s0, s13, 16
+; GFX90a-SDAG-NEXT: s_and_b32 s1, s13, 0xffff
+; GFX90a-SDAG-NEXT: s_and_b32 s2, s14, 0xffff
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v3, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, s1
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v2, s2
+; GFX90a-SDAG-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: preload_workgroup_size_xyz:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
+; GFX90a-GISEL-NEXT: s_load_dword s14, s[4:5], 0x18
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB15_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB15_0:
+; GFX90a-GISEL-NEXT: s_and_b32 s0, s13, 0xffff
+; GFX90a-GISEL-NEXT: s_lshr_b32 s1, s13, 16
+; GFX90a-GISEL-NEXT: s_and_b32 s2, s14, 0xffff
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX90a-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: preload_workgroup_size_xyz:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_lshr_b32 s0, s7, 16
+; GFX1250-SDAG-NEXT: s_and_b32 s1, s7, 0xffff
+; GFX1250-SDAG-NEXT: s_and_b32 s4, s8, 0xffff
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s1
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s4
+; GFX1250-SDAG-NEXT: global_store_b96 v3, v[0:2], s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: preload_workgroup_size_xyz:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_and_b32 s4, s7, 0xffff
+; GFX1250-GISEL-NEXT: s_lshr_b32 s5, s7, 16
+; GFX1250-GISEL-NEXT: s_and_b32 s6, s8, 0xffff
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, 0
+; GFX1250-GISEL-NEXT: global_store_b96 v3, v[0:2], s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
%imp_arg_ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
%gep_x = getelementptr i8, ptr addrspace(4) %imp_arg_ptr, i32 12
%load_x = load i16, ptr addrspace(4) %gep_x
@@ -990,62 +1371,87 @@ define amdgpu_kernel void @preload_workgroup_size_xyz(ptr addrspace(1) inreg %ou
}
define amdgpu_kernel void @preload_remainder_x(ptr addrspace(1) inreg %out) #0 {
-; GFX942-LABEL: preload_remainder_x:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
-; GFX942-NEXT: s_load_dword s8, s[0:1], 0x18
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB16_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB16_0:
-; GFX942-NEXT: s_lshr_b32 s0, s8, 16
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s0
-; GFX942-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: preload_remainder_x:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GFX90a-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
-; GFX90a-NEXT: s_load_dword s14, s[4:5], 0x18
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB16_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB16_0:
-; GFX90a-NEXT: s_lshr_b32 s0, s14, 16
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s0
-; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: preload_remainder_x:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
-; GISEL-GFX90A-NEXT: s_load_dword s14, s[4:5], 0x18
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB16_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB16_0:
-; GISEL-GFX90A-NEXT: s_lshr_b32 s0, s14, 16
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: preload_remainder_x:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_lshr_b32 s0, s8, 16
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
-; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: preload_remainder_x:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_load_dword s8, s[0:1], 0x18
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB16_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB16_0:
+; GFX942-SDAG-NEXT: s_lshr_b32 s0, s8, 16
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: preload_remainder_x:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_load_dword s8, s[0:1], 0x18
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB16_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB16_0:
+; GFX942-GISEL-NEXT: s_lshr_b32 s0, s8, 16
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: preload_remainder_x:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
+; GFX90a-SDAG-NEXT: s_load_dword s14, s[4:5], 0x18
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB16_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB16_0:
+; GFX90a-SDAG-NEXT: s_lshr_b32 s0, s14, 16
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: preload_remainder_x:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
+; GFX90a-GISEL-NEXT: s_load_dword s14, s[4:5], 0x18
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB16_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB16_0:
+; GFX90a-GISEL-NEXT: s_lshr_b32 s0, s14, 16
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_dword v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: preload_remainder_x:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_lshr_b32 s0, s8, 16
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: preload_remainder_x:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_lshr_b32 s0, s8, 16
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s0
+; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
%imp_arg_ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
%gep = getelementptr i8, ptr addrspace(4) %imp_arg_ptr, i32 18
%load = load i16, ptr addrspace(4) %gep
@@ -1055,58 +1461,83 @@ define amdgpu_kernel void @preload_remainder_x(ptr addrspace(1) inreg %out) #0 {
}
define amdgpu_kernel void @preloadremainder_y(ptr addrspace(1) inreg %out) #0 {
-; GFX942-LABEL: preloadremainder_y:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
-; GFX942-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB17_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB17_0:
-; GFX942-NEXT: s_and_b32 s0, s9, 0xffff
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s0
-; GFX942-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: preloadremainder_y:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB17_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB17_0:
-; GFX90a-NEXT: s_and_b32 s0, s15, 0xffff
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s0
-; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: preloadremainder_y:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB17_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB17_0:
-; GISEL-GFX90A-NEXT: s_and_b32 s0, s15, 0xffff
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: preloadremainder_y:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_and_b32 s0, s9, 0xffff
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
-; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: preloadremainder_y:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB17_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB17_0:
+; GFX942-SDAG-NEXT: s_and_b32 s0, s9, 0xffff
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: preloadremainder_y:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB17_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB17_0:
+; GFX942-GISEL-NEXT: s_and_b32 s0, s9, 0xffff
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: preloadremainder_y:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB17_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB17_0:
+; GFX90a-SDAG-NEXT: s_and_b32 s0, s15, 0xffff
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: preloadremainder_y:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB17_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB17_0:
+; GFX90a-GISEL-NEXT: s_and_b32 s0, s15, 0xffff
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_dword v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: preloadremainder_y:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_and_b32 s0, s9, 0xffff
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: preloadremainder_y:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_and_b32 s0, s9, 0xffff
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s0
+; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
%imp_arg_ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
%gep = getelementptr i8, ptr addrspace(4) %imp_arg_ptr, i32 20
%load = load i16, ptr addrspace(4) %gep
@@ -1116,58 +1547,83 @@ define amdgpu_kernel void @preloadremainder_y(ptr addrspace(1) inreg %out) #0 {
}
define amdgpu_kernel void @preloadremainder_z(ptr addrspace(1) inreg %out) #0 {
-; GFX942-LABEL: preloadremainder_z:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
-; GFX942-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB18_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB18_0:
-; GFX942-NEXT: s_lshr_b32 s0, s9, 16
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s0
-; GFX942-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: preloadremainder_z:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB18_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB18_0:
-; GFX90a-NEXT: s_lshr_b32 s0, s15, 16
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s0
-; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: preloadremainder_z:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB18_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB18_0:
-; GISEL-GFX90A-NEXT: s_lshr_b32 s0, s15, 16
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: preloadremainder_z:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_lshr_b32 s0, s9, 16
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
-; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: preloadremainder_z:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB18_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB18_0:
+; GFX942-SDAG-NEXT: s_lshr_b32 s0, s9, 16
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: preloadremainder_z:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB18_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB18_0:
+; GFX942-GISEL-NEXT: s_lshr_b32 s0, s9, 16
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: preloadremainder_z:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB18_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB18_0:
+; GFX90a-SDAG-NEXT: s_lshr_b32 s0, s15, 16
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: preloadremainder_z:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB18_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB18_0:
+; GFX90a-GISEL-NEXT: s_lshr_b32 s0, s15, 16
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_dword v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: preloadremainder_z:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_lshr_b32 s0, s9, 16
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: preloadremainder_z:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_lshr_b32 s0, s9, 16
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s0
+; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
%imp_arg_ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
%gep = getelementptr i8, ptr addrspace(4) %imp_arg_ptr, i32 22
%load = load i16, ptr addrspace(4) %gep
@@ -1177,72 +1633,104 @@ define amdgpu_kernel void @preloadremainder_z(ptr addrspace(1) inreg %out) #0 {
}
define amdgpu_kernel void @preloadremainder_xyz(ptr addrspace(1) inreg %out) #0 {
-; GFX942-LABEL: preloadremainder_xyz:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
-; GFX942-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB19_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB19_0:
-; GFX942-NEXT: s_lshr_b32 s0, s9, 16
-; GFX942-NEXT: s_lshr_b32 s1, s8, 16
-; GFX942-NEXT: s_and_b32 s4, s9, 0xffff
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, s1
-; GFX942-NEXT: v_mov_b32_e32 v1, s4
-; GFX942-NEXT: v_mov_b32_e32 v2, s0
-; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: preloadremainder_xyz:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB19_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB19_0:
-; GFX90a-NEXT: s_lshr_b32 s0, s15, 16
-; GFX90a-NEXT: s_lshr_b32 s1, s14, 16
-; GFX90a-NEXT: s_and_b32 s2, s15, 0xffff
-; GFX90a-NEXT: v_mov_b32_e32 v3, 0
-; GFX90a-NEXT: v_mov_b32_e32 v0, s1
-; GFX90a-NEXT: v_mov_b32_e32 v1, s2
-; GFX90a-NEXT: v_mov_b32_e32 v2, s0
-; GFX90a-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: preloadremainder_xyz:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB19_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB19_0:
-; GISEL-GFX90A-NEXT: s_lshr_b32 s0, s14, 16
-; GISEL-GFX90A-NEXT: s_lshr_b32 s2, s15, 16
-; GISEL-GFX90A-NEXT: s_and_b32 s1, s15, 0xffff
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, s1
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, s2
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v3, 0
-; GISEL-GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: preloadremainder_xyz:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_lshr_b32 s0, s9, 16
-; GFX1250-NEXT: s_lshr_b32 s1, s8, 16
-; GFX1250-NEXT: s_and_b32 s4, s9, 0xffff
-; GFX1250-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s1
-; GFX1250-NEXT: v_dual_mov_b32 v1, s4 :: v_dual_mov_b32 v2, s0
-; GFX1250-NEXT: global_store_b96 v3, v[0:2], s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: preloadremainder_xyz:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB19_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB19_0:
+; GFX942-SDAG-NEXT: s_lshr_b32 s0, s9, 16
+; GFX942-SDAG-NEXT: s_lshr_b32 s1, s8, 16
+; GFX942-SDAG-NEXT: s_and_b32 s4, s9, 0xffff
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, s1
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s4
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, s0
+; GFX942-SDAG-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: preloadremainder_xyz:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB19_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB19_0:
+; GFX942-GISEL-NEXT: s_lshr_b32 s4, s8, 16
+; GFX942-GISEL-NEXT: s_lshr_b32 s6, s9, 16
+; GFX942-GISEL-NEXT: s_and_b32 s5, s9, 0xffff
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v2, s6
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: preloadremainder_xyz:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB19_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB19_0:
+; GFX90a-SDAG-NEXT: s_lshr_b32 s0, s15, 16
+; GFX90a-SDAG-NEXT: s_lshr_b32 s1, s14, 16
+; GFX90a-SDAG-NEXT: s_and_b32 s2, s15, 0xffff
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v3, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, s1
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s2
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v2, s0
+; GFX90a-SDAG-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: preloadremainder_xyz:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB19_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB19_0:
+; GFX90a-GISEL-NEXT: s_lshr_b32 s0, s14, 16
+; GFX90a-GISEL-NEXT: s_lshr_b32 s2, s15, 16
+; GFX90a-GISEL-NEXT: s_and_b32 s1, s15, 0xffff
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX90a-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: preloadremainder_xyz:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_lshr_b32 s0, s9, 16
+; GFX1250-SDAG-NEXT: s_lshr_b32 s1, s8, 16
+; GFX1250-SDAG-NEXT: s_and_b32 s4, s9, 0xffff
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s1
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v1, s4 :: v_dual_mov_b32 v2, s0
+; GFX1250-SDAG-NEXT: global_store_b96 v3, v[0:2], s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: preloadremainder_xyz:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_lshr_b32 s4, s8, 16
+; GFX1250-GISEL-NEXT: s_lshr_b32 s6, s9, 16
+; GFX1250-GISEL-NEXT: s_and_b32 s5, s9, 0xffff
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, 0
+; GFX1250-GISEL-NEXT: global_store_b96 v3, v[0:2], s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
%imp_arg_ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
%gep_x = getelementptr i8, ptr addrspace(4) %imp_arg_ptr, i32 18
%load_x = load i16, ptr addrspace(4) %gep_x
@@ -1261,60 +1749,83 @@ define amdgpu_kernel void @preloadremainder_xyz(ptr addrspace(1) inreg %out) #0
}
define amdgpu_kernel void @no_free_sgprs_preloadremainder_z(ptr addrspace(1) inreg %out) {
-; GFX942-LABEL: no_free_sgprs_preloadremainder_z:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB20_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB20_0:
-; GFX942-NEXT: s_lshr_b32 s0, s15, 16
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s0
-; GFX942-NEXT: global_store_dword v0, v1, s[8:9]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: no_free_sgprs_preloadremainder_z:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx2 s[14:15], s[8:9], 0x0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB20_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB20_0:
-; GFX90a-NEXT: s_load_dword s0, s[8:9], 0x1c
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_lshr_b32 s0, s0, 16
-; GFX90a-NEXT: v_mov_b32_e32 v1, s0
-; GFX90a-NEXT: global_store_dword v0, v1, s[14:15]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: no_free_sgprs_preloadremainder_z:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[14:15], s[8:9], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB20_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB20_0:
-; GISEL-GFX90A-NEXT: s_load_dword s0, s[8:9], 0x1c
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_lshr_b32 s0, s0, 16
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[14:15]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: no_free_sgprs_preloadremainder_z:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_lshr_b32 s0, s15, 16
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
-; GFX1250-NEXT: global_store_b32 v0, v1, s[8:9]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: no_free_sgprs_preloadremainder_z:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB20_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB20_0:
+; GFX942-SDAG-NEXT: s_lshr_b32 s0, s15, 16
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[8:9]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: no_free_sgprs_preloadremainder_z:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB20_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB20_0:
+; GFX942-GISEL-NEXT: s_lshr_b32 s0, s15, 16
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_dword v1, v0, s[8:9]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: no_free_sgprs_preloadremainder_z:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[14:15], s[8:9], 0x0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB20_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB20_0:
+; GFX90a-SDAG-NEXT: s_load_dword s0, s[8:9], 0x1c
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_lshr_b32 s0, s0, 16
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[14:15]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: no_free_sgprs_preloadremainder_z:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[14:15], s[8:9], 0x0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB20_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB20_0:
+; GFX90a-GISEL-NEXT: s_load_dword s0, s[8:9], 0x1c
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_lshr_b32 s0, s0, 16
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: global_store_dword v1, v0, s[14:15]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: no_free_sgprs_preloadremainder_z:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_lshr_b32 s0, s15, 16
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[8:9]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: no_free_sgprs_preloadremainder_z:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_lshr_b32 s0, s15, 16
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s0
+; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[8:9]
+; GFX1250-GISEL-NEXT: s_endpgm
%imp_arg_ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
%gep = getelementptr i8, ptr addrspace(4) %imp_arg_ptr, i32 22
%load = load i16, ptr addrspace(4) %gep
@@ -1326,57 +1837,79 @@ define amdgpu_kernel void @no_free_sgprs_preloadremainder_z(ptr addrspace(1) inr
; Check for consistency between isel and earlier passes preload SGPR accounting with max preload SGPRs.
define amdgpu_kernel void @preload_block_max_user_sgprs(ptr addrspace(1) inreg %out, i192 inreg %t0, i32 inreg %t1) #0 {
-; GFX942-LABEL: preload_block_max_user_sgprs:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x8
-; GFX942-NEXT: s_load_dword s12, s[0:1], 0x28
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB21_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB21_0:
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s12
-; GFX942-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: preload_block_max_user_sgprs:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB21_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB21_0:
-; GFX90a-NEXT: s_load_dword s0, s[4:5], 0x28
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: v_mov_b32_e32 v1, s0
-; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: preload_block_max_user_sgprs:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB21_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB21_0:
-; GISEL-GFX90A-NEXT: s_load_dword s0, s[4:5], 0x28
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: preload_block_max_user_sgprs:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s12
-; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: preload_block_max_user_sgprs:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_load_dword s12, s[0:1], 0x28
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB21_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB21_0:
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s12
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: preload_block_max_user_sgprs:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_load_dword s12, s[0:1], 0x28
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB21_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB21_0:
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s12
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: preload_block_max_user_sgprs:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB21_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB21_0:
+; GFX90a-SDAG-NEXT: s_load_dword s0, s[4:5], 0x28
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: preload_block_max_user_sgprs:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB21_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB21_0:
+; GFX90a-GISEL-NEXT: s_load_dword s0, s[4:5], 0x28
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: global_store_dword v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: preload_block_max_user_sgprs:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s12
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: preload_block_max_user_sgprs:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, 0
+; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
%imp_arg_ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
%load = load i32, ptr addrspace(4) %imp_arg_ptr
store i32 %load, ptr addrspace(1) %out
@@ -1384,69 +1917,101 @@ define amdgpu_kernel void @preload_block_max_user_sgprs(ptr addrspace(1) inreg %
}
define amdgpu_kernel void @preload_block_count_z_workgroup_size_z_remainder_z(ptr addrspace(1) inreg %out) #0 {
-; GFX942-LABEL: preload_block_count_z_workgroup_size_z_remainder_z:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
-; GFX942-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB22_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB22_0:
-; GFX942-NEXT: s_lshr_b32 s0, s9, 16
-; GFX942-NEXT: s_and_b32 s1, s8, 0xffff
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, s6
-; GFX942-NEXT: v_mov_b32_e32 v1, s1
-; GFX942-NEXT: v_mov_b32_e32 v2, s0
-; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: preload_block_count_z_workgroup_size_z_remainder_z:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB22_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB22_0:
-; GFX90a-NEXT: s_lshr_b32 s0, s15, 16
-; GFX90a-NEXT: s_and_b32 s1, s14, 0xffff
-; GFX90a-NEXT: v_mov_b32_e32 v3, 0
-; GFX90a-NEXT: v_mov_b32_e32 v0, s12
-; GFX90a-NEXT: v_mov_b32_e32 v1, s1
-; GFX90a-NEXT: v_mov_b32_e32 v2, s0
-; GFX90a-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: preload_block_count_z_workgroup_size_z_remainder_z:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB22_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB22_0:
-; GISEL-GFX90A-NEXT: s_mov_b32 s0, s14
-; GISEL-GFX90A-NEXT: s_lshr_b32 s14, s15, 16
-; GISEL-GFX90A-NEXT: s_and_b32 s13, s0, 0xffff
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s12
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, s13
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, s14
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v3, 0
-; GISEL-GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: preload_block_count_z_workgroup_size_z_remainder_z:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_lshr_b32 s0, s9, 16
-; GFX1250-NEXT: s_and_b32 s1, s8, 0xffff
-; GFX1250-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s6
-; GFX1250-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s0
-; GFX1250-NEXT: global_store_b96 v3, v[0:2], s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: preload_block_count_z_workgroup_size_z_remainder_z:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB22_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB22_0:
+; GFX942-SDAG-NEXT: s_lshr_b32 s0, s9, 16
+; GFX942-SDAG-NEXT: s_and_b32 s1, s8, 0xffff
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, s6
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, s0
+; GFX942-SDAG-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: preload_block_count_z_workgroup_size_z_remainder_z:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB22_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB22_0:
+; GFX942-GISEL-NEXT: s_mov_b32 s4, s6
+; GFX942-GISEL-NEXT: s_lshr_b32 s6, s9, 16
+; GFX942-GISEL-NEXT: s_and_b32 s5, s8, 0xffff
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v2, s6
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: preload_block_count_z_workgroup_size_z_remainder_z:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB22_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB22_0:
+; GFX90a-SDAG-NEXT: s_lshr_b32 s0, s15, 16
+; GFX90a-SDAG-NEXT: s_and_b32 s1, s14, 0xffff
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v3, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, s12
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v2, s0
+; GFX90a-SDAG-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: preload_block_count_z_workgroup_size_z_remainder_z:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB22_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB22_0:
+; GFX90a-GISEL-NEXT: s_mov_b32 s0, s14
+; GFX90a-GISEL-NEXT: s_lshr_b32 s14, s15, 16
+; GFX90a-GISEL-NEXT: s_and_b32 s13, s0, 0xffff
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s12
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, s13
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v2, s14
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX90a-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: preload_block_count_z_workgroup_size_z_remainder_z:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_lshr_b32 s0, s9, 16
+; GFX1250-SDAG-NEXT: s_and_b32 s1, s8, 0xffff
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s6
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s0
+; GFX1250-SDAG-NEXT: global_store_b96 v3, v[0:2], s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: preload_block_count_z_workgroup_size_z_remainder_z:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b32 s4, s6
+; GFX1250-GISEL-NEXT: s_lshr_b32 s6, s9, 16
+; GFX1250-GISEL-NEXT: s_and_b32 s5, s8, 0xffff
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, 0
+; GFX1250-GISEL-NEXT: global_store_b96 v3, v[0:2], s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
%imp_arg_ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
%gep0 = getelementptr i8, ptr addrspace(4) %imp_arg_ptr, i32 8
%gep1 = getelementptr i8, ptr addrspace(4) %imp_arg_ptr, i32 16
@@ -1482,61 +2047,75 @@ define amdgpu_kernel void @preload_block_count_x_no_explicit_args() local_unname
; GFX942-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX942-NEXT: s_endpgm
;
-; GFX90a-LABEL: preload_block_count_x_no_explicit_args:
-; GFX90a: ; %bb.3:
-; GFX90a-NEXT: s_load_dword s8, s[4:5], 0x0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB23_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.4:
-; GFX90a-NEXT: .LBB23_0: ; %entry
-; GFX90a-NEXT: s_add_u32 flat_scratch_lo, s6, s12
-; GFX90a-NEXT: s_addc_u32 flat_scratch_hi, s7, 0
-; GFX90a-NEXT: s_cmp_lg_u32 s8, 0
-; GFX90a-NEXT: s_cbranch_scc0 .LBB23_2
-; GFX90a-NEXT: ; %bb.1: ; %ret
-; GFX90a-NEXT: s_endpgm
-; GFX90a-NEXT: .LBB23_2: ; %store
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, v0
-; GFX90a-NEXT: v_mov_b32_e32 v2, 32
-; GFX90a-NEXT: v_mov_b32_e32 v3, 0
-; GFX90a-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: preload_block_count_x_no_explicit_args:
-; GISEL-GFX90A: ; %bb.3:
-; GISEL-GFX90A-NEXT: s_load_dword s8, s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB23_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.4:
-; GISEL-GFX90A-NEXT: .LBB23_0: ; %entry
-; GISEL-GFX90A-NEXT: s_add_u32 flat_scratch_lo, s6, s12
-; GISEL-GFX90A-NEXT: s_addc_u32 flat_scratch_hi, s7, 0
-; GISEL-GFX90A-NEXT: s_cmp_lg_u32 s8, 0
-; GISEL-GFX90A-NEXT: s_cbranch_scc0 .LBB23_2
-; GISEL-GFX90A-NEXT: ; %bb.1: ; %ret
-; GISEL-GFX90A-NEXT: s_endpgm
-; GISEL-GFX90A-NEXT: .LBB23_2: ; %store
-; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[0:1], 0, 0
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, 32
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v3, 0
-; GISEL-GFX90A-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: preload_block_count_x_no_explicit_args:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_cmp_lg_u32 s2, 0
-; GFX1250-NEXT: s_cbranch_scc0 .LBB23_2
-; GFX1250-NEXT: ; %bb.1: ; %ret
-; GFX1250-NEXT: s_endpgm
-; GFX1250-NEXT: .LBB23_2: ; %store
-; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 0
-; GFX1250-NEXT: v_mov_b64_e32 v[2:3], 32
-; GFX1250-NEXT: flat_store_b64 v[2:3], v[0:1]
-; GFX1250-NEXT: s_endpgm
+; GFX90a-SDAG-LABEL: preload_block_count_x_no_explicit_args:
+; GFX90a-SDAG: ; %bb.3:
+; GFX90a-SDAG-NEXT: s_load_dword s8, s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB23_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.4:
+; GFX90a-SDAG-NEXT: .LBB23_0: ; %entry
+; GFX90a-SDAG-NEXT: s_add_u32 flat_scratch_lo, s6, s12
+; GFX90a-SDAG-NEXT: s_addc_u32 flat_scratch_hi, s7, 0
+; GFX90a-SDAG-NEXT: s_cmp_lg_u32 s8, 0
+; GFX90a-SDAG-NEXT: s_cbranch_scc0 .LBB23_2
+; GFX90a-SDAG-NEXT: ; %bb.1: ; %ret
+; GFX90a-SDAG-NEXT: s_endpgm
+; GFX90a-SDAG-NEXT: .LBB23_2: ; %store
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, v0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v2, 32
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v3, 0
+; GFX90a-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: preload_block_count_x_no_explicit_args:
+; GFX90a-GISEL: ; %bb.3:
+; GFX90a-GISEL-NEXT: s_load_dword s8, s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB23_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.4:
+; GFX90a-GISEL-NEXT: .LBB23_0: ; %entry
+; GFX90a-GISEL-NEXT: s_add_u32 flat_scratch_lo, s6, s12
+; GFX90a-GISEL-NEXT: s_addc_u32 flat_scratch_hi, s7, 0
+; GFX90a-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; GFX90a-GISEL-NEXT: s_cbranch_scc0 .LBB23_2
+; GFX90a-GISEL-NEXT: ; %bb.1: ; %ret
+; GFX90a-GISEL-NEXT: s_endpgm
+; GFX90a-GISEL-NEXT: .LBB23_2: ; %store
+; GFX90a-GISEL-NEXT: v_pk_mov_b32 v[0:1], 0, 0
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v2, 32
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX90a-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: preload_block_count_x_no_explicit_args:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1250-SDAG-NEXT: s_cbranch_scc0 .LBB23_2
+; GFX1250-SDAG-NEXT: ; %bb.1: ; %ret
+; GFX1250-SDAG-NEXT: s_endpgm
+; GFX1250-SDAG-NEXT: .LBB23_2: ; %store
+; GFX1250-SDAG-NEXT: v_mov_b64_e32 v[0:1], 0
+; GFX1250-SDAG-NEXT: v_mov_b64_e32 v[2:3], 32
+; GFX1250-SDAG-NEXT: flat_store_b64 v[2:3], v[0:1]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: preload_block_count_x_no_explicit_args:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1250-GISEL-NEXT: s_cbranch_scc0 .LBB23_2
+; GFX1250-GISEL-NEXT: ; %bb.1: ; %ret
+; GFX1250-GISEL-NEXT: s_endpgm
+; GFX1250-GISEL-NEXT: .LBB23_2: ; %store
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], 0
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250-GISEL-NEXT: s_mov_b64 s[0:1], 32
+; GFX1250-GISEL-NEXT: flat_store_b64 v2, v[0:1], s[0:1]
+; GFX1250-GISEL-NEXT: s_endpgm
entry:
%imp_arg_ptr = tail call dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
%load = load i32, ptr addrspace(4) %imp_arg_ptr, align 4
@@ -1552,3 +2131,7 @@ ret:
}
attributes #0 = { "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX1250-FAKE16: {{.*}}
+; GFX1250-REAL16: {{.*}}
+; GFX90a: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/preload-kernargs.ll b/llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
index 7833f163ead4d..8d2ea415829a4 100644
--- a/llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
+++ b/llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
@@ -1,362 +1,511 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX942 %s
-; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX90a %s
-; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefixes=GISEL-GFX90A %s
-; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250 %s
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX942,GFX942-SDAG %s
+; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX942,GFX942-GISEL %s
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX90a,GFX90a-SDAG %s
+; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX90a,GFX90a-GISEL %s
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s
+; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s
define amdgpu_kernel void @ptr1_i8(ptr addrspace(1) inreg %out, i8 inreg %arg0) #0 {
-; GFX942-LABEL: ptr1_i8:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dword s4, s[0:1], 0x8
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB0_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB0_0:
-; GFX942-NEXT: s_and_b32 s0, s4, 0xff
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s0
-; GFX942-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: ptr1_i8:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x8
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB0_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB0_0:
-; GFX90a-NEXT: s_and_b32 s0, s10, 0xff
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s0
-; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: ptr1_i8:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_load_dword s10, s[4:5], 0x8
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB0_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB0_0:
-; GISEL-GFX90A-NEXT: s_and_b32 s0, s10, 0xff
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: ptr1_i8:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_and_b32 s0, s4, 0xff
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
-; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: ptr1_i8:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dword s4, s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB0_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB0_0:
+; GFX942-SDAG-NEXT: s_and_b32 s0, s4, 0xff
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: ptr1_i8:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dword s4, s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB0_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB0_0:
+; GFX942-GISEL-NEXT: s_and_b32 s0, s4, 0xff
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: ptr1_i8:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_load_dword s10, s[4:5], 0x8
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB0_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB0_0:
+; GFX90a-SDAG-NEXT: s_and_b32 s0, s10, 0xff
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: ptr1_i8:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_load_dword s10, s[4:5], 0x8
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB0_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB0_0:
+; GFX90a-GISEL-NEXT: s_and_b32 s0, s10, 0xff
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_dword v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: ptr1_i8:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_and_b32 s0, s4, 0xff
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: ptr1_i8:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_and_b32 s0, s4, 0xff
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s0
+; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
%ext = zext i8 %arg0 to i32
store i32 %ext, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @ptr1_i8_zext_arg(ptr addrspace(1) inreg %out, i8 zeroext inreg %arg0) #0 {
-; GFX942-LABEL: ptr1_i8_zext_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dword s4, s[0:1], 0x8
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB1_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB1_0:
-; GFX942-NEXT: s_and_b32 s0, s4, 0xff
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s0
-; GFX942-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: ptr1_i8_zext_arg:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x8
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB1_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB1_0:
-; GFX90a-NEXT: s_and_b32 s0, s10, 0xff
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s0
-; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: ptr1_i8_zext_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_load_dword s10, s[4:5], 0x8
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB1_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB1_0:
-; GISEL-GFX90A-NEXT: s_and_b32 s0, s10, 0xff
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: ptr1_i8_zext_arg:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_and_b32 s0, s4, 0xff
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
-; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: ptr1_i8_zext_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dword s4, s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB1_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB1_0:
+; GFX942-SDAG-NEXT: s_and_b32 s0, s4, 0xff
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: ptr1_i8_zext_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dword s4, s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB1_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB1_0:
+; GFX942-GISEL-NEXT: s_and_b32 s0, s4, 0xff
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: ptr1_i8_zext_arg:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_load_dword s10, s[4:5], 0x8
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB1_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB1_0:
+; GFX90a-SDAG-NEXT: s_and_b32 s0, s10, 0xff
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: ptr1_i8_zext_arg:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_load_dword s10, s[4:5], 0x8
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB1_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB1_0:
+; GFX90a-GISEL-NEXT: s_and_b32 s0, s10, 0xff
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_dword v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: ptr1_i8_zext_arg:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_and_b32 s0, s4, 0xff
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: ptr1_i8_zext_arg:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_and_b32 s0, s4, 0xff
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s0
+; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
%ext = zext i8 %arg0 to i32
store i32 %ext, ptr addrspace(1) %out, align 4
ret void
}
define amdgpu_kernel void @ptr1_i16_preload_arg(ptr addrspace(1) inreg %out, i16 inreg %arg0) #0 {
-; GFX942-LABEL: ptr1_i16_preload_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dword s4, s[0:1], 0x8
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB2_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB2_0:
-; GFX942-NEXT: s_and_b32 s0, s4, 0xffff
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s0
-; GFX942-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: ptr1_i16_preload_arg:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x8
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB2_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB2_0:
-; GFX90a-NEXT: s_and_b32 s0, s10, 0xffff
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s0
-; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: ptr1_i16_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_load_dword s10, s[4:5], 0x8
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB2_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB2_0:
-; GISEL-GFX90A-NEXT: s_and_b32 s0, s10, 0xffff
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: ptr1_i16_preload_arg:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_and_b32 s0, s4, 0xffff
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
-; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: ptr1_i16_preload_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dword s4, s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB2_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB2_0:
+; GFX942-SDAG-NEXT: s_and_b32 s0, s4, 0xffff
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: ptr1_i16_preload_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dword s4, s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB2_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB2_0:
+; GFX942-GISEL-NEXT: s_and_b32 s0, s4, 0xffff
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: ptr1_i16_preload_arg:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_load_dword s10, s[4:5], 0x8
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB2_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB2_0:
+; GFX90a-SDAG-NEXT: s_and_b32 s0, s10, 0xffff
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: ptr1_i16_preload_arg:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_load_dword s10, s[4:5], 0x8
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB2_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB2_0:
+; GFX90a-GISEL-NEXT: s_and_b32 s0, s10, 0xffff
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_dword v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: ptr1_i16_preload_arg:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_and_b32 s0, s4, 0xffff
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: ptr1_i16_preload_arg:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_and_b32 s0, s4, 0xffff
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s0
+; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
%ext = zext i16 %arg0 to i32
store i32 %ext, ptr addrspace(1) %out, align 4
ret void
}
define amdgpu_kernel void @ptr1_i32_preload_arg(ptr addrspace(1) inreg %out, i32 inreg %arg0) #0 {
-; GFX942-LABEL: ptr1_i32_preload_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dword s4, s[0:1], 0x8
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB3_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB3_0:
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s4
-; GFX942-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: ptr1_i32_preload_arg:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x8
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB3_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB3_0:
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s10
-; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: ptr1_i32_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_load_dword s10, s[4:5], 0x8
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB3_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB3_0:
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: ptr1_i32_preload_arg:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
-; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: ptr1_i32_preload_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dword s4, s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB3_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB3_0:
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s4
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: ptr1_i32_preload_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dword s4, s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB3_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB3_0:
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: ptr1_i32_preload_arg:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_load_dword s10, s[4:5], 0x8
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB3_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB3_0:
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s10
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: ptr1_i32_preload_arg:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_load_dword s10, s[4:5], 0x8
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB3_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB3_0:
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s10
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_dword v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: ptr1_i32_preload_arg:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: ptr1_i32_preload_arg:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, 0
+; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
store i32 %arg0, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @i32_ptr1_i32_preload_arg(i32 inreg %arg0, ptr addrspace(1) inreg %out, i32 inreg %arg1) #0 {
-; GFX942-LABEL: i32_ptr1_i32_preload_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
-; GFX942-NEXT: s_load_dword s6, s[0:1], 0x10
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB4_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB4_0:
-; GFX942-NEXT: s_add_i32 s0, s2, s6
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s0
-; GFX942-NEXT: global_store_dword v0, v1, s[4:5]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: i32_ptr1_i32_preload_arg:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GFX90a-NEXT: s_load_dword s12, s[4:5], 0x10
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB4_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB4_0:
-; GFX90a-NEXT: s_add_i32 s0, s8, s12
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s0
-; GFX90a-NEXT: global_store_dword v0, v1, s[10:11]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: i32_ptr1_i32_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_load_dword s12, s[4:5], 0x10
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB4_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB4_0:
-; GISEL-GFX90A-NEXT: s_add_i32 s0, s8, s12
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[10:11]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: i32_ptr1_i32_preload_arg:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_add_co_i32 s0, s2, s6
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
-; GFX1250-NEXT: global_store_b32 v0, v1, s[4:5]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: i32_ptr1_i32_preload_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_load_dword s6, s[0:1], 0x10
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB4_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB4_0:
+; GFX942-SDAG-NEXT: s_add_i32 s0, s2, s6
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[4:5]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: i32_ptr1_i32_preload_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_load_dword s6, s[0:1], 0x10
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB4_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB4_0:
+; GFX942-GISEL-NEXT: s_add_i32 s0, s2, s6
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_dword v1, v0, s[4:5]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: i32_ptr1_i32_preload_arg:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_load_dword s12, s[4:5], 0x10
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB4_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB4_0:
+; GFX90a-SDAG-NEXT: s_add_i32 s0, s8, s12
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[10:11]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: i32_ptr1_i32_preload_arg:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_load_dword s12, s[4:5], 0x10
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB4_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB4_0:
+; GFX90a-GISEL-NEXT: s_add_i32 s0, s8, s12
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_dword v1, v0, s[10:11]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: i32_ptr1_i32_preload_arg:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_add_co_i32 s0, s2, s6
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[4:5]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: i32_ptr1_i32_preload_arg:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_add_co_i32 s0, s2, s6
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s0
+; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[4:5]
+; GFX1250-GISEL-NEXT: s_endpgm
%add = add i32 %arg0, %arg1
store i32 %add, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @ptr1_i16_i16_preload_arg(ptr addrspace(1) inreg %out, i16 inreg %arg0, i16 inreg %arg1) #0 {
-; GFX942-LABEL: ptr1_i16_i16_preload_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dword s4, s[0:1], 0x8
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB5_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB5_0:
-; GFX942-NEXT: s_lshr_b32 s0, s4, 16
-; GFX942-NEXT: s_and_b32 s1, s4, 0xffff
-; GFX942-NEXT: s_add_i32 s0, s1, s0
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s0
-; GFX942-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: ptr1_i16_i16_preload_arg:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x8
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB5_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB5_0:
-; GFX90a-NEXT: s_lshr_b32 s0, s10, 16
-; GFX90a-NEXT: s_and_b32 s1, s10, 0xffff
-; GFX90a-NEXT: s_add_i32 s0, s1, s0
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s0
-; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: ptr1_i16_i16_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_load_dword s10, s[4:5], 0x8
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB5_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB5_0:
-; GISEL-GFX90A-NEXT: s_lshr_b32 s0, s10, 16
-; GISEL-GFX90A-NEXT: s_and_b32 s1, s10, 0xffff
-; GISEL-GFX90A-NEXT: s_add_i32 s0, s1, s0
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: ptr1_i16_i16_preload_arg:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_lshr_b32 s0, s4, 16
-; GFX1250-NEXT: s_and_b32 s1, s4, 0xffff
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_add_co_i32 s0, s1, s0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
-; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: ptr1_i16_i16_preload_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dword s4, s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB5_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB5_0:
+; GFX942-SDAG-NEXT: s_lshr_b32 s0, s4, 16
+; GFX942-SDAG-NEXT: s_and_b32 s1, s4, 0xffff
+; GFX942-SDAG-NEXT: s_add_i32 s0, s1, s0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: ptr1_i16_i16_preload_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dword s4, s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB5_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB5_0:
+; GFX942-GISEL-NEXT: s_lshr_b32 s0, s4, 16
+; GFX942-GISEL-NEXT: s_and_b32 s1, s4, 0xffff
+; GFX942-GISEL-NEXT: s_add_i32 s0, s1, s0
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: ptr1_i16_i16_preload_arg:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_load_dword s10, s[4:5], 0x8
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB5_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB5_0:
+; GFX90a-SDAG-NEXT: s_lshr_b32 s0, s10, 16
+; GFX90a-SDAG-NEXT: s_and_b32 s1, s10, 0xffff
+; GFX90a-SDAG-NEXT: s_add_i32 s0, s1, s0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: ptr1_i16_i16_preload_arg:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_load_dword s10, s[4:5], 0x8
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB5_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB5_0:
+; GFX90a-GISEL-NEXT: s_lshr_b32 s0, s10, 16
+; GFX90a-GISEL-NEXT: s_and_b32 s1, s10, 0xffff
+; GFX90a-GISEL-NEXT: s_add_i32 s0, s1, s0
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_dword v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: ptr1_i16_i16_preload_arg:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_lshr_b32 s0, s4, 16
+; GFX1250-SDAG-NEXT: s_and_b32 s1, s4, 0xffff
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1250-SDAG-NEXT: s_add_co_i32 s0, s1, s0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: ptr1_i16_i16_preload_arg:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_lshr_b32 s0, s4, 16
+; GFX1250-GISEL-NEXT: s_and_b32 s1, s4, 0xffff
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1250-GISEL-NEXT: s_add_co_i32 s0, s1, s0
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
%ext = zext i16 %arg0 to i32
%ext1 = zext i16 %arg1 to i32
%add = add i32 %ext, %ext1
@@ -365,54 +514,76 @@ define amdgpu_kernel void @ptr1_i16_i16_preload_arg(ptr addrspace(1) inreg %out,
}
define amdgpu_kernel void @ptr1_v2i8_preload_arg(ptr addrspace(1) inreg %out, <2 x i8> inreg %in) #0 {
-; GFX942-LABEL: ptr1_v2i8_preload_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dword s4, s[0:1], 0x8
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB6_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB6_0:
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s4
-; GFX942-NEXT: global_store_short v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: ptr1_v2i8_preload_arg:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x8
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB6_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB6_0:
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s10
-; GFX90a-NEXT: global_store_short v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: ptr1_v2i8_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_load_dword s10, s[4:5], 0x8
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB6_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB6_0:
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: ptr1_v2i8_preload_arg:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
-; GFX1250-NEXT: global_store_b16 v0, v1, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: ptr1_v2i8_preload_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dword s4, s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB6_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB6_0:
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s4
+; GFX942-SDAG-NEXT: global_store_short v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: ptr1_v2i8_preload_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dword s4, s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB6_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB6_0:
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: ptr1_v2i8_preload_arg:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_load_dword s10, s[4:5], 0x8
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB6_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB6_0:
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s10
+; GFX90a-SDAG-NEXT: global_store_short v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: ptr1_v2i8_preload_arg:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_load_dword s10, s[4:5], 0x8
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB6_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB6_0:
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s10
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: ptr1_v2i8_preload_arg:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
+; GFX1250-SDAG-NEXT: global_store_b16 v0, v1, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: ptr1_v2i8_preload_arg:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v0.l, s4
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1250-GISEL-NEXT: global_store_b16 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
store <2 x i8> %in, ptr addrspace(1) %out
ret void
}
@@ -457,25 +628,6 @@ define amdgpu_kernel void @byref_preload_arg(ptr addrspace(1) inreg %out, ptr ad
; GFX90a-NEXT: s_waitcnt vmcnt(0)
; GFX90a-NEXT: s_endpgm
;
-; GISEL-GFX90A-LABEL: byref_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB7_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB7_0:
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x100
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, 0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, s0
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, s1
-; GISEL-GFX90A-NEXT: global_store_dword v0, v1, s[8:9]
-; GISEL-GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GISEL-GFX90A-NEXT: global_store_dword v0, v2, s[8:9]
-; GISEL-GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GISEL-GFX90A-NEXT: s_endpgm
-;
; GFX1250-LABEL: byref_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -536,25 +688,6 @@ define amdgpu_kernel void @byref_staggered_preload_arg(ptr addrspace(1) inreg %o
; GFX90a-NEXT: s_waitcnt vmcnt(0)
; GFX90a-NEXT: s_endpgm
;
-; GISEL-GFX90A-LABEL: byref_staggered_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB8_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB8_0:
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x100
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, 0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, s0
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, s1
-; GISEL-GFX90A-NEXT: global_store_dword v0, v1, s[8:9]
-; GISEL-GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GISEL-GFX90A-NEXT: global_store_dword v0, v2, s[8:9]
-; GISEL-GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GISEL-GFX90A-NEXT: s_endpgm
-;
; GFX1250-LABEL: byref_staggered_preload_arg:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
@@ -576,169 +709,262 @@ define amdgpu_kernel void @byref_staggered_preload_arg(ptr addrspace(1) inreg %o
define amdgpu_kernel void @v8i32_arg(ptr addrspace(1) nocapture inreg %out, <8 x i32> inreg %in) #0 {
-; GFX942-LABEL: v8i32_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB9_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB9_0:
-; GFX942-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x20
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: v_mov_b32_e32 v0, s8
-; GFX942-NEXT: v_mov_b32_e32 v1, s9
-; GFX942-NEXT: v_mov_b32_e32 v2, s10
-; GFX942-NEXT: v_mov_b32_e32 v3, s11
-; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] offset:16
-; GFX942-NEXT: s_nop 1
-; GFX942-NEXT: v_mov_b32_e32 v0, s4
-; GFX942-NEXT: v_mov_b32_e32 v1, s5
-; GFX942-NEXT: v_mov_b32_e32 v2, s6
-; GFX942-NEXT: v_mov_b32_e32 v3, s7
-; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: v8i32_arg:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB9_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB9_0:
-; GFX90a-NEXT: s_load_dwordx8 s[12:19], s[4:5], 0x20
-; GFX90a-NEXT: v_mov_b32_e32 v4, 0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: v_mov_b32_e32 v0, s16
-; GFX90a-NEXT: v_mov_b32_e32 v1, s17
-; GFX90a-NEXT: v_mov_b32_e32 v2, s18
-; GFX90a-NEXT: v_mov_b32_e32 v3, s19
-; GFX90a-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9] offset:16
-; GFX90a-NEXT: s_nop 0
-; GFX90a-NEXT: v_mov_b32_e32 v0, s12
-; GFX90a-NEXT: v_mov_b32_e32 v1, s13
-; GFX90a-NEXT: v_mov_b32_e32 v2, s14
-; GFX90a-NEXT: v_mov_b32_e32 v3, s15
-; GFX90a-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: v8i32_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB9_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB9_0:
-; GISEL-GFX90A-NEXT: s_load_dwordx8 s[12:19], s[4:5], 0x20
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v8, 0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[12:13], s[12:13] op_sel:[0,1]
-; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[2:3], s[14:15], s[14:15] op_sel:[0,1]
-; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[4:5], s[16:17], s[16:17] op_sel:[0,1]
-; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[6:7], s[18:19], s[18:19] op_sel:[0,1]
-; GISEL-GFX90A-NEXT: global_store_dwordx4 v8, v[0:3], s[8:9]
-; GISEL-GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[8:9] offset:16
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: v8i32_arg:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v0, s14
-; GFX1250-NEXT: v_dual_mov_b32 v1, s15 :: v_dual_mov_b32 v2, s16
-; GFX1250-NEXT: v_dual_mov_b32 v3, s17 :: v_dual_mov_b32 v4, s10
-; GFX1250-NEXT: v_dual_mov_b32 v5, s11 :: v_dual_mov_b32 v6, s12
-; GFX1250-NEXT: v_mov_b32_e32 v7, s13
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: global_store_b128 v8, v[0:3], s[2:3] offset:16
-; GFX1250-NEXT: global_store_b128 v8, v[4:7], s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: v8i32_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB9_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB9_0:
+; GFX942-SDAG-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x20
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, s8
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s9
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, s10
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, s11
+; GFX942-SDAG-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] offset:16
+; GFX942-SDAG-NEXT: s_nop 1
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s5
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, s6
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, s7
+; GFX942-SDAG-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: v8i32_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB9_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB9_0:
+; GFX942-GISEL-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x20
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[4:5]
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[6:7]
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[8:9]
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[10:11]
+; GFX942-GISEL-NEXT: global_store_dwordx4 v8, v[0:3], s[2:3]
+; GFX942-GISEL-NEXT: global_store_dwordx4 v8, v[4:7], s[2:3] offset:16
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: v8i32_arg:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB9_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB9_0:
+; GFX90a-SDAG-NEXT: s_load_dwordx8 s[12:19], s[4:5], 0x20
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v4, 0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, s16
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s17
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v2, s18
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v3, s19
+; GFX90a-SDAG-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9] offset:16
+; GFX90a-SDAG-NEXT: s_nop 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, s12
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s13
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v2, s14
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v3, s15
+; GFX90a-SDAG-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: v8i32_arg:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB9_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB9_0:
+; GFX90a-GISEL-NEXT: s_load_dwordx8 s[12:19], s[4:5], 0x20
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v8, 0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[12:13], s[12:13] op_sel:[0,1]
+; GFX90a-GISEL-NEXT: v_pk_mov_b32 v[2:3], s[14:15], s[14:15] op_sel:[0,1]
+; GFX90a-GISEL-NEXT: v_pk_mov_b32 v[4:5], s[16:17], s[16:17] op_sel:[0,1]
+; GFX90a-GISEL-NEXT: v_pk_mov_b32 v[6:7], s[18:19], s[18:19] op_sel:[0,1]
+; GFX90a-GISEL-NEXT: global_store_dwordx4 v8, v[0:3], s[8:9]
+; GFX90a-GISEL-NEXT: global_store_dwordx4 v8, v[4:7], s[8:9] offset:16
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: v8i32_arg:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v0, s14
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v1, s15 :: v_dual_mov_b32 v2, s16
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, s17 :: v_dual_mov_b32 v4, s10
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, s11 :: v_dual_mov_b32 v6, s12
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v7, s13
+; GFX1250-SDAG-NEXT: s_clause 0x1
+; GFX1250-SDAG-NEXT: global_store_b128 v8, v[0:3], s[2:3] offset:16
+; GFX1250-SDAG-NEXT: global_store_b128 v8, v[4:7], s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: v8i32_arg:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b32 s5, s15
+; GFX1250-GISEL-NEXT: s_mov_b32 s4, s14
+; GFX1250-GISEL-NEXT: s_mov_b32 s15, s13
+; GFX1250-GISEL-NEXT: s_mov_b32 s14, s12
+; GFX1250-GISEL-NEXT: s_mov_b32 s13, s11
+; GFX1250-GISEL-NEXT: s_mov_b32 s12, s10
+; GFX1250-GISEL-NEXT: s_mov_b32 s7, s17
+; GFX1250-GISEL-NEXT: s_mov_b32 s6, s16
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[12:13]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[14:15]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v8, 0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
+; GFX1250-GISEL-NEXT: s_clause 0x1
+; GFX1250-GISEL-NEXT: global_store_b128 v8, v[0:3], s[2:3]
+; GFX1250-GISEL-NEXT: global_store_b128 v8, v[4:7], s[2:3] offset:16
+; GFX1250-GISEL-NEXT: s_endpgm
store <8 x i32> %in, ptr addrspace(1) %out, align 4
ret void
}
define amdgpu_kernel void @v3i16_preload_arg(ptr addrspace(1) nocapture inreg %out, <3 x i16> inreg %in) #0 {
-; GFX942-LABEL: v3i16_preload_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB10_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB10_0:
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s5
-; GFX942-NEXT: global_store_short v0, v1, s[2:3] offset:4
-; GFX942-NEXT: v_mov_b32_e32 v1, s4
-; GFX942-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: v3i16_preload_arg:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB10_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB10_0:
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s11
-; GFX90a-NEXT: global_store_short v0, v1, s[8:9] offset:4
-; GFX90a-NEXT: v_mov_b32_e32 v1, s10
-; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: v3i16_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB10_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB10_0:
-; GISEL-GFX90A-NEXT: s_lshr_b32 s0, s10, 16
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9] offset:2
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s11
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9] offset:4
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: v3i16_preload_arg:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s5
-; GFX1250-NEXT: v_mov_b32_e32 v2, s4
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: global_store_b16 v0, v1, s[2:3] offset:4
-; GFX1250-NEXT: global_store_b32 v0, v2, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: v3i16_preload_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB10_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB10_0:
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s5
+; GFX942-SDAG-NEXT: global_store_short v0, v1, s[2:3] offset:4
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s4
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: v3i16_preload_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB10_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB10_0:
+; GFX942-GISEL-NEXT: s_lshr_b32 s0, s4, 16
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[2:3] offset:2
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[2:3] offset:4
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: v3i16_preload_arg:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB10_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB10_0:
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s11
+; GFX90a-SDAG-NEXT: global_store_short v0, v1, s[8:9] offset:4
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s10
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: v3i16_preload_arg:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB10_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB10_0:
+; GFX90a-GISEL-NEXT: s_lshr_b32 s0, s10, 16
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s10
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[8:9] offset:2
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s11
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[8:9] offset:4
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: v3i16_preload_arg:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s5
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, s4
+; GFX1250-SDAG-NEXT: s_clause 0x1
+; GFX1250-SDAG-NEXT: global_store_b16 v0, v1, s[2:3] offset:4
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v2, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: v3i16_preload_arg:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_lshr_b32 s0, s4, 16
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v0.l, s4
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v0.h, s0
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v1.l, s5
+; GFX1250-GISEL-NEXT: s_clause 0x2
+; GFX1250-GISEL-NEXT: global_store_b16 v2, v0, s[2:3]
+; GFX1250-GISEL-NEXT: global_store_d16_hi_b16 v2, v0, s[2:3] offset:2
+; GFX1250-GISEL-NEXT: global_store_b16 v2, v1, s[2:3] offset:4
+; GFX1250-GISEL-NEXT: s_endpgm
store <3 x i16> %in, ptr addrspace(1) %out, align 4
ret void
}
define amdgpu_kernel void @v3i32_preload_arg(ptr addrspace(1) nocapture inreg %out, <3 x i32> inreg %in) #0 {
-; GFX942-LABEL: v3i32_preload_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
-; GFX942-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB11_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB11_0:
-; GFX942-NEXT: v_mov_b32_e32 v0, s6
-; GFX942-NEXT: v_mov_b32_e32 v1, s7
-; GFX942-NEXT: v_mov_b32_e32 v2, s8
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
-; GFX942-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: v3i32_preload_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB11_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB11_0:
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, s6
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s7
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, s8
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-SDAG-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: v3i32_preload_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB11_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB11_0:
+; GFX942-GISEL-NEXT: s_mov_b32 s10, s8
+; GFX942-GISEL-NEXT: s_mov_b32 s8, s6
+; GFX942-GISEL-NEXT: s_mov_b32 s9, s7
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s8
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, s9
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v2, s10
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
;
; GFX90a-LABEL: v3i32_preload_arg:
; GFX90a: ; %bb.1:
@@ -755,407 +981,558 @@ define amdgpu_kernel void @v3i32_preload_arg(ptr addrspace(1) nocapture inreg %o
; GFX90a-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
; GFX90a-NEXT: s_endpgm
;
-; GISEL-GFX90A-LABEL: v3i32_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB11_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB11_0:
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s12
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, s13
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, s14
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v3, 0
-; GISEL-GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: v3i32_preload_arg:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
-; GFX1250-NEXT: v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v3, 0
-; GFX1250-NEXT: global_store_b96 v3, v[0:2], s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX1250-SDAG-LABEL: v3i32_preload_arg:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v3, 0
+; GFX1250-SDAG-NEXT: global_store_b96 v3, v[0:2], s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: v3i32_preload_arg:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b32 s10, s8
+; GFX1250-GISEL-NEXT: s_mov_b32 s8, s6
+; GFX1250-GISEL-NEXT: s_mov_b32 s9, s7
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, 0
+; GFX1250-GISEL-NEXT: global_store_b96 v3, v[0:2], s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
store <3 x i32> %in, ptr addrspace(1) %out, align 4
ret void
}
define amdgpu_kernel void @v3f32_preload_arg(ptr addrspace(1) nocapture inreg %out, <3 x float> inreg %in) #0 {
-; GFX942-LABEL: v3f32_preload_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
-; GFX942-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB12_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB12_0:
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, s6
-; GFX942-NEXT: v_mov_b32_e32 v1, s7
-; GFX942-NEXT: v_mov_b32_e32 v2, s8
-; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: v3f32_preload_arg:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB12_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB12_0:
-; GFX90a-NEXT: v_mov_b32_e32 v3, 0
-; GFX90a-NEXT: v_mov_b32_e32 v0, s12
-; GFX90a-NEXT: v_mov_b32_e32 v1, s13
-; GFX90a-NEXT: v_mov_b32_e32 v2, s14
-; GFX90a-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: v3f32_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB12_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB12_0:
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s12
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, s13
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, s14
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v3, 0
-; GISEL-GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: v3f32_preload_arg:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s6
-; GFX1250-NEXT: v_dual_mov_b32 v1, s7 :: v_dual_mov_b32 v2, s8
-; GFX1250-NEXT: global_store_b96 v3, v[0:2], s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: v3f32_preload_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB12_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB12_0:
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, s6
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s7
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, s8
+; GFX942-SDAG-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: v3f32_preload_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB12_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB12_0:
+; GFX942-GISEL-NEXT: s_mov_b32 s10, s8
+; GFX942-GISEL-NEXT: s_mov_b32 s8, s6
+; GFX942-GISEL-NEXT: s_mov_b32 s9, s7
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s8
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, s9
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v2, s10
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: v3f32_preload_arg:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB12_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB12_0:
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v3, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, s12
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s13
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v2, s14
+; GFX90a-SDAG-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: v3f32_preload_arg:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB12_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB12_0:
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s12
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, s13
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v2, s14
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX90a-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: v3f32_preload_arg:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s6
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v1, s7 :: v_dual_mov_b32 v2, s8
+; GFX1250-SDAG-NEXT: global_store_b96 v3, v[0:2], s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: v3f32_preload_arg:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b32 s10, s8
+; GFX1250-GISEL-NEXT: s_mov_b32 s8, s6
+; GFX1250-GISEL-NEXT: s_mov_b32 s9, s7
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, 0
+; GFX1250-GISEL-NEXT: global_store_b96 v3, v[0:2], s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
store <3 x float> %in, ptr addrspace(1) %out, align 4
ret void
}
define amdgpu_kernel void @v5i8_preload_arg(ptr addrspace(1) nocapture inreg %out, <5 x i8> inreg %in) #0 {
-; GFX942-LABEL: v5i8_preload_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB13_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB13_0:
-; GFX942-NEXT: s_lshr_b32 s1, s4, 24
-; GFX942-NEXT: s_and_b32 s0, s4, 0xffff
-; GFX942-NEXT: s_lshl_b32 s1, s1, 8
-; GFX942-NEXT: s_bfe_u32 s4, s4, 0x80010
-; GFX942-NEXT: s_or_b32 s1, s4, s1
-; GFX942-NEXT: s_lshl_b32 s1, s1, 16
-; GFX942-NEXT: s_or_b32 s0, s0, s1
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s5
-; GFX942-NEXT: global_store_byte v0, v1, s[2:3] offset:4
-; GFX942-NEXT: v_mov_b32_e32 v1, s0
-; GFX942-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: v5i8_preload_arg:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB13_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB13_0:
-; GFX90a-NEXT: s_lshr_b32 s1, s10, 24
-; GFX90a-NEXT: s_lshl_b32 s1, s1, 8
-; GFX90a-NEXT: s_bfe_u32 s2, s10, 0x80010
-; GFX90a-NEXT: s_or_b32 s1, s2, s1
-; GFX90a-NEXT: s_and_b32 s0, s10, 0xffff
-; GFX90a-NEXT: s_lshl_b32 s1, s1, 16
-; GFX90a-NEXT: s_or_b32 s0, s0, s1
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s11
-; GFX90a-NEXT: global_store_byte v0, v1, s[8:9] offset:4
-; GFX90a-NEXT: v_mov_b32_e32 v1, s0
-; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: v5i8_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB13_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB13_0:
-; GISEL-GFX90A-NEXT: s_and_b32 s1, 0xffff, s10
-; GISEL-GFX90A-NEXT: s_lshr_b32 s1, s1, 8
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: s_lshr_b32 s0, s10, 16
-; GISEL-GFX90A-NEXT: global_store_byte v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s1
-; GISEL-GFX90A-NEXT: s_lshr_b32 s2, s10, 24
-; GISEL-GFX90A-NEXT: global_store_byte v1, v0, s[8:9] offset:1
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: global_store_byte v1, v0, s[8:9] offset:2
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX90A-NEXT: global_store_byte v1, v0, s[8:9] offset:3
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s11
-; GISEL-GFX90A-NEXT: global_store_byte v1, v0, s[8:9] offset:4
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: v5i8_preload_arg:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_pack_lh_b32_b16 s0, 0, s4
-; GFX1250-NEXT: s_and_b32 s1, s4, 0xffff
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s5
-; GFX1250-NEXT: s_or_b32 s0, s1, s0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_mov_b32_e32 v2, s0
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: global_store_b8 v0, v1, s[2:3] offset:4
-; GFX1250-NEXT: global_store_b32 v0, v2, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: v5i8_preload_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB13_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB13_0:
+; GFX942-SDAG-NEXT: s_lshr_b32 s1, s4, 24
+; GFX942-SDAG-NEXT: s_and_b32 s0, s4, 0xffff
+; GFX942-SDAG-NEXT: s_lshl_b32 s1, s1, 8
+; GFX942-SDAG-NEXT: s_bfe_u32 s4, s4, 0x80010
+; GFX942-SDAG-NEXT: s_or_b32 s1, s4, s1
+; GFX942-SDAG-NEXT: s_lshl_b32 s1, s1, 16
+; GFX942-SDAG-NEXT: s_or_b32 s0, s0, s1
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s5
+; GFX942-SDAG-NEXT: global_store_byte v0, v1, s[2:3] offset:4
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: v5i8_preload_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB13_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB13_0:
+; GFX942-GISEL-NEXT: s_and_b32 s1, 0xffff, s4
+; GFX942-GISEL-NEXT: s_lshr_b32 s1, s1, 8
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: s_lshr_b32 s0, s4, 16
+; GFX942-GISEL-NEXT: global_store_byte v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s1
+; GFX942-GISEL-NEXT: s_lshr_b32 s6, s4, 24
+; GFX942-GISEL-NEXT: global_store_byte v1, v0, s[2:3] offset:1
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX942-GISEL-NEXT: global_store_byte v1, v0, s[2:3] offset:2
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX942-GISEL-NEXT: global_store_byte v1, v0, s[2:3] offset:3
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; GFX942-GISEL-NEXT: global_store_byte v1, v0, s[2:3] offset:4
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: v5i8_preload_arg:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB13_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB13_0:
+; GFX90a-SDAG-NEXT: s_lshr_b32 s1, s10, 24
+; GFX90a-SDAG-NEXT: s_lshl_b32 s1, s1, 8
+; GFX90a-SDAG-NEXT: s_bfe_u32 s2, s10, 0x80010
+; GFX90a-SDAG-NEXT: s_or_b32 s1, s2, s1
+; GFX90a-SDAG-NEXT: s_and_b32 s0, s10, 0xffff
+; GFX90a-SDAG-NEXT: s_lshl_b32 s1, s1, 16
+; GFX90a-SDAG-NEXT: s_or_b32 s0, s0, s1
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s11
+; GFX90a-SDAG-NEXT: global_store_byte v0, v1, s[8:9] offset:4
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: v5i8_preload_arg:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB13_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB13_0:
+; GFX90a-GISEL-NEXT: s_and_b32 s1, 0xffff, s10
+; GFX90a-GISEL-NEXT: s_lshr_b32 s1, s1, 8
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s10
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: s_lshr_b32 s0, s10, 16
+; GFX90a-GISEL-NEXT: global_store_byte v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s1
+; GFX90a-GISEL-NEXT: s_lshr_b32 s2, s10, 24
+; GFX90a-GISEL-NEXT: global_store_byte v1, v0, s[8:9] offset:1
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: global_store_byte v1, v0, s[8:9] offset:2
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX90a-GISEL-NEXT: global_store_byte v1, v0, s[8:9] offset:3
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s11
+; GFX90a-GISEL-NEXT: global_store_byte v1, v0, s[8:9] offset:4
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: v5i8_preload_arg:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_pack_lh_b32_b16 s0, 0, s4
+; GFX1250-SDAG-NEXT: s_and_b32 s1, s4, 0xffff
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s5
+; GFX1250-SDAG-NEXT: s_or_b32 s0, s1, s0
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, s0
+; GFX1250-SDAG-NEXT: s_clause 0x1
+; GFX1250-SDAG-NEXT: global_store_b8 v0, v1, s[2:3] offset:4
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v2, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: v5i8_preload_arg:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_and_b32 s0, 0xffff, s4
+; GFX1250-GISEL-NEXT: s_lshr_b32 s1, s4, 16
+; GFX1250-GISEL-NEXT: s_lshr_b32 s0, s0, 8
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, 0
+; GFX1250-GISEL-NEXT: s_lshr_b32 s6, s1, 8
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v5, s5
+; GFX1250-GISEL-NEXT: s_clause 0x4
+; GFX1250-GISEL-NEXT: global_store_b8 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: global_store_b8 v1, v2, s[2:3] offset:1
+; GFX1250-GISEL-NEXT: global_store_b8 v1, v3, s[2:3] offset:2
+; GFX1250-GISEL-NEXT: global_store_b8 v1, v4, s[2:3] offset:3
+; GFX1250-GISEL-NEXT: global_store_b8 v1, v5, s[2:3] offset:4
+; GFX1250-GISEL-NEXT: s_endpgm
store <5 x i8> %in, ptr addrspace(1) %out, align 4
ret void
}
define amdgpu_kernel void @v5f64_arg(ptr addrspace(1) nocapture inreg %out, <5 x double> inreg %in) #0 {
-; GFX942-LABEL: v5f64_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB14_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB14_0:
-; GFX942-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x60
-; GFX942-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x40
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[12:13]
-; GFX942-NEXT: v_mov_b32_e32 v0, s8
-; GFX942-NEXT: global_store_dwordx2 v4, v[2:3], s[2:3] offset:32
-; GFX942-NEXT: v_mov_b32_e32 v1, s9
-; GFX942-NEXT: v_mov_b32_e32 v2, s10
-; GFX942-NEXT: v_mov_b32_e32 v3, s11
-; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] offset:16
-; GFX942-NEXT: s_nop 1
-; GFX942-NEXT: v_mov_b32_e32 v0, s4
-; GFX942-NEXT: v_mov_b32_e32 v1, s5
-; GFX942-NEXT: v_mov_b32_e32 v2, s6
-; GFX942-NEXT: v_mov_b32_e32 v3, s7
-; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: v5f64_arg:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB14_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB14_0:
-; GFX90a-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x60
-; GFX90a-NEXT: s_load_dwordx8 s[12:19], s[4:5], 0x40
-; GFX90a-NEXT: v_mov_b32_e32 v4, 0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: v_pk_mov_b32 v[2:3], s[0:1], s[0:1] op_sel:[0,1]
-; GFX90a-NEXT: v_mov_b32_e32 v0, s16
-; GFX90a-NEXT: global_store_dwordx2 v4, v[2:3], s[8:9] offset:32
-; GFX90a-NEXT: v_mov_b32_e32 v1, s17
-; GFX90a-NEXT: v_mov_b32_e32 v2, s18
-; GFX90a-NEXT: v_mov_b32_e32 v3, s19
-; GFX90a-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9] offset:16
-; GFX90a-NEXT: s_nop 0
-; GFX90a-NEXT: v_mov_b32_e32 v0, s12
-; GFX90a-NEXT: v_mov_b32_e32 v1, s13
-; GFX90a-NEXT: v_mov_b32_e32 v2, s14
-; GFX90a-NEXT: v_mov_b32_e32 v3, s15
-; GFX90a-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: v5f64_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB14_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB14_0:
-; GISEL-GFX90A-NEXT: s_load_dwordx8 s[12:19], s[4:5], 0x40
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x60
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v8, 0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[12:13], s[12:13] op_sel:[0,1]
-; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[2:3], s[14:15], s[14:15] op_sel:[0,1]
-; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[4:5], s[16:17], s[16:17] op_sel:[0,1]
-; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[6:7], s[18:19], s[18:19] op_sel:[0,1]
-; GISEL-GFX90A-NEXT: global_store_dwordx4 v8, v[0:3], s[8:9]
-; GISEL-GFX90A-NEXT: global_store_dwordx4 v8, v[4:7], s[8:9] offset:16
-; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
-; GISEL-GFX90A-NEXT: global_store_dwordx2 v8, v[0:1], s[8:9] offset:32
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: v5f64_arg:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: s_load_b64 s[12:13], s[0:1], 0x60 nv
-; GFX1250-NEXT: s_load_b256 s[4:11], s[0:1], 0x40 nv
-; GFX1250-NEXT: v_mov_b32_e32 v10, 0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_mov_b64_e32 v[8:9], s[12:13]
-; GFX1250-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
-; GFX1250-NEXT: v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, s11
-; GFX1250-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
-; GFX1250-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
-; GFX1250-NEXT: s_clause 0x2
-; GFX1250-NEXT: global_store_b64 v10, v[8:9], s[2:3] offset:32
-; GFX1250-NEXT: global_store_b128 v10, v[0:3], s[2:3] offset:16
-; GFX1250-NEXT: global_store_b128 v10, v[4:7], s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: v5f64_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB14_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB14_0:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x60
+; GFX942-SDAG-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x40
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[12:13]
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, s8
+; GFX942-SDAG-NEXT: global_store_dwordx2 v4, v[2:3], s[2:3] offset:32
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s9
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, s10
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, s11
+; GFX942-SDAG-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] offset:16
+; GFX942-SDAG-NEXT: s_nop 1
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s5
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, s6
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, s7
+; GFX942-SDAG-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: v5f64_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB14_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB14_0:
+; GFX942-GISEL-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x40
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v8, 0
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x60
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[4:5]
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[6:7]
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[8:9]
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[10:11]
+; GFX942-GISEL-NEXT: global_store_dwordx4 v8, v[0:3], s[2:3]
+; GFX942-GISEL-NEXT: global_store_dwordx4 v8, v[4:7], s[2:3] offset:16
+; GFX942-GISEL-NEXT: s_nop 0
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
+; GFX942-GISEL-NEXT: global_store_dwordx2 v8, v[0:1], s[2:3] offset:32
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: v5f64_arg:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB14_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB14_0:
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x60
+; GFX90a-SDAG-NEXT: s_load_dwordx8 s[12:19], s[4:5], 0x40
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v4, 0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: v_pk_mov_b32 v[2:3], s[0:1], s[0:1] op_sel:[0,1]
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, s16
+; GFX90a-SDAG-NEXT: global_store_dwordx2 v4, v[2:3], s[8:9] offset:32
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s17
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v2, s18
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v3, s19
+; GFX90a-SDAG-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9] offset:16
+; GFX90a-SDAG-NEXT: s_nop 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, s12
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s13
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v2, s14
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v3, s15
+; GFX90a-SDAG-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: v5f64_arg:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB14_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB14_0:
+; GFX90a-GISEL-NEXT: s_load_dwordx8 s[12:19], s[4:5], 0x40
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x60
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v8, 0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[12:13], s[12:13] op_sel:[0,1]
+; GFX90a-GISEL-NEXT: v_pk_mov_b32 v[2:3], s[14:15], s[14:15] op_sel:[0,1]
+; GFX90a-GISEL-NEXT: v_pk_mov_b32 v[4:5], s[16:17], s[16:17] op_sel:[0,1]
+; GFX90a-GISEL-NEXT: v_pk_mov_b32 v[6:7], s[18:19], s[18:19] op_sel:[0,1]
+; GFX90a-GISEL-NEXT: global_store_dwordx4 v8, v[0:3], s[8:9]
+; GFX90a-GISEL-NEXT: global_store_dwordx4 v8, v[4:7], s[8:9] offset:16
+; GFX90a-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
+; GFX90a-GISEL-NEXT: global_store_dwordx2 v8, v[0:1], s[8:9] offset:32
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: v5f64_arg:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_clause 0x1
+; GFX1250-SDAG-NEXT: s_load_b64 s[12:13], s[0:1], 0x60 nv
+; GFX1250-SDAG-NEXT: s_load_b256 s[4:11], s[0:1], 0x40 nv
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v10, 0
+; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1250-SDAG-NEXT: v_mov_b64_e32 v[8:9], s[12:13]
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, s11
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
+; GFX1250-SDAG-NEXT: s_clause 0x2
+; GFX1250-SDAG-NEXT: global_store_b64 v10, v[8:9], s[2:3] offset:32
+; GFX1250-SDAG-NEXT: global_store_b128 v10, v[0:3], s[2:3] offset:16
+; GFX1250-SDAG-NEXT: global_store_b128 v10, v[4:7], s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: v5f64_arg:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_clause 0x1
+; GFX1250-GISEL-NEXT: s_load_b256 s[4:11], s[0:1], 0x40 nv
+; GFX1250-GISEL-NEXT: s_load_b64 s[12:13], s[0:1], 0x60 nv
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v10, 0
+; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[4:5]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[6:7]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[8:9]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[10:11]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[12:13]
+; GFX1250-GISEL-NEXT: s_clause 0x2
+; GFX1250-GISEL-NEXT: global_store_b128 v10, v[0:3], s[2:3]
+; GFX1250-GISEL-NEXT: global_store_b128 v10, v[4:7], s[2:3] offset:16
+; GFX1250-GISEL-NEXT: global_store_b64 v10, v[8:9], s[2:3] offset:32
+; GFX1250-GISEL-NEXT: s_endpgm
store <5 x double> %in, ptr addrspace(1) %out, align 8
ret void
}
define amdgpu_kernel void @v8i8_preload_arg(ptr addrspace(1) inreg %out, <8 x i8> inreg %in) #0 {
-; GFX942-LABEL: v8i8_preload_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB15_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB15_0:
-; GFX942-NEXT: s_lshr_b32 s1, s5, 24
-; GFX942-NEXT: s_and_b32 s0, s5, 0xffff
-; GFX942-NEXT: s_lshl_b32 s1, s1, 8
-; GFX942-NEXT: s_bfe_u32 s5, s5, 0x80010
-; GFX942-NEXT: s_or_b32 s1, s5, s1
-; GFX942-NEXT: s_lshl_b32 s1, s1, 16
-; GFX942-NEXT: s_lshr_b32 s5, s4, 24
-; GFX942-NEXT: s_or_b32 s0, s0, s1
-; GFX942-NEXT: s_and_b32 s1, s4, 0xffff
-; GFX942-NEXT: s_lshl_b32 s5, s5, 8
-; GFX942-NEXT: s_bfe_u32 s4, s4, 0x80010
-; GFX942-NEXT: s_or_b32 s4, s4, s5
-; GFX942-NEXT: s_lshl_b32 s4, s4, 16
-; GFX942-NEXT: s_or_b32 s1, s1, s4
-; GFX942-NEXT: v_mov_b32_e32 v0, s1
-; GFX942-NEXT: v_mov_b32_e32 v1, s0
-; GFX942-NEXT: v_mov_b32_e32 v2, 0
-; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: v8i8_preload_arg:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB15_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB15_0:
-; GFX90a-NEXT: s_lshr_b32 s1, s11, 24
-; GFX90a-NEXT: s_lshl_b32 s1, s1, 8
-; GFX90a-NEXT: s_bfe_u32 s2, s11, 0x80010
-; GFX90a-NEXT: s_or_b32 s1, s2, s1
-; GFX90a-NEXT: s_lshr_b32 s2, s10, 24
-; GFX90a-NEXT: s_lshl_b32 s2, s2, 8
-; GFX90a-NEXT: s_bfe_u32 s3, s10, 0x80010
-; GFX90a-NEXT: s_and_b32 s0, s11, 0xffff
-; GFX90a-NEXT: s_lshl_b32 s1, s1, 16
-; GFX90a-NEXT: s_or_b32 s2, s3, s2
-; GFX90a-NEXT: s_or_b32 s0, s0, s1
-; GFX90a-NEXT: s_and_b32 s1, s10, 0xffff
-; GFX90a-NEXT: s_lshl_b32 s2, s2, 16
-; GFX90a-NEXT: s_or_b32 s1, s1, s2
-; GFX90a-NEXT: v_mov_b32_e32 v0, s1
-; GFX90a-NEXT: v_mov_b32_e32 v1, s0
-; GFX90a-NEXT: v_mov_b32_e32 v2, 0
-; GFX90a-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: v8i8_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB15_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB15_0:
-; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[10:11], s[10:11] op_sel:[0,1]
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, 0
-; GISEL-GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: v8i8_preload_arg:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_pack_lh_b32_b16 s0, 0, s5
-; GFX1250-NEXT: s_pack_lh_b32_b16 s1, 0, s4
-; GFX1250-NEXT: s_and_b32 s4, s4, 0xffff
-; GFX1250-NEXT: s_and_b32 s5, s5, 0xffff
-; GFX1250-NEXT: s_or_b32 s1, s4, s1
-; GFX1250-NEXT: s_or_b32 s0, s5, s0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
-; GFX1250-NEXT: v_mov_b32_e32 v2, 0
-; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: v8i8_preload_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB15_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB15_0:
+; GFX942-SDAG-NEXT: s_lshr_b32 s1, s5, 24
+; GFX942-SDAG-NEXT: s_and_b32 s0, s5, 0xffff
+; GFX942-SDAG-NEXT: s_lshl_b32 s1, s1, 8
+; GFX942-SDAG-NEXT: s_bfe_u32 s5, s5, 0x80010
+; GFX942-SDAG-NEXT: s_or_b32 s1, s5, s1
+; GFX942-SDAG-NEXT: s_lshl_b32 s1, s1, 16
+; GFX942-SDAG-NEXT: s_lshr_b32 s5, s4, 24
+; GFX942-SDAG-NEXT: s_or_b32 s0, s0, s1
+; GFX942-SDAG-NEXT: s_and_b32 s1, s4, 0xffff
+; GFX942-SDAG-NEXT: s_lshl_b32 s5, s5, 8
+; GFX942-SDAG-NEXT: s_bfe_u32 s4, s4, 0x80010
+; GFX942-SDAG-NEXT: s_or_b32 s4, s4, s5
+; GFX942-SDAG-NEXT: s_lshl_b32 s4, s4, 16
+; GFX942-SDAG-NEXT: s_or_b32 s1, s1, s4
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, s1
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX942-SDAG-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: v8i8_preload_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB15_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB15_0:
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[4:5]
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX942-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: v8i8_preload_arg:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB15_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB15_0:
+; GFX90a-SDAG-NEXT: s_lshr_b32 s1, s11, 24
+; GFX90a-SDAG-NEXT: s_lshl_b32 s1, s1, 8
+; GFX90a-SDAG-NEXT: s_bfe_u32 s2, s11, 0x80010
+; GFX90a-SDAG-NEXT: s_or_b32 s1, s2, s1
+; GFX90a-SDAG-NEXT: s_lshr_b32 s2, s10, 24
+; GFX90a-SDAG-NEXT: s_lshl_b32 s2, s2, 8
+; GFX90a-SDAG-NEXT: s_bfe_u32 s3, s10, 0x80010
+; GFX90a-SDAG-NEXT: s_and_b32 s0, s11, 0xffff
+; GFX90a-SDAG-NEXT: s_lshl_b32 s1, s1, 16
+; GFX90a-SDAG-NEXT: s_or_b32 s2, s3, s2
+; GFX90a-SDAG-NEXT: s_or_b32 s0, s0, s1
+; GFX90a-SDAG-NEXT: s_and_b32 s1, s10, 0xffff
+; GFX90a-SDAG-NEXT: s_lshl_b32 s2, s2, 16
+; GFX90a-SDAG-NEXT: s_or_b32 s1, s1, s2
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, s1
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX90a-SDAG-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: v8i8_preload_arg:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB15_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB15_0:
+; GFX90a-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[10:11], s[10:11] op_sel:[0,1]
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX90a-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: v8i8_preload_arg:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_pack_lh_b32_b16 s0, 0, s5
+; GFX1250-SDAG-NEXT: s_pack_lh_b32_b16 s1, 0, s4
+; GFX1250-SDAG-NEXT: s_and_b32 s4, s4, 0xffff
+; GFX1250-SDAG-NEXT: s_and_b32 s5, s5, 0xffff
+; GFX1250-SDAG-NEXT: s_or_b32 s1, s4, s1
+; GFX1250-SDAG-NEXT: s_or_b32 s0, s5, s0
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250-SDAG-NEXT: global_store_b64 v2, v[0:1], s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: v8i8_preload_arg:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[4:5]
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250-GISEL-NEXT: global_store_b64 v2, v[0:1], s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
store <8 x i8> %in, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @i64_kernel_preload_arg(ptr addrspace(1) inreg %out, i64 inreg %a) #0 {
-; GFX942-LABEL: i64_kernel_preload_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB16_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB16_0:
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[4:5]
-; GFX942-NEXT: global_store_dwordx2 v0, v[2:3], s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: i64_kernel_preload_arg:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB16_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB16_0:
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_pk_mov_b32 v[2:3], s[10:11], s[10:11] op_sel:[0,1]
-; GFX90a-NEXT: global_store_dwordx2 v0, v[2:3], s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: i64_kernel_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB16_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB16_0:
-; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[10:11], s[10:11] op_sel:[0,1]
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, 0
-; GISEL-GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: i64_kernel_preload_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB16_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB16_0:
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[4:5]
+; GFX942-SDAG-NEXT: global_store_dwordx2 v0, v[2:3], s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: i64_kernel_preload_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB16_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB16_0:
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[4:5]
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX942-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: i64_kernel_preload_arg:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB16_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB16_0:
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_pk_mov_b32 v[2:3], s[10:11], s[10:11] op_sel:[0,1]
+; GFX90a-SDAG-NEXT: global_store_dwordx2 v0, v[2:3], s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: i64_kernel_preload_arg:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB16_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB16_0:
+; GFX90a-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[10:11], s[10:11] op_sel:[0,1]
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX90a-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
;
; GFX1250-LABEL: i64_kernel_preload_arg:
; GFX1250: ; %bb.0:
@@ -1169,45 +1546,59 @@ define amdgpu_kernel void @i64_kernel_preload_arg(ptr addrspace(1) inreg %out, i
}
define amdgpu_kernel void @f64_kernel_preload_arg(ptr addrspace(1) inreg %out, double inreg %in) #0 {
-; GFX942-LABEL: f64_kernel_preload_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB17_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB17_0:
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[4:5]
-; GFX942-NEXT: global_store_dwordx2 v0, v[2:3], s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: f64_kernel_preload_arg:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB17_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB17_0:
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_pk_mov_b32 v[2:3], s[10:11], s[10:11] op_sel:[0,1]
-; GFX90a-NEXT: global_store_dwordx2 v0, v[2:3], s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: f64_kernel_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB17_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB17_0:
-; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[10:11], s[10:11] op_sel:[0,1]
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, 0
-; GISEL-GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: f64_kernel_preload_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB17_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB17_0:
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[4:5]
+; GFX942-SDAG-NEXT: global_store_dwordx2 v0, v[2:3], s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: f64_kernel_preload_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB17_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB17_0:
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[4:5]
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX942-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: f64_kernel_preload_arg:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB17_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB17_0:
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_pk_mov_b32 v[2:3], s[10:11], s[10:11] op_sel:[0,1]
+; GFX90a-SDAG-NEXT: global_store_dwordx2 v0, v[2:3], s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: f64_kernel_preload_arg:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB17_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB17_0:
+; GFX90a-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[10:11], s[10:11] op_sel:[0,1]
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX90a-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
;
; GFX1250-LABEL: f64_kernel_preload_arg:
; GFX1250: ; %bb.0:
@@ -1221,244 +1612,362 @@ define amdgpu_kernel void @f64_kernel_preload_arg(ptr addrspace(1) inreg %out, d
}
define amdgpu_kernel void @half_kernel_preload_arg(ptr addrspace(1) inreg %out, half inreg %in) #0 {
-; GFX942-LABEL: half_kernel_preload_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dword s4, s[0:1], 0x8
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB18_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB18_0:
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s4
-; GFX942-NEXT: global_store_short v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: half_kernel_preload_arg:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x8
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB18_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB18_0:
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s10
-; GFX90a-NEXT: global_store_short v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: half_kernel_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_load_dword s10, s[4:5], 0x8
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB18_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB18_0:
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: half_kernel_preload_arg:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
-; GFX1250-NEXT: global_store_b16 v0, v1, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: half_kernel_preload_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dword s4, s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB18_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB18_0:
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s4
+; GFX942-SDAG-NEXT: global_store_short v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: half_kernel_preload_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dword s4, s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB18_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB18_0:
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: half_kernel_preload_arg:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_load_dword s10, s[4:5], 0x8
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB18_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB18_0:
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s10
+; GFX90a-SDAG-NEXT: global_store_short v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: half_kernel_preload_arg:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_load_dword s10, s[4:5], 0x8
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB18_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB18_0:
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s10
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: half_kernel_preload_arg:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
+; GFX1250-SDAG-NEXT: global_store_b16 v0, v1, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: half_kernel_preload_arg:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v0.l, s4
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1250-GISEL-NEXT: global_store_b16 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
store half %in, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @bfloat_kernel_preload_arg(ptr addrspace(1) inreg %out, bfloat inreg %in) #0 {
-; GFX942-LABEL: bfloat_kernel_preload_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dword s4, s[0:1], 0x8
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB19_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB19_0:
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s4
-; GFX942-NEXT: global_store_short v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: bfloat_kernel_preload_arg:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x8
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB19_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB19_0:
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s10
-; GFX90a-NEXT: global_store_short v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: bfloat_kernel_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_load_dword s10, s[4:5], 0x8
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB19_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB19_0:
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: bfloat_kernel_preload_arg:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
-; GFX1250-NEXT: global_store_b16 v0, v1, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: bfloat_kernel_preload_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dword s4, s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB19_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB19_0:
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s4
+; GFX942-SDAG-NEXT: global_store_short v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: bfloat_kernel_preload_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dword s4, s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB19_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB19_0:
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: bfloat_kernel_preload_arg:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_load_dword s10, s[4:5], 0x8
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB19_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB19_0:
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s10
+; GFX90a-SDAG-NEXT: global_store_short v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: bfloat_kernel_preload_arg:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_load_dword s10, s[4:5], 0x8
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB19_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB19_0:
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s10
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: bfloat_kernel_preload_arg:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
+; GFX1250-SDAG-NEXT: global_store_b16 v0, v1, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: bfloat_kernel_preload_arg:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v0.l, s4
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1250-GISEL-NEXT: global_store_b16 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
store bfloat %in, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @v2bfloat_kernel_preload_arg(ptr addrspace(1) inreg %out, <2 x bfloat> inreg %in) #0 {
-; GFX942-LABEL: v2bfloat_kernel_preload_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dword s4, s[0:1], 0x8
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB20_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB20_0:
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s4
-; GFX942-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: v2bfloat_kernel_preload_arg:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x8
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB20_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB20_0:
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s10
-; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: v2bfloat_kernel_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_load_dword s10, s[4:5], 0x8
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB20_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB20_0:
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: v2bfloat_kernel_preload_arg:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
-; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: v2bfloat_kernel_preload_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dword s4, s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB20_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB20_0:
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s4
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: v2bfloat_kernel_preload_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dword s4, s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB20_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB20_0:
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: v2bfloat_kernel_preload_arg:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_load_dword s10, s[4:5], 0x8
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB20_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB20_0:
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s10
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: v2bfloat_kernel_preload_arg:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_load_dword s10, s[4:5], 0x8
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB20_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB20_0:
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s10
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_dword v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: v2bfloat_kernel_preload_arg:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: v2bfloat_kernel_preload_arg:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, 0
+; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
store <2 x bfloat> %in, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @v3bfloat_kernel_preload_arg(ptr addrspace(1) inreg %out, <3 x bfloat> inreg %in) #0 {
-; GFX942-LABEL: v3bfloat_kernel_preload_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB21_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB21_0:
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s5
-; GFX942-NEXT: global_store_short v0, v1, s[2:3] offset:4
-; GFX942-NEXT: v_mov_b32_e32 v1, s4
-; GFX942-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: v3bfloat_kernel_preload_arg:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB21_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB21_0:
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s11
-; GFX90a-NEXT: global_store_short v0, v1, s[8:9] offset:4
-; GFX90a-NEXT: v_mov_b32_e32 v1, s10
-; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: v3bfloat_kernel_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB21_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB21_0:
-; GISEL-GFX90A-NEXT: s_lshr_b32 s0, s10, 16
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9] offset:2
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s11
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9] offset:4
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: v3bfloat_kernel_preload_arg:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s5
-; GFX1250-NEXT: v_mov_b32_e32 v2, s4
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: global_store_b16 v0, v1, s[2:3] offset:4
-; GFX1250-NEXT: global_store_b32 v0, v2, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: v3bfloat_kernel_preload_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB21_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB21_0:
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s5
+; GFX942-SDAG-NEXT: global_store_short v0, v1, s[2:3] offset:4
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s4
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: v3bfloat_kernel_preload_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB21_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB21_0:
+; GFX942-GISEL-NEXT: s_lshr_b32 s0, s4, 16
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[2:3] offset:2
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[2:3] offset:4
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: v3bfloat_kernel_preload_arg:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB21_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB21_0:
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s11
+; GFX90a-SDAG-NEXT: global_store_short v0, v1, s[8:9] offset:4
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s10
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: v3bfloat_kernel_preload_arg:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB21_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB21_0:
+; GFX90a-GISEL-NEXT: s_lshr_b32 s0, s10, 16
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s10
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[8:9] offset:2
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s11
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[8:9] offset:4
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: v3bfloat_kernel_preload_arg:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s5
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, s4
+; GFX1250-SDAG-NEXT: s_clause 0x1
+; GFX1250-SDAG-NEXT: global_store_b16 v0, v1, s[2:3] offset:4
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v2, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: v3bfloat_kernel_preload_arg:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_lshr_b32 s0, s4, 16
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v0.l, s4
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v0.h, s0
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v1.l, s5
+; GFX1250-GISEL-NEXT: s_clause 0x2
+; GFX1250-GISEL-NEXT: global_store_b16 v2, v0, s[2:3]
+; GFX1250-GISEL-NEXT: global_store_d16_hi_b16 v2, v0, s[2:3] offset:2
+; GFX1250-GISEL-NEXT: global_store_b16 v2, v1, s[2:3] offset:4
+; GFX1250-GISEL-NEXT: s_endpgm
store <3 x bfloat> %in, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @v6bfloat_kernel_preload_arg(ptr addrspace(1) inreg %out, <6 x bfloat> inreg %in) #0 {
-; GFX942-LABEL: v6bfloat_kernel_preload_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
-; GFX942-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB22_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB22_0:
-; GFX942-NEXT: v_mov_b32_e32 v0, s6
-; GFX942-NEXT: v_mov_b32_e32 v1, s7
-; GFX942-NEXT: v_mov_b32_e32 v2, s8
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
-; GFX942-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: v6bfloat_kernel_preload_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB22_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB22_0:
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, s6
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s7
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, s8
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-SDAG-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: v6bfloat_kernel_preload_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB22_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB22_0:
+; GFX942-GISEL-NEXT: s_mov_b32 s10, s8
+; GFX942-GISEL-NEXT: s_mov_b32 s8, s6
+; GFX942-GISEL-NEXT: s_mov_b32 s9, s7
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s8
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, s9
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v2, s10
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
;
; GFX90a-LABEL: v6bfloat_kernel_preload_arg:
; GFX90a: ; %bb.1:
@@ -1475,680 +1984,1022 @@ define amdgpu_kernel void @v6bfloat_kernel_preload_arg(ptr addrspace(1) inreg %o
; GFX90a-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
; GFX90a-NEXT: s_endpgm
;
-; GISEL-GFX90A-LABEL: v6bfloat_kernel_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB22_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB22_0:
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s12
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, s13
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, s14
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v3, 0
-; GISEL-GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: v6bfloat_kernel_preload_arg:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
-; GFX1250-NEXT: v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v3, 0
-; GFX1250-NEXT: global_store_b96 v3, v[0:2], s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX1250-SDAG-LABEL: v6bfloat_kernel_preload_arg:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v3, 0
+; GFX1250-SDAG-NEXT: global_store_b96 v3, v[0:2], s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: v6bfloat_kernel_preload_arg:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b32 s10, s8
+; GFX1250-GISEL-NEXT: s_mov_b32 s8, s6
+; GFX1250-GISEL-NEXT: s_mov_b32 s9, s7
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, 0
+; GFX1250-GISEL-NEXT: global_store_b96 v3, v[0:2], s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
store <6 x bfloat> %in, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @half_v7bfloat_kernel_preload_arg(ptr addrspace(1) inreg %out, half inreg %in, <7 x bfloat> inreg %in2, ptr addrspace(1) inreg %out2) #0 {
-; GFX942-LABEL: half_v7bfloat_kernel_preload_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x8
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB23_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB23_0:
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, s4
-; GFX942-NEXT: global_store_short v3, v0, s[2:3]
-; GFX942-NEXT: v_mov_b32_e32 v0, s9
-; GFX942-NEXT: global_store_short v3, v0, s[10:11] offset:12
-; GFX942-NEXT: v_mov_b32_e32 v2, s8
-; GFX942-NEXT: v_mov_b32_e32 v0, s6
-; GFX942-NEXT: v_mov_b32_e32 v1, s7
-; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[10:11]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: half_v7bfloat_kernel_preload_arg:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB23_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB23_0:
-; GFX90a-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x20
-; GFX90a-NEXT: v_mov_b32_e32 v3, 0
-; GFX90a-NEXT: v_mov_b32_e32 v0, s10
-; GFX90a-NEXT: global_store_short v3, v0, s[8:9]
-; GFX90a-NEXT: v_mov_b32_e32 v0, s15
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: global_store_short v3, v0, s[0:1] offset:12
-; GFX90a-NEXT: v_mov_b32_e32 v2, s14
-; GFX90a-NEXT: v_mov_b32_e32 v0, s12
-; GFX90a-NEXT: v_mov_b32_e32 v1, s13
-; GFX90a-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: half_v7bfloat_kernel_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB23_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB23_0:
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x20
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: s_lshr_b32 s2, s12, 16
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s12
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[0:1]
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX90A-NEXT: s_lshr_b32 s3, s13, 16
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[0:1] offset:2
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s13
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[0:1] offset:4
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s3
-; GISEL-GFX90A-NEXT: s_lshr_b32 s6, s14, 16
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[0:1] offset:6
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s14
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[0:1] offset:8
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s6
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[0:1] offset:10
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s15
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[0:1] offset:12
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: half_v7bfloat_kernel_preload_arg:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, s4
-; GFX1250-NEXT: v_dual_mov_b32 v5, s9 :: v_dual_mov_b32 v2, s8
-; GFX1250-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
-; GFX1250-NEXT: s_clause 0x2
-; GFX1250-NEXT: global_store_b16 v3, v4, s[2:3]
-; GFX1250-NEXT: global_store_b16 v3, v5, s[10:11] offset:12
-; GFX1250-NEXT: global_store_b96 v3, v[0:2], s[10:11]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: half_v7bfloat_kernel_preload_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB23_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB23_0:
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-SDAG-NEXT: global_store_short v3, v0, s[2:3]
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, s9
+; GFX942-SDAG-NEXT: global_store_short v3, v0, s[10:11] offset:12
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, s8
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, s6
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s7
+; GFX942-SDAG-NEXT: global_store_dwordx3 v3, v[0:2], s[10:11]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: half_v7bfloat_kernel_preload_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB23_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB23_0:
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: s_lshr_b32 s0, s6, 16
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[10:11]
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX942-GISEL-NEXT: s_lshr_b32 s1, s7, 16
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[10:11] offset:2
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s7
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[10:11] offset:4
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s1
+; GFX942-GISEL-NEXT: s_lshr_b32 s5, s8, 16
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[10:11] offset:6
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s8
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[10:11] offset:8
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[10:11] offset:10
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s9
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[10:11] offset:12
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: half_v7bfloat_kernel_preload_arg:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB23_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB23_0:
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x20
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v3, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, s10
+; GFX90a-SDAG-NEXT: global_store_short v3, v0, s[8:9]
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, s15
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: global_store_short v3, v0, s[0:1] offset:12
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v2, s14
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, s12
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s13
+; GFX90a-SDAG-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: half_v7bfloat_kernel_preload_arg:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB23_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB23_0:
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x20
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s10
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: s_lshr_b32 s2, s12, 16
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s12
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[0:1]
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX90a-GISEL-NEXT: s_lshr_b32 s3, s13, 16
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[0:1] offset:2
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s13
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[0:1] offset:4
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX90a-GISEL-NEXT: s_lshr_b32 s6, s14, 16
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[0:1] offset:6
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s14
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[0:1] offset:8
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[0:1] offset:10
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s15
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[0:1] offset:12
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: half_v7bfloat_kernel_preload_arg:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, s4
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, s9 :: v_dual_mov_b32 v2, s8
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
+; GFX1250-SDAG-NEXT: s_clause 0x2
+; GFX1250-SDAG-NEXT: global_store_b16 v3, v4, s[2:3]
+; GFX1250-SDAG-NEXT: global_store_b16 v3, v5, s[10:11] offset:12
+; GFX1250-SDAG-NEXT: global_store_b96 v3, v[0:2], s[10:11]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: half_v7bfloat_kernel_preload_arg:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v0.l, s4
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX1250-GISEL-NEXT: s_lshr_b32 s0, s6, 16
+; GFX1250-GISEL-NEXT: s_lshr_b32 s1, s7, 16
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v0.h, s0
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v1.l, s7
+; GFX1250-GISEL-NEXT: global_store_b16 v4, v0, s[2:3]
+; GFX1250-GISEL-NEXT: s_wait_xcnt 0x0
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v0.l, s6
+; GFX1250-GISEL-NEXT: s_lshr_b32 s4, s8, 16
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v1.h, s1
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v2.l, s8
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v2.h, s4
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v3.l, s9
+; GFX1250-GISEL-NEXT: s_clause 0x6
+; GFX1250-GISEL-NEXT: global_store_b16 v4, v0, s[10:11]
+; GFX1250-GISEL-NEXT: global_store_d16_hi_b16 v4, v0, s[10:11] offset:2
+; GFX1250-GISEL-NEXT: global_store_b16 v4, v1, s[10:11] offset:4
+; GFX1250-GISEL-NEXT: global_store_d16_hi_b16 v4, v1, s[10:11] offset:6
+; GFX1250-GISEL-NEXT: global_store_b16 v4, v2, s[10:11] offset:8
+; GFX1250-GISEL-NEXT: global_store_d16_hi_b16 v4, v2, s[10:11] offset:10
+; GFX1250-GISEL-NEXT: global_store_b16 v4, v3, s[10:11] offset:12
+; GFX1250-GISEL-NEXT: s_endpgm
store half %in, ptr addrspace(1) %out
store <7 x bfloat> %in2, ptr addrspace(1) %out2
ret void
}
define amdgpu_kernel void @i1_kernel_preload_arg(ptr addrspace(1) inreg %out, i1 inreg %in) #0 {
-; GFX942-LABEL: i1_kernel_preload_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dword s4, s[0:1], 0x8
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB24_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB24_0:
-; GFX942-NEXT: s_and_b32 s0, s4, 1
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s0
-; GFX942-NEXT: global_store_byte v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: i1_kernel_preload_arg:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x8
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB24_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB24_0:
-; GFX90a-NEXT: s_and_b32 s0, s10, 1
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s0
-; GFX90a-NEXT: global_store_byte v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: i1_kernel_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_load_dword s10, s[4:5], 0x8
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB24_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB24_0:
-; GISEL-GFX90A-NEXT: s_and_b32 s0, s10, 1
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_byte v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: i1_kernel_preload_arg:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_and_b32 s0, s4, 1
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
-; GFX1250-NEXT: global_store_b8 v0, v1, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: i1_kernel_preload_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dword s4, s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB24_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB24_0:
+; GFX942-SDAG-NEXT: s_and_b32 s0, s4, 1
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX942-SDAG-NEXT: global_store_byte v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: i1_kernel_preload_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dword s4, s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB24_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB24_0:
+; GFX942-GISEL-NEXT: s_and_b32 s0, s4, 1
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_byte v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: i1_kernel_preload_arg:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_load_dword s10, s[4:5], 0x8
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB24_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB24_0:
+; GFX90a-SDAG-NEXT: s_and_b32 s0, s10, 1
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX90a-SDAG-NEXT: global_store_byte v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: i1_kernel_preload_arg:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_load_dword s10, s[4:5], 0x8
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB24_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB24_0:
+; GFX90a-GISEL-NEXT: s_and_b32 s0, s10, 1
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_byte v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: i1_kernel_preload_arg:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_and_b32 s0, s4, 1
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX1250-SDAG-NEXT: global_store_b8 v0, v1, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: i1_kernel_preload_arg:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_and_b32 s0, s4, 1
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s0
+; GFX1250-GISEL-NEXT: global_store_b8 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
store i1 %in, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @fp128_kernel_preload_arg(ptr addrspace(1) inreg %out, fp128 inreg %in) #0 {
-; GFX942-LABEL: fp128_kernel_preload_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
-; GFX942-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB25_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB25_0:
-; GFX942-NEXT: v_mov_b32_e32 v0, s6
-; GFX942-NEXT: v_mov_b32_e32 v1, s7
-; GFX942-NEXT: v_mov_b32_e32 v2, s8
-; GFX942-NEXT: v_mov_b32_e32 v3, s9
-; GFX942-NEXT: v_mov_b32_e32 v4, 0
-; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: fp128_kernel_preload_arg:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB25_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB25_0:
-; GFX90a-NEXT: v_mov_b32_e32 v0, s12
-; GFX90a-NEXT: v_mov_b32_e32 v1, s13
-; GFX90a-NEXT: v_mov_b32_e32 v2, s14
-; GFX90a-NEXT: v_mov_b32_e32 v3, s15
-; GFX90a-NEXT: v_mov_b32_e32 v4, 0
-; GFX90a-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: fp128_kernel_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB25_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB25_0:
-; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[12:13], s[12:13] op_sel:[0,1]
-; GISEL-GFX90A-NEXT: v_pk_mov_b32 v[2:3], s[14:15], s[14:15] op_sel:[0,1]
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v4, 0
-; GISEL-GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: fp128_kernel_preload_arg:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
-; GFX1250-NEXT: v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v3, s9
-; GFX1250-NEXT: v_mov_b32_e32 v4, 0
-; GFX1250-NEXT: global_store_b128 v4, v[0:3], s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: fp128_kernel_preload_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB25_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB25_0:
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, s6
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s7
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, s8
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, s9
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-SDAG-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: fp128_kernel_preload_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB25_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB25_0:
+; GFX942-GISEL-NEXT: s_mov_b32 s11, s9
+; GFX942-GISEL-NEXT: s_mov_b32 s10, s8
+; GFX942-GISEL-NEXT: s_mov_b32 s9, s7
+; GFX942-GISEL-NEXT: s_mov_b32 s8, s6
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX942-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: fp128_kernel_preload_arg:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB25_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB25_0:
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, s12
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s13
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v2, s14
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v3, s15
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v4, 0
+; GFX90a-SDAG-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: fp128_kernel_preload_arg:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB25_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB25_0:
+; GFX90a-GISEL-NEXT: v_pk_mov_b32 v[0:1], s[12:13], s[12:13] op_sel:[0,1]
+; GFX90a-GISEL-NEXT: v_pk_mov_b32 v[2:3], s[14:15], s[14:15] op_sel:[0,1]
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX90a-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: fp128_kernel_preload_arg:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v3, s9
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v4, 0
+; GFX1250-SDAG-NEXT: global_store_b128 v4, v[0:3], s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: fp128_kernel_preload_arg:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b32 s11, s9
+; GFX1250-GISEL-NEXT: s_mov_b32 s10, s8
+; GFX1250-GISEL-NEXT: s_mov_b32 s9, s7
+; GFX1250-GISEL-NEXT: s_mov_b32 s8, s6
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
+; GFX1250-GISEL-NEXT: global_store_b128 v4, v[0:3], s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
store fp128 %in, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @v7i8_kernel_preload_arg(ptr addrspace(1) inreg %out, <7 x i8> inreg %in) #0 {
-; GFX942-LABEL: v7i8_kernel_preload_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB26_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB26_0:
-; GFX942-NEXT: s_lshr_b32 s1, s4, 24
-; GFX942-NEXT: s_and_b32 s0, s4, 0xffff
-; GFX942-NEXT: s_lshl_b32 s1, s1, 8
-; GFX942-NEXT: s_bfe_u32 s4, s4, 0x80010
-; GFX942-NEXT: s_or_b32 s1, s4, s1
-; GFX942-NEXT: s_lshl_b32 s1, s1, 16
-; GFX942-NEXT: s_or_b32 s0, s0, s1
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s5
-; GFX942-NEXT: global_store_byte_d16_hi v0, v1, s[2:3] offset:6
-; GFX942-NEXT: global_store_short v0, v1, s[2:3] offset:4
-; GFX942-NEXT: v_mov_b32_e32 v1, s0
-; GFX942-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: v7i8_kernel_preload_arg:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB26_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB26_0:
-; GFX90a-NEXT: s_lshr_b32 s1, s10, 24
-; GFX90a-NEXT: s_lshl_b32 s1, s1, 8
-; GFX90a-NEXT: s_bfe_u32 s2, s10, 0x80010
-; GFX90a-NEXT: s_or_b32 s1, s2, s1
-; GFX90a-NEXT: s_and_b32 s0, s10, 0xffff
-; GFX90a-NEXT: s_lshl_b32 s1, s1, 16
-; GFX90a-NEXT: s_or_b32 s0, s0, s1
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s11
-; GFX90a-NEXT: global_store_byte_d16_hi v0, v1, s[8:9] offset:6
-; GFX90a-NEXT: global_store_short v0, v1, s[8:9] offset:4
-; GFX90a-NEXT: v_mov_b32_e32 v1, s0
-; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: v7i8_kernel_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB26_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB26_0:
-; GISEL-GFX90A-NEXT: s_and_b32 s2, 0xffff, s10
-; GISEL-GFX90A-NEXT: s_lshr_b32 s2, s2, 8
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: s_lshr_b32 s0, s10, 16
-; GISEL-GFX90A-NEXT: global_store_byte v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX90A-NEXT: s_lshr_b32 s3, s10, 24
-; GISEL-GFX90A-NEXT: global_store_byte v1, v0, s[8:9] offset:1
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: s_and_b32 s4, 0xffff, s11
-; GISEL-GFX90A-NEXT: global_store_byte v1, v0, s[8:9] offset:2
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s3
-; GISEL-GFX90A-NEXT: s_lshr_b32 s4, s4, 8
-; GISEL-GFX90A-NEXT: global_store_byte v1, v0, s[8:9] offset:3
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s11
-; GISEL-GFX90A-NEXT: s_lshr_b32 s1, s11, 16
-; GISEL-GFX90A-NEXT: global_store_byte v1, v0, s[8:9] offset:4
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s4
-; GISEL-GFX90A-NEXT: global_store_byte v1, v0, s[8:9] offset:5
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s1
-; GISEL-GFX90A-NEXT: global_store_byte v1, v0, s[8:9] offset:6
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: v7i8_kernel_preload_arg:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_pack_lh_b32_b16 s0, 0, s4
-; GFX1250-NEXT: s_and_b32 s1, s4, 0xffff
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s5
-; GFX1250-NEXT: s_or_b32 s0, s1, s0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_mov_b32_e32 v2, s0
-; GFX1250-NEXT: s_clause 0x2
-; GFX1250-NEXT: global_store_d16_hi_b8 v0, v1, s[2:3] offset:6
-; GFX1250-NEXT: global_store_b16 v0, v1, s[2:3] offset:4
-; GFX1250-NEXT: global_store_b32 v0, v2, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: v7i8_kernel_preload_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB26_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB26_0:
+; GFX942-SDAG-NEXT: s_lshr_b32 s1, s4, 24
+; GFX942-SDAG-NEXT: s_and_b32 s0, s4, 0xffff
+; GFX942-SDAG-NEXT: s_lshl_b32 s1, s1, 8
+; GFX942-SDAG-NEXT: s_bfe_u32 s4, s4, 0x80010
+; GFX942-SDAG-NEXT: s_or_b32 s1, s4, s1
+; GFX942-SDAG-NEXT: s_lshl_b32 s1, s1, 16
+; GFX942-SDAG-NEXT: s_or_b32 s0, s0, s1
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s5
+; GFX942-SDAG-NEXT: global_store_byte_d16_hi v0, v1, s[2:3] offset:6
+; GFX942-SDAG-NEXT: global_store_short v0, v1, s[2:3] offset:4
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: v7i8_kernel_preload_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB26_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB26_0:
+; GFX942-GISEL-NEXT: s_and_b32 s6, 0xffff, s4
+; GFX942-GISEL-NEXT: s_lshr_b32 s6, s6, 8
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: s_lshr_b32 s0, s4, 16
+; GFX942-GISEL-NEXT: global_store_byte v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX942-GISEL-NEXT: s_lshr_b32 s7, s4, 24
+; GFX942-GISEL-NEXT: global_store_byte v1, v0, s[2:3] offset:1
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX942-GISEL-NEXT: s_and_b32 s8, 0xffff, s5
+; GFX942-GISEL-NEXT: global_store_byte v1, v0, s[2:3] offset:2
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s7
+; GFX942-GISEL-NEXT: s_lshr_b32 s8, s8, 8
+; GFX942-GISEL-NEXT: global_store_byte v1, v0, s[2:3] offset:3
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; GFX942-GISEL-NEXT: s_lshr_b32 s1, s5, 16
+; GFX942-GISEL-NEXT: global_store_byte v1, v0, s[2:3] offset:4
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s8
+; GFX942-GISEL-NEXT: global_store_byte v1, v0, s[2:3] offset:5
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s1
+; GFX942-GISEL-NEXT: global_store_byte v1, v0, s[2:3] offset:6
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: v7i8_kernel_preload_arg:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB26_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB26_0:
+; GFX90a-SDAG-NEXT: s_lshr_b32 s1, s10, 24
+; GFX90a-SDAG-NEXT: s_lshl_b32 s1, s1, 8
+; GFX90a-SDAG-NEXT: s_bfe_u32 s2, s10, 0x80010
+; GFX90a-SDAG-NEXT: s_or_b32 s1, s2, s1
+; GFX90a-SDAG-NEXT: s_and_b32 s0, s10, 0xffff
+; GFX90a-SDAG-NEXT: s_lshl_b32 s1, s1, 16
+; GFX90a-SDAG-NEXT: s_or_b32 s0, s0, s1
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s11
+; GFX90a-SDAG-NEXT: global_store_byte_d16_hi v0, v1, s[8:9] offset:6
+; GFX90a-SDAG-NEXT: global_store_short v0, v1, s[8:9] offset:4
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: v7i8_kernel_preload_arg:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB26_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB26_0:
+; GFX90a-GISEL-NEXT: s_and_b32 s2, 0xffff, s10
+; GFX90a-GISEL-NEXT: s_lshr_b32 s2, s2, 8
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s10
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: s_lshr_b32 s0, s10, 16
+; GFX90a-GISEL-NEXT: global_store_byte v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX90a-GISEL-NEXT: s_lshr_b32 s3, s10, 24
+; GFX90a-GISEL-NEXT: global_store_byte v1, v0, s[8:9] offset:1
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: s_and_b32 s4, 0xffff, s11
+; GFX90a-GISEL-NEXT: global_store_byte v1, v0, s[8:9] offset:2
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX90a-GISEL-NEXT: s_lshr_b32 s4, s4, 8
+; GFX90a-GISEL-NEXT: global_store_byte v1, v0, s[8:9] offset:3
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s11
+; GFX90a-GISEL-NEXT: s_lshr_b32 s1, s11, 16
+; GFX90a-GISEL-NEXT: global_store_byte v1, v0, s[8:9] offset:4
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX90a-GISEL-NEXT: global_store_byte v1, v0, s[8:9] offset:5
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s1
+; GFX90a-GISEL-NEXT: global_store_byte v1, v0, s[8:9] offset:6
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: v7i8_kernel_preload_arg:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_pack_lh_b32_b16 s0, 0, s4
+; GFX1250-SDAG-NEXT: s_and_b32 s1, s4, 0xffff
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s5
+; GFX1250-SDAG-NEXT: s_or_b32 s0, s1, s0
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, s0
+; GFX1250-SDAG-NEXT: s_clause 0x2
+; GFX1250-SDAG-NEXT: global_store_d16_hi_b8 v0, v1, s[2:3] offset:6
+; GFX1250-SDAG-NEXT: global_store_b16 v0, v1, s[2:3] offset:4
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v2, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: v7i8_kernel_preload_arg:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_and_b32 s1, 0xffff, s4
+; GFX1250-GISEL-NEXT: s_lshr_b32 s0, s4, 16
+; GFX1250-GISEL-NEXT: s_lshr_b32 s1, s1, 8
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, 0
+; GFX1250-GISEL-NEXT: s_and_b32 s7, 0xffff, s5
+; GFX1250-GISEL-NEXT: s_lshr_b32 s8, s0, 8
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v3, s0
+; GFX1250-GISEL-NEXT: s_lshr_b32 s6, s5, 16
+; GFX1250-GISEL-NEXT: s_lshr_b32 s7, s7, 8
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s5
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, s7 :: v_dual_mov_b32 v7, s6
+; GFX1250-GISEL-NEXT: s_clause 0x6
+; GFX1250-GISEL-NEXT: global_store_b8 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: global_store_b8 v1, v2, s[2:3] offset:1
+; GFX1250-GISEL-NEXT: global_store_b8 v1, v3, s[2:3] offset:2
+; GFX1250-GISEL-NEXT: global_store_b8 v1, v4, s[2:3] offset:3
+; GFX1250-GISEL-NEXT: global_store_b8 v1, v5, s[2:3] offset:4
+; GFX1250-GISEL-NEXT: global_store_b8 v1, v6, s[2:3] offset:5
+; GFX1250-GISEL-NEXT: global_store_b8 v1, v7, s[2:3] offset:6
+; GFX1250-GISEL-NEXT: s_endpgm
store <7 x i8> %in, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @v7half_kernel_preload_arg(ptr addrspace(1) inreg %out, <7 x half> inreg %in) #0 {
-; GFX942-LABEL: v7half_kernel_preload_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
-; GFX942-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB27_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB27_0:
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-NEXT: v_mov_b32_e32 v0, s9
-; GFX942-NEXT: global_store_short v3, v0, s[2:3] offset:12
-; GFX942-NEXT: v_mov_b32_e32 v2, s8
-; GFX942-NEXT: v_mov_b32_e32 v0, s6
-; GFX942-NEXT: v_mov_b32_e32 v1, s7
-; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: v7half_kernel_preload_arg:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB27_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB27_0:
-; GFX90a-NEXT: v_mov_b32_e32 v3, 0
-; GFX90a-NEXT: v_mov_b32_e32 v0, s15
-; GFX90a-NEXT: global_store_short v3, v0, s[8:9] offset:12
-; GFX90a-NEXT: v_mov_b32_e32 v2, s14
-; GFX90a-NEXT: v_mov_b32_e32 v0, s12
-; GFX90a-NEXT: v_mov_b32_e32 v1, s13
-; GFX90a-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: v7half_kernel_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB27_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB27_0:
-; GISEL-GFX90A-NEXT: s_lshr_b32 s0, s12, 16
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s12
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: s_lshr_b32 s1, s13, 16
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9] offset:2
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s13
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9] offset:4
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s1
-; GISEL-GFX90A-NEXT: s_lshr_b32 s2, s14, 16
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9] offset:6
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s14
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9] offset:8
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9] offset:10
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s15
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9] offset:12
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: v7half_kernel_preload_arg:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, s9
-; GFX1250-NEXT: v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v0, s6
-; GFX1250-NEXT: v_mov_b32_e32 v1, s7
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: global_store_b16 v3, v4, s[2:3] offset:12
-; GFX1250-NEXT: global_store_b96 v3, v[0:2], s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: v7half_kernel_preload_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB27_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB27_0:
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, s9
+; GFX942-SDAG-NEXT: global_store_short v3, v0, s[2:3] offset:12
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, s8
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, s6
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s7
+; GFX942-SDAG-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: v7half_kernel_preload_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB27_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB27_0:
+; GFX942-GISEL-NEXT: s_lshr_b32 s0, s6, 16
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX942-GISEL-NEXT: s_lshr_b32 s1, s7, 16
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[2:3] offset:2
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s7
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[2:3] offset:4
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s1
+; GFX942-GISEL-NEXT: s_lshr_b32 s4, s8, 16
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[2:3] offset:6
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s8
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[2:3] offset:8
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[2:3] offset:10
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s9
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[2:3] offset:12
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: v7half_kernel_preload_arg:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB27_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB27_0:
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v3, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, s15
+; GFX90a-SDAG-NEXT: global_store_short v3, v0, s[8:9] offset:12
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v2, s14
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, s12
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s13
+; GFX90a-SDAG-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: v7half_kernel_preload_arg:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB27_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB27_0:
+; GFX90a-GISEL-NEXT: s_lshr_b32 s0, s12, 16
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s12
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: s_lshr_b32 s1, s13, 16
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[8:9] offset:2
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s13
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[8:9] offset:4
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s1
+; GFX90a-GISEL-NEXT: s_lshr_b32 s2, s14, 16
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[8:9] offset:6
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s14
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[8:9] offset:8
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[8:9] offset:10
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s15
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[8:9] offset:12
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: v7half_kernel_preload_arg:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, s9
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v0, s6
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, s7
+; GFX1250-SDAG-NEXT: s_clause 0x1
+; GFX1250-SDAG-NEXT: global_store_b16 v3, v4, s[2:3] offset:12
+; GFX1250-SDAG-NEXT: global_store_b96 v3, v[0:2], s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: v7half_kernel_preload_arg:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_lshr_b32 s0, s6, 16
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v0.l, s6
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX1250-GISEL-NEXT: s_lshr_b32 s1, s7, 16
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v0.h, s0
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v1.l, s7
+; GFX1250-GISEL-NEXT: s_lshr_b32 s4, s8, 16
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v1.h, s1
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v2.l, s8
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v2.h, s4
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v3.l, s9
+; GFX1250-GISEL-NEXT: s_clause 0x6
+; GFX1250-GISEL-NEXT: global_store_b16 v4, v0, s[2:3]
+; GFX1250-GISEL-NEXT: global_store_d16_hi_b16 v4, v0, s[2:3] offset:2
+; GFX1250-GISEL-NEXT: global_store_b16 v4, v1, s[2:3] offset:4
+; GFX1250-GISEL-NEXT: global_store_d16_hi_b16 v4, v1, s[2:3] offset:6
+; GFX1250-GISEL-NEXT: global_store_b16 v4, v2, s[2:3] offset:8
+; GFX1250-GISEL-NEXT: global_store_d16_hi_b16 v4, v2, s[2:3] offset:10
+; GFX1250-GISEL-NEXT: global_store_b16 v4, v3, s[2:3] offset:12
+; GFX1250-GISEL-NEXT: s_endpgm
store <7 x half> %in, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @i16_i32_kernel_preload_arg(ptr addrspace(1) inreg %out, i16 inreg %in, i32 inreg %in2, ptr addrspace(1) inreg %out2) #0 {
-; GFX942-LABEL: i16_i32_kernel_preload_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB28_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB28_0:
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s4
-; GFX942-NEXT: global_store_short v0, v1, s[2:3]
-; GFX942-NEXT: v_mov_b32_e32 v1, s5
-; GFX942-NEXT: global_store_dword v0, v1, s[6:7]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: i16_i32_kernel_preload_arg:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GFX90a-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB28_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB28_0:
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s10
-; GFX90a-NEXT: global_store_short v0, v1, s[8:9]
-; GFX90a-NEXT: v_mov_b32_e32 v1, s11
-; GFX90a-NEXT: global_store_dword v0, v1, s[12:13]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: i16_i32_kernel_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB28_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB28_0:
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s11
-; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[12:13]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: i16_i32_kernel_preload_arg:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
-; GFX1250-NEXT: v_mov_b32_e32 v2, s5
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: global_store_b16 v0, v1, s[2:3]
-; GFX1250-NEXT: global_store_b32 v0, v2, s[6:7]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: i16_i32_kernel_preload_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB28_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB28_0:
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s4
+; GFX942-SDAG-NEXT: global_store_short v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s5
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[6:7]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: i16_i32_kernel_preload_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB28_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB28_0:
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; GFX942-GISEL-NEXT: global_store_dword v1, v0, s[6:7]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: i16_i32_kernel_preload_arg:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB28_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB28_0:
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s10
+; GFX90a-SDAG-NEXT: global_store_short v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s11
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[12:13]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: i16_i32_kernel_preload_arg:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB28_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB28_0:
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s10
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s11
+; GFX90a-GISEL-NEXT: global_store_dword v1, v0, s[12:13]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: i16_i32_kernel_preload_arg:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, s5
+; GFX1250-SDAG-NEXT: s_clause 0x1
+; GFX1250-SDAG-NEXT: global_store_b16 v0, v1, s[2:3]
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v2, s[6:7]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: i16_i32_kernel_preload_arg:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v0.l, s4
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s5
+; GFX1250-GISEL-NEXT: s_clause 0x1
+; GFX1250-GISEL-NEXT: global_store_b16 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: global_store_b32 v1, v2, s[6:7]
+; GFX1250-GISEL-NEXT: s_endpgm
store i16 %in, ptr addrspace(1) %out
store i32 %in2, ptr addrspace(1) %out2
ret void
}
define amdgpu_kernel void @i16_v3i32_kernel_preload_arg(ptr addrspace(1) inreg %out, i16 inreg %in, <3 x i32> inreg %in2, ptr addrspace(1) inreg %out2) #0 {
-; GFX942-LABEL: i16_v3i32_kernel_preload_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x8
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB29_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB29_0:
-; GFX942-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-NEXT: v_mov_b32_e32 v4, s4
-; GFX942-NEXT: v_mov_b32_e32 v0, s6
-; GFX942-NEXT: v_mov_b32_e32 v1, s7
-; GFX942-NEXT: v_mov_b32_e32 v2, s8
-; GFX942-NEXT: global_store_short v3, v4, s[2:3]
-; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[10:11]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: i16_v3i32_kernel_preload_arg:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB29_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB29_0:
-; GFX90a-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x20
-; GFX90a-NEXT: v_mov_b32_e32 v3, 0
-; GFX90a-NEXT: v_mov_b32_e32 v4, s10
-; GFX90a-NEXT: v_mov_b32_e32 v0, s12
-; GFX90a-NEXT: v_mov_b32_e32 v1, s13
-; GFX90a-NEXT: v_mov_b32_e32 v2, s14
-; GFX90a-NEXT: global_store_short v3, v4, s[8:9]
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: i16_v3i32_kernel_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB29_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB29_0:
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x20
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v3, 0
-; GISEL-GFX90A-NEXT: global_store_short v3, v0, s[8:9]
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s12
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, s13
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v2, s14
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: i16_v3i32_kernel_preload_arg:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, s4
-; GFX1250-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
-; GFX1250-NEXT: v_mov_b32_e32 v2, s8
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: global_store_b16 v3, v4, s[2:3]
-; GFX1250-NEXT: global_store_b96 v3, v[0:2], s[10:11]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: i16_v3i32_kernel_preload_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB29_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB29_0:
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v4, s4
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, s6
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s7
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, s8
+; GFX942-SDAG-NEXT: global_store_short v3, v4, s[2:3]
+; GFX942-SDAG-NEXT: global_store_dwordx3 v3, v[0:2], s[10:11]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: i16_v3i32_kernel_preload_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB29_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB29_0:
+; GFX942-GISEL-NEXT: s_mov_b32 s12, s6
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX942-GISEL-NEXT: s_mov_b32 s14, s8
+; GFX942-GISEL-NEXT: s_mov_b32 s13, s7
+; GFX942-GISEL-NEXT: global_store_short v3, v0, s[2:3]
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s12
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, s13
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v2, s14
+; GFX942-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[10:11]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: i16_v3i32_kernel_preload_arg:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB29_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB29_0:
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x20
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v3, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v4, s10
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, s12
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s13
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v2, s14
+; GFX90a-SDAG-NEXT: global_store_short v3, v4, s[8:9]
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: i16_v3i32_kernel_preload_arg:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB29_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB29_0:
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x20
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s10
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX90a-GISEL-NEXT: global_store_short v3, v0, s[8:9]
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s12
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, s13
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v2, s14
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: i16_v3i32_kernel_preload_arg:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, s4
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, s8
+; GFX1250-SDAG-NEXT: s_clause 0x1
+; GFX1250-SDAG-NEXT: global_store_b16 v3, v4, s[2:3]
+; GFX1250-SDAG-NEXT: global_store_b96 v3, v[0:2], s[10:11]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: i16_v3i32_kernel_preload_arg:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b32 s12, s6
+; GFX1250-GISEL-NEXT: s_mov_b32 s14, s8
+; GFX1250-GISEL-NEXT: s_mov_b32 s13, s7
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v0.l, s4
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s12
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v3, s13 :: v_dual_mov_b32 v4, s14
+; GFX1250-GISEL-NEXT: s_clause 0x1
+; GFX1250-GISEL-NEXT: global_store_b16 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: global_store_b96 v1, v[2:4], s[10:11]
+; GFX1250-GISEL-NEXT: s_endpgm
store i16 %in, ptr addrspace(1) %out
store <3 x i32> %in2, ptr addrspace(1) %out2
ret void
}
define amdgpu_kernel void @i16_i16_kernel_preload_arg(ptr addrspace(1) inreg %out, i16 inreg %in, i16 inreg %in2, ptr addrspace(1) inreg %out2) #0 {
-; GFX942-LABEL: i16_i16_kernel_preload_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB30_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB30_0:
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s4
-; GFX942-NEXT: global_store_short v0, v1, s[2:3]
-; GFX942-NEXT: global_store_short_d16_hi v0, v1, s[6:7]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: i16_i16_kernel_preload_arg:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GFX90a-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB30_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB30_0:
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s10
-; GFX90a-NEXT: global_store_short v0, v1, s[8:9]
-; GFX90a-NEXT: global_store_short_d16_hi v0, v1, s[12:13]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: i16_i16_kernel_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB30_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB30_0:
-; GISEL-GFX90A-NEXT: s_lshr_b32 s0, s10, 16
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[12:13]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: i16_i16_kernel_preload_arg:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: global_store_b16 v0, v1, s[2:3]
-; GFX1250-NEXT: global_store_d16_hi_b16 v0, v1, s[6:7]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: i16_i16_kernel_preload_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB30_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB30_0:
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s4
+; GFX942-SDAG-NEXT: global_store_short v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: global_store_short_d16_hi v0, v1, s[6:7]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: i16_i16_kernel_preload_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB30_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB30_0:
+; GFX942-GISEL-NEXT: s_lshr_b32 s0, s4, 16
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[6:7]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: i16_i16_kernel_preload_arg:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB30_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB30_0:
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s10
+; GFX90a-SDAG-NEXT: global_store_short v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: global_store_short_d16_hi v0, v1, s[12:13]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: i16_i16_kernel_preload_arg:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB30_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB30_0:
+; GFX90a-GISEL-NEXT: s_lshr_b32 s0, s10, 16
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s10
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[12:13]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: i16_i16_kernel_preload_arg:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
+; GFX1250-SDAG-NEXT: s_clause 0x1
+; GFX1250-SDAG-NEXT: global_store_b16 v0, v1, s[2:3]
+; GFX1250-SDAG-NEXT: global_store_d16_hi_b16 v0, v1, s[6:7]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: i16_i16_kernel_preload_arg:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_lshr_b32 s0, s4, 16
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v0.l, s4
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v0.h, s0
+; GFX1250-GISEL-NEXT: s_clause 0x1
+; GFX1250-GISEL-NEXT: global_store_b16 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: global_store_d16_hi_b16 v1, v0, s[6:7]
+; GFX1250-GISEL-NEXT: s_endpgm
store i16 %in, ptr addrspace(1) %out
store i16 %in2, ptr addrspace(1) %out2
ret void
}
define amdgpu_kernel void @i16_v2i8_kernel_preload_arg(ptr addrspace(1) inreg %out, i16 inreg %in, <2 x i8> inreg %in2, ptr addrspace(1) inreg %out2) #0 {
-; GFX942-LABEL: i16_v2i8_kernel_preload_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB31_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB31_0:
-; GFX942-NEXT: s_lshr_b32 s0, s4, 24
-; GFX942-NEXT: s_lshl_b32 s0, s0, 8
-; GFX942-NEXT: s_bfe_u32 s1, s4, 0x80010
-; GFX942-NEXT: s_or_b32 s0, s1, s0
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s4
-; GFX942-NEXT: global_store_short v0, v1, s[2:3]
-; GFX942-NEXT: v_mov_b32_e32 v1, s0
-; GFX942-NEXT: global_store_short v0, v1, s[6:7]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: i16_v2i8_kernel_preload_arg:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GFX90a-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB31_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB31_0:
-; GFX90a-NEXT: s_lshr_b32 s0, s10, 24
-; GFX90a-NEXT: s_lshl_b32 s0, s0, 8
-; GFX90a-NEXT: s_bfe_u32 s1, s10, 0x80010
-; GFX90a-NEXT: s_or_b32 s0, s1, s0
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s10
-; GFX90a-NEXT: global_store_short v0, v1, s[8:9]
-; GFX90a-NEXT: v_mov_b32_e32 v1, s0
-; GFX90a-NEXT: global_store_short v0, v1, s[12:13]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: i16_v2i8_kernel_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB31_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB31_0:
-; GISEL-GFX90A-NEXT: s_lshr_b32 s0, s10, 16
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s10
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: global_store_short v1, v0, s[12:13]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: i16_v2i8_kernel_preload_arg:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
-; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: global_store_b16 v0, v1, s[2:3]
-; GFX1250-NEXT: global_store_d16_hi_b16 v0, v1, s[6:7]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: i16_v2i8_kernel_preload_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB31_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB31_0:
+; GFX942-SDAG-NEXT: s_lshr_b32 s0, s4, 24
+; GFX942-SDAG-NEXT: s_lshl_b32 s0, s0, 8
+; GFX942-SDAG-NEXT: s_bfe_u32 s1, s4, 0x80010
+; GFX942-SDAG-NEXT: s_or_b32 s0, s1, s0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s4
+; GFX942-SDAG-NEXT: global_store_short v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX942-SDAG-NEXT: global_store_short v0, v1, s[6:7]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: i16_v2i8_kernel_preload_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB31_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB31_0:
+; GFX942-GISEL-NEXT: s_lshr_b32 s0, s4, 16
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX942-GISEL-NEXT: global_store_short v1, v0, s[6:7]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: i16_v2i8_kernel_preload_arg:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB31_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB31_0:
+; GFX90a-SDAG-NEXT: s_lshr_b32 s0, s10, 24
+; GFX90a-SDAG-NEXT: s_lshl_b32 s0, s0, 8
+; GFX90a-SDAG-NEXT: s_bfe_u32 s1, s10, 0x80010
+; GFX90a-SDAG-NEXT: s_or_b32 s0, s1, s0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s10
+; GFX90a-SDAG-NEXT: global_store_short v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX90a-SDAG-NEXT: global_store_short v0, v1, s[12:13]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: i16_v2i8_kernel_preload_arg:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB31_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB31_0:
+; GFX90a-GISEL-NEXT: s_lshr_b32 s0, s10, 16
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s10
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: global_store_short v1, v0, s[12:13]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: i16_v2i8_kernel_preload_arg:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
+; GFX1250-SDAG-NEXT: s_clause 0x1
+; GFX1250-SDAG-NEXT: global_store_b16 v0, v1, s[2:3]
+; GFX1250-SDAG-NEXT: global_store_d16_hi_b16 v0, v1, s[6:7]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: i16_v2i8_kernel_preload_arg:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_lshr_b32 s0, s4, 16
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v0.l, s4
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v0.h, s0
+; GFX1250-GISEL-NEXT: s_clause 0x1
+; GFX1250-GISEL-NEXT: global_store_b16 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: global_store_d16_hi_b16 v1, v0, s[6:7]
+; GFX1250-GISEL-NEXT: s_endpgm
store i16 %in, ptr addrspace(1) %out
store <2 x i8> %in2, ptr addrspace(1) %out2
ret void
@@ -2157,124 +3008,177 @@ define amdgpu_kernel void @i16_v2i8_kernel_preload_arg(ptr addrspace(1) inreg %o
; The second argument is not expected to be preloaded with the current behavior.
define amdgpu_kernel void @i32_ptr1_i32_staggered_preload_arg(i32 inreg %arg0, ptr addrspace(1) %out, i32 inreg %arg1) #0 {
-; GFX942-LABEL: i32_ptr1_i32_staggered_preload_arg:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dword s2, s[0:1], 0x0
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB32_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB32_0:
-; GFX942-NEXT: s_load_dword s3, s[0:1], 0x10
-; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_add_i32 s0, s2, s3
-; GFX942-NEXT: v_mov_b32_e32 v1, s0
-; GFX942-NEXT: global_store_dword v0, v1, s[4:5]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: i32_ptr1_i32_staggered_preload_arg:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dword s8, s[4:5], 0x0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB32_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB32_0:
-; GFX90a-NEXT: s_load_dword s2, s[4:5], 0x10
-; GFX90a-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_add_i32 s2, s8, s2
-; GFX90a-NEXT: v_mov_b32_e32 v1, s2
-; GFX90a-NEXT: global_store_dword v0, v1, s[0:1]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: i32_ptr1_i32_staggered_preload_arg:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dword s8, s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB32_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB32_0:
-; GISEL-GFX90A-NEXT: s_load_dword s2, s[4:5], 0x10
-; GISEL-GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_add_i32 s2, s8, s2
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: i32_ptr1_i32_staggered_preload_arg:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_load_b96 s[4:6], s[0:1], 0x8 nv
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_add_co_i32 s0, s2, s6
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
-; GFX1250-NEXT: global_store_b32 v0, v1, s[4:5]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: i32_ptr1_i32_staggered_preload_arg:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dword s2, s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB32_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB32_0:
+; GFX942-SDAG-NEXT: s_load_dword s3, s[0:1], 0x10
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_add_i32 s0, s2, s3
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[4:5]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: i32_ptr1_i32_staggered_preload_arg:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dword s2, s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB32_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB32_0:
+; GFX942-GISEL-NEXT: s_load_dword s3, s[0:1], 0x10
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_add_i32 s0, s2, s3
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX942-GISEL-NEXT: global_store_dword v1, v0, s[4:5]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: i32_ptr1_i32_staggered_preload_arg:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dword s8, s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB32_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB32_0:
+; GFX90a-SDAG-NEXT: s_load_dword s2, s[4:5], 0x10
+; GFX90a-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_add_i32 s2, s8, s2
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s2
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: i32_ptr1_i32_staggered_preload_arg:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dword s8, s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB32_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB32_0:
+; GFX90a-GISEL-NEXT: s_load_dword s2, s[4:5], 0x10
+; GFX90a-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_add_i32 s2, s8, s2
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX90a-GISEL-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: i32_ptr1_i32_staggered_preload_arg:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_load_b96 s[4:6], s[0:1], 0x8 nv
+; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX1250-SDAG-NEXT: s_add_co_i32 s0, s2, s6
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[4:5]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: i32_ptr1_i32_staggered_preload_arg:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_load_b96 s[4:6], s[0:1], 0x8 nv
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX1250-GISEL-NEXT: s_add_co_i32 s0, s2, s6
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[4:5]
+; GFX1250-GISEL-NEXT: s_endpgm
%add = add i32 %arg0, %arg1
store i32 %add, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @ptr1_i8_trailing_unused(ptr addrspace(1) inreg %out, i8 inreg %arg0, i32 inreg %unused) #0 {
-; GFX942-LABEL: ptr1_i8_trailing_unused:
-; GFX942: ; %bb.1:
-; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
-; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
-; GFX942-NEXT: s_waitcnt lgkmcnt(0)
-; GFX942-NEXT: s_branch .LBB33_0
-; GFX942-NEXT: .p2align 8
-; GFX942-NEXT: ; %bb.2:
-; GFX942-NEXT: .LBB33_0:
-; GFX942-NEXT: s_and_b32 s0, s4, 0xff
-; GFX942-NEXT: v_mov_b32_e32 v0, 0
-; GFX942-NEXT: v_mov_b32_e32 v1, s0
-; GFX942-NEXT: global_store_dword v0, v1, s[2:3]
-; GFX942-NEXT: s_endpgm
-;
-; GFX90a-LABEL: ptr1_i8_trailing_unused:
-; GFX90a: ; %bb.1:
-; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GFX90a-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90a-NEXT: s_branch .LBB33_0
-; GFX90a-NEXT: .p2align 8
-; GFX90a-NEXT: ; %bb.2:
-; GFX90a-NEXT: .LBB33_0:
-; GFX90a-NEXT: s_and_b32 s0, s10, 0xff
-; GFX90a-NEXT: v_mov_b32_e32 v0, 0
-; GFX90a-NEXT: v_mov_b32_e32 v1, s0
-; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]
-; GFX90a-NEXT: s_endpgm
-;
-; GISEL-GFX90A-LABEL: ptr1_i8_trailing_unused:
-; GISEL-GFX90A: ; %bb.1:
-; GISEL-GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
-; GISEL-GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX90A-NEXT: s_branch .LBB33_0
-; GISEL-GFX90A-NEXT: .p2align 8
-; GISEL-GFX90A-NEXT: ; %bb.2:
-; GISEL-GFX90A-NEXT: .LBB33_0:
-; GISEL-GFX90A-NEXT: s_and_b32 s0, s10, 0xff
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX90A-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX90A-NEXT: global_store_dword v1, v0, s[8:9]
-; GISEL-GFX90A-NEXT: s_endpgm
-;
-; GFX1250-LABEL: ptr1_i8_trailing_unused:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_and_b32 s0, s4, 0xff
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
-; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]
-; GFX1250-NEXT: s_endpgm
+; GFX942-SDAG-LABEL: ptr1_i8_trailing_unused:
+; GFX942-SDAG: ; %bb.1:
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-SDAG-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-SDAG-NEXT: s_branch .LBB33_0
+; GFX942-SDAG-NEXT: .p2align 8
+; GFX942-SDAG-NEXT: ; %bb.2:
+; GFX942-SDAG-NEXT: .LBB33_0:
+; GFX942-SDAG-NEXT: s_and_b32 s0, s4, 0xff
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX942-SDAG-NEXT: global_store_dword v0, v1, s[2:3]
+; GFX942-SDAG-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: ptr1_i8_trailing_unused:
+; GFX942-GISEL: ; %bb.1:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: s_branch .LBB33_0
+; GFX942-GISEL-NEXT: .p2align 8
+; GFX942-GISEL-NEXT: ; %bb.2:
+; GFX942-GISEL-NEXT: .LBB33_0:
+; GFX942-GISEL-NEXT: s_and_b32 s0, s4, 0xff
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX942-GISEL-NEXT: s_endpgm
+;
+; GFX90a-SDAG-LABEL: ptr1_i8_trailing_unused:
+; GFX90a-SDAG: ; %bb.1:
+; GFX90a-SDAG-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-SDAG-NEXT: s_branch .LBB33_0
+; GFX90a-SDAG-NEXT: .p2align 8
+; GFX90a-SDAG-NEXT: ; %bb.2:
+; GFX90a-SDAG-NEXT: .LBB33_0:
+; GFX90a-SDAG-NEXT: s_and_b32 s0, s10, 0xff
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX90a-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; GFX90a-SDAG-NEXT: global_store_dword v0, v1, s[8:9]
+; GFX90a-SDAG-NEXT: s_endpgm
+;
+; GFX90a-GISEL-LABEL: ptr1_i8_trailing_unused:
+; GFX90a-GISEL: ; %bb.1:
+; GFX90a-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX90a-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90a-GISEL-NEXT: s_branch .LBB33_0
+; GFX90a-GISEL-NEXT: .p2align 8
+; GFX90a-GISEL-NEXT: ; %bb.2:
+; GFX90a-GISEL-NEXT: .LBB33_0:
+; GFX90a-GISEL-NEXT: s_and_b32 s0, s10, 0xff
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX90a-GISEL-NEXT: global_store_dword v1, v0, s[8:9]
+; GFX90a-GISEL-NEXT: s_endpgm
+;
+; GFX1250-SDAG-LABEL: ptr1_i8_trailing_unused:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_and_b32 s0, s4, 0xff
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX1250-SDAG-NEXT: global_store_b32 v0, v1, s[2:3]
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: ptr1_i8_trailing_unused:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_and_b32 s0, s4, 0xff
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s0
+; GFX1250-GISEL-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX1250-GISEL-NEXT: s_endpgm
%ext = zext i8 %arg0 to i32
store i32 %ext, ptr addrspace(1) %out
ret void
>From f8452103b74e90ba6f76d58d5ec013d721eca7be Mon Sep 17 00:00:00 2001
From: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
Date: Wed, 1 Jul 2026 17:06:05 +0530
Subject: [PATCH 4/6] [AMDGPU][GlobalISel] Address kernarg preload review
comments
Remove helper-based preload materialization and derive preloaded argument values from the IR type while still copying rounded SGPR storage widths. Add the 32-bit address-space pointer coverage requested in review and refresh the affected generated checks.
Co-authored-by: GPT-5 Codex <noreply at openai.com>
Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
---
llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp | 101 +++++---------
.../irtranslator-preload-kernargs.ll | 93 +++++++------
.../AMDGPU/preload-implicit-kernargs.ll | 14 +-
llvm/test/CodeGen/AMDGPU/preload-kernargs.ll | 129 +++++++++---------
4 files changed, 153 insertions(+), 184 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
index 4b76a06a7f22d..8f59ab142c800 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
@@ -20,7 +20,6 @@
#include "llvm/CodeGen/Analysis.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
-#include "llvm/CodeGen/GlobalISel/Utils.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/PseudoSourceValueManager.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
@@ -298,67 +297,38 @@ struct AMDGPUOutgoingArgHandler : public AMDGPUOutgoingValueHandler {
}
};
-// Return the virtual register and type for a preloaded physical SGPR live-in.
-static std::pair<Register, LLT> getPreloadedLiveIn(MachineIRBuilder &B,
- MCRegister PhysReg,
- const SIRegisterInfo &TRI) {
- MachineFunction &MF = B.getMF();
- const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
- const TargetRegisterClass *RC = TRI.getPhysRegBaseClass(PhysReg);
- assert(RC && "expected a register class for preload SGPR");
- LLT RegTy = LLT::scalar(TRI.getRegSizeInBits(*RC).getFixedValue());
- return {getFunctionLiveInPhysReg(MF, *TII, PhysReg, *RC, B.getDL(), RegTy),
- RegTy};
-}
-
-// Convert raw SGPR preload bits to the type expected by the formal argument.
-static Register adjustPreloadedArgType(MachineIRBuilder &B, Register Src,
- LLT SrcTy, LLT DstTy) {
- if (SrcTy == DstTy)
- return Src;
-
- LLT IntDstTy = (DstTy.isPointer() || DstTy.isVector())
- ? LLT::scalar(DstTy.getSizeInBits())
- : DstTy;
- if (SrcTy.getSizeInBits() != IntDstTy.getSizeInBits())
- Src = B.buildAnyExtOrTrunc(IntDstTy, Src).getReg(0);
-
- if (DstTy.isPointer())
- return B.buildIntToPtr(DstTy, Src).getReg(0);
-
- if (DstTy.isVector())
- return B.buildBitcast(DstTy, Src).getReg(0);
-
- return Src;
-}
-
// Materialize a preloaded kernarg from its assigned SGPRs into DstReg.
static void lowerPreloadedKernArg(MachineIRBuilder &B, Register DstReg,
LLT DstTy, uint64_t Offset, Align Alignment,
- ArrayRef<MCRegister> PreloadRegs,
- const SIRegisterInfo &TRI) {
+ ArrayRef<MCRegister> PreloadRegs) {
assert(!PreloadRegs.empty());
// Kernarg preloads are assigned in 32-bit SGPR units.
const LLT S32 = LLT::scalar(32);
+ LLT IntDstTy = (DstTy.isPointer() || DstTy.isVector())
+ ? LLT::scalar(DstTy.getSizeInBits())
+ : DstTy;
+ auto BuildCopyFromPreload = [&B](LLT Ty, MCRegister Reg) {
+ B.getMBB().addLiveIn(Reg);
+ return B.buildCopy(Ty, Register(Reg)).getReg(0);
+ };
Register Value;
LLT ValueTy;
const bool IsPackedSubDword = DstTy.getSizeInBits() < 32 && Alignment < 4;
if (PreloadRegs.size() == 1) {
- auto [LiveIn, LiveInTy] = getPreloadedLiveIn(B, PreloadRegs[0], TRI);
if (IsPackedSubDword) {
// Extract sub-dword preloads from their containing 32-bit SGPR word.
- Register Raw = B.buildCopy(S32, LiveIn).getReg(0);
+ Register Raw = BuildCopyFromPreload(S32, PreloadRegs[0]);
uint64_t OffsetDiff = Offset - alignDown(Offset, 4);
Register ShiftAmt = B.buildConstant(S32, OffsetDiff * 8).getReg(0);
Value = B.buildLShr(S32, Raw, ShiftAmt).getReg(0);
ValueTy = S32;
} else {
- // A single preload entry may be a 32-bit SGPR or a wider SGPR tuple.
- ValueTy = LiveInTy;
- Value = B.buildCopy(ValueTy, LiveIn).getReg(0);
+ // Copy the physical preload storage width, then narrow to the IR size.
+ ValueTy = LLT::scalar(alignTo(IntDstTy.getSizeInBits(), 32));
+ Value = BuildCopyFromPreload(ValueTy, PreloadRegs[0]);
}
} else {
assert(!IsPackedSubDword && "packed sub-dword preload should use one SGPR");
@@ -366,34 +336,22 @@ static void lowerPreloadedKernArg(MachineIRBuilder &B, Register DstReg,
SmallVector<Register, 4> Regs;
Regs.reserve(PreloadRegs.size());
for (MCRegister Reg : PreloadRegs) {
- Register LiveIn = getPreloadedLiveIn(B, Reg, TRI).first;
- Regs.push_back(B.buildCopy(S32, LiveIn).getReg(0));
+ Regs.push_back(BuildCopyFromPreload(S32, Reg));
}
ValueTy = LLT::scalar(PreloadRegs.size() * 32);
Value = B.buildMergeLikeInstr(ValueTy, Regs).getReg(0);
}
- Register Adjusted = adjustPreloadedArgType(B, Value, ValueTy, DstTy);
- B.buildCopy(DstReg, Adjusted);
-}
+ if (ValueTy.getSizeInBits() != IntDstTy.getSizeInBits())
+ Value = B.buildAnyExtOrTrunc(IntDstTy, Value).getReg(0);
-// CCValAssign records an MVT, so round odd-sized split argument parts to the
-// simple memory type used for kernarg layout.
-static MVT getLocVTForSplitArg(const TargetLowering &TLI, const DataLayout &DL,
- Type *Ty, LLVMContext &Ctx) {
- EVT LocVT = TLI.getValueType(DL, Ty, true);
-
- if (LocVT.isVector() && LocVT.getVectorNumElements() == 1)
- LocVT = LocVT.getScalarType();
-
- if (LocVT.isVector() && !LocVT.isPow2VectorType())
- LocVT = LocVT.getPow2VectorType(Ctx);
- else if (!LocVT.isSimple() && !LocVT.isVector())
- LocVT = LocVT.getRoundIntegerType(Ctx);
+ if (DstTy.isPointer())
+ Value = B.buildIntToPtr(DstTy, Value).getReg(0);
+ else if (DstTy.isVector())
+ Value = B.buildBitcast(DstTy, Value).getReg(0);
- assert(LocVT.isSimple());
- return LocVT.getSimpleVT();
+ B.buildCopy(DstReg, Value);
}
// Assign SGPRs for the contiguous sequence of kernel argument parts marked for
@@ -657,8 +615,6 @@ bool AMDGPUCallLowering::lowerParameter(MachineIRBuilder &B, ArgInfo &Arg,
const bool IsHiddenArg =
IRArg && IRArg->hasAttribute("amdgpu-hidden-argument");
const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
- const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>();
- const SIRegisterInfo *TRI = Subtarget.getRegisterInfo();
const SITargetLowering &TLI = *getTLI<SITargetLowering>();
MachinePointerInfo PtrInfo = TLI.getKernargSegmentPtrInfo(MF);
@@ -678,7 +634,7 @@ bool AMDGPUCallLowering::lowerParameter(MachineIRBuilder &B, ArgInfo &Arg,
auto PreloadArg = Info->getArgInfo().PreloadKernArgs.find(InputArgIndex);
if (PreloadArg != Info->getArgInfo().PreloadKernArgs.end()) {
lowerPreloadedKernArg(B, Arg.Regs[0], ArgTy, Offset, Alignment,
- PreloadArg->getSecond().Regs, *TRI);
+ PreloadArg->getSecond().Regs);
return true;
}
@@ -810,12 +766,17 @@ bool AMDGPUCallLowering::lowerFormalArgumentsKernel(
SplitIdx != NumSplitArgs; ++SplitIdx) {
unsigned InputArgIndex = SplitArgs.size();
ArgSplitArgs[SplitIdx].OrigValue = &Arg;
- MVT LocVT = getLocVTForSplitArg(TLI, DL, ArgSplitArgs[SplitIdx].Ty,
- F.getContext());
+ EVT LocVT = TLI.getValueType(DL, ArgSplitArgs[SplitIdx].Ty, true);
+ if (LocVT.isVector() && LocVT.getVectorNumElements() == 1)
+ LocVT = LocVT.getScalarType();
+ if (LocVT.isVector() && !LocVT.isPow2VectorType())
+ LocVT = LocVT.getPow2VectorType(F.getContext());
+ else if (!LocVT.isSimple() && !LocVT.isVector())
+ LocVT = LocVT.getRoundIntegerType(F.getContext());
CCInfo.addLoc(CCValAssign::getCustomMem(
- InputArgIndex, LocVT,
- ArgOffset + FieldOffsets[SplitIdx].getFixedValue(), LocVT,
- CCValAssign::Full));
+ InputArgIndex, LocVT.getSimpleVT(),
+ ArgOffset + FieldOffsets[SplitIdx].getFixedValue(),
+ LocVT.getSimpleVT(), CCValAssign::Full));
SplitArgAlignments.push_back(
commonAlignment(ArgBaseAlign, FieldOffsets[SplitIdx]));
SplitArgs.push_back(ArgSplitArgs[SplitIdx]);
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-preload-kernargs.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-preload-kernargs.ll
index 961e78d425a56..9c388affbcb0d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-preload-kernargs.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-preload-kernargs.ll
@@ -6,15 +6,14 @@ define amdgpu_kernel void @preload_i32_inreg(i32 inreg %x, ptr addrspace(1) %out
; GFX90A: bb.1 (%ir-block.0):
; GFX90A-NEXT: liveins: $sgpr6, $sgpr4_sgpr5
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr6
- ; GFX90A-NEXT: [[COPY1:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; GFX90A-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]]
- ; GFX90A-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
+ ; GFX90A-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
+ ; GFX90A-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr6
+ ; GFX90A-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX90A-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
; GFX90A-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; GFX90A-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw nusw inbounds G_PTR_ADD [[INT]], [[C]](s64)
; GFX90A-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from %ir.out.kernarg.offset, addrspace 4)
- ; GFX90A-NEXT: G_STORE [[COPY3]](s32), [[LOAD]](p1) :: (store (s32) into %ir.out.load, addrspace 1)
+ ; GFX90A-NEXT: G_STORE [[COPY2]](s32), [[LOAD]](p1) :: (store (s32) into %ir.out.load, addrspace 1)
; GFX90A-NEXT: S_ENDPGM 0
store i32 %x, ptr addrspace(1) %out, align 4
ret void
@@ -25,15 +24,14 @@ define amdgpu_kernel void @preload_i64_inreg(i64 inreg %x, ptr addrspace(1) %out
; GFX90A: bb.1 (%ir-block.0):
; GFX90A-NEXT: liveins: $sgpr4_sgpr5, $sgpr6_sgpr7
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr6_sgpr7
- ; GFX90A-NEXT: [[COPY1:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; GFX90A-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]]
- ; GFX90A-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY2]](s64)
+ ; GFX90A-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
+ ; GFX90A-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $sgpr6_sgpr7
+ ; GFX90A-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
; GFX90A-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
; GFX90A-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; GFX90A-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw nusw inbounds G_PTR_ADD [[INT]], [[C]](s64)
; GFX90A-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from %ir.out.kernarg.offset, addrspace 4)
- ; GFX90A-NEXT: G_STORE [[COPY3]](s64), [[LOAD]](p1) :: (store (s64) into %ir.out.load, addrspace 1)
+ ; GFX90A-NEXT: G_STORE [[COPY2]](s64), [[LOAD]](p1) :: (store (s64) into %ir.out.load, addrspace 1)
; GFX90A-NEXT: S_ENDPGM 0
store i64 %x, ptr addrspace(1) %out, align 8
ret void
@@ -44,38 +42,55 @@ define amdgpu_kernel void @preload_ptr_inreg(ptr addrspace(1) inreg %p, ptr addr
; GFX90A: bb.1 (%ir-block.0):
; GFX90A-NEXT: liveins: $sgpr4_sgpr5, $sgpr6_sgpr7
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr6_sgpr7
- ; GFX90A-NEXT: [[COPY1:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; GFX90A-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]]
- ; GFX90A-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[COPY2]](s64)
- ; GFX90A-NEXT: [[COPY3:%[0-9]+]]:_(p1) = COPY [[INTTOPTR]](p1)
+ ; GFX90A-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
+ ; GFX90A-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $sgpr6_sgpr7
+ ; GFX90A-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[COPY1]](s64)
+ ; GFX90A-NEXT: [[COPY2:%[0-9]+]]:_(p1) = COPY [[INTTOPTR]](p1)
; GFX90A-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
; GFX90A-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; GFX90A-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw nusw inbounds G_PTR_ADD [[INT]], [[C]](s64)
; GFX90A-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from %ir.out.kernarg.offset, addrspace 4)
- ; GFX90A-NEXT: G_STORE [[COPY3]](p1), [[LOAD]](p1) :: (store (p1) into %ir.out.load, addrspace 1)
+ ; GFX90A-NEXT: G_STORE [[COPY2]](p1), [[LOAD]](p1) :: (store (p1) into %ir.out.load, addrspace 1)
; GFX90A-NEXT: S_ENDPGM 0
store ptr addrspace(1) %p, ptr addrspace(1) %out, align 8
ret void
}
+define amdgpu_kernel void @preload_lds_ptr_inreg(ptr addrspace(3) inreg %p, ptr addrspace(1) %out) #0 {
+ ; GFX90A-LABEL: name: preload_lds_ptr_inreg
+ ; GFX90A: bb.1 (%ir-block.0):
+ ; GFX90A-NEXT: liveins: $sgpr6, $sgpr4_sgpr5
+ ; GFX90A-NEXT: {{ $}}
+ ; GFX90A-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
+ ; GFX90A-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr6
+ ; GFX90A-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[COPY1]](s32)
+ ; GFX90A-NEXT: [[COPY2:%[0-9]+]]:_(p3) = COPY [[INTTOPTR]](p3)
+ ; GFX90A-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
+ ; GFX90A-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; GFX90A-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw nusw inbounds G_PTR_ADD [[INT]], [[C]](s64)
+ ; GFX90A-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from %ir.out.kernarg.offset, addrspace 4)
+ ; GFX90A-NEXT: G_STORE [[COPY2]](p3), [[LOAD]](p1) :: (store (p3) into %ir.out.load, addrspace 1)
+ ; GFX90A-NEXT: S_ENDPGM 0
+ store ptr addrspace(3) %p, ptr addrspace(1) %out, align 4
+ ret void
+}
+
define amdgpu_kernel void @preload_packed_i16_inreg(i16 inreg %a, i16 inreg %b, ptr addrspace(1) %out) #0 {
; GFX90A-LABEL: name: preload_packed_i16_inreg
; GFX90A: bb.1 (%ir-block.0):
; GFX90A-NEXT: liveins: $sgpr6, $sgpr4_sgpr5
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr6
- ; GFX90A-NEXT: [[COPY1:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; GFX90A-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]]
+ ; GFX90A-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
+ ; GFX90A-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr6
; GFX90A-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; GFX90A-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C]](s32)
+ ; GFX90A-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; GFX90A-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
- ; GFX90A-NEXT: [[COPY3:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
+ ; GFX90A-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
; GFX90A-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
; GFX90A-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; GFX90A-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw nusw inbounds G_PTR_ADD [[INT]], [[C1]](s64)
; GFX90A-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from %ir.out.kernarg.offset, addrspace 4)
- ; GFX90A-NEXT: G_STORE [[COPY3]](s16), [[LOAD]](p1) :: (store (s16) into %ir.out.load, addrspace 1)
+ ; GFX90A-NEXT: G_STORE [[COPY2]](s16), [[LOAD]](p1) :: (store (s16) into %ir.out.load, addrspace 1)
; GFX90A-NEXT: S_ENDPGM 0
store i16 %b, ptr addrspace(1) %out, align 2
ret void
@@ -86,16 +101,14 @@ define amdgpu_kernel void @preload_hidden_block_count_x(ptr addrspace(1) inreg %
; GFX90A: bb.1 (%ir-block.0):
; GFX90A-NEXT: liveins: $sgpr8, $sgpr4_sgpr5, $sgpr6_sgpr7
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr8
- ; GFX90A-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr6_sgpr7
- ; GFX90A-NEXT: [[COPY2:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; GFX90A-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]]
- ; GFX90A-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[COPY3]](s64)
- ; GFX90A-NEXT: [[COPY4:%[0-9]+]]:_(p1) = COPY [[INTTOPTR]](p1)
- ; GFX90A-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]]
- ; GFX90A-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
+ ; GFX90A-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
+ ; GFX90A-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $sgpr6_sgpr7
+ ; GFX90A-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[COPY1]](s64)
+ ; GFX90A-NEXT: [[COPY2:%[0-9]+]]:_(p1) = COPY [[INTTOPTR]](p1)
+ ; GFX90A-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr8
+ ; GFX90A-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; GFX90A-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
- ; GFX90A-NEXT: G_STORE [[COPY6]](s32), [[COPY4]](p1) :: (store (s32) into %ir.out, addrspace 1)
+ ; GFX90A-NEXT: G_STORE [[COPY4]](s32), [[COPY2]](p1) :: (store (s32) into %ir.out, addrspace 1)
; GFX90A-NEXT: S_ENDPGM 0
store i32 %_hidden_block_count_x, ptr addrspace(1) %out, align 4
ret void
@@ -106,15 +119,14 @@ define amdgpu_kernel void @preload_v1i32_inreg(<1 x i32> inreg %x, ptr addrspace
; GFX90A: bb.1 (%ir-block.0):
; GFX90A-NEXT: liveins: $sgpr6, $sgpr4_sgpr5
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr6
- ; GFX90A-NEXT: [[COPY1:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; GFX90A-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]]
- ; GFX90A-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
+ ; GFX90A-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
+ ; GFX90A-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr6
+ ; GFX90A-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX90A-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
; GFX90A-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; GFX90A-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw nusw inbounds G_PTR_ADD [[INT]], [[C]](s64)
; GFX90A-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from %ir.out.kernarg.offset, addrspace 4)
- ; GFX90A-NEXT: G_STORE [[COPY3]](s32), [[LOAD]](p1) :: (store (s32) into %ir.out.load, addrspace 1)
+ ; GFX90A-NEXT: G_STORE [[COPY2]](s32), [[LOAD]](p1) :: (store (s32) into %ir.out.load, addrspace 1)
; GFX90A-NEXT: S_ENDPGM 0
store <1 x i32> %x, ptr addrspace(1) %out, align 4
ret void
@@ -125,15 +137,14 @@ define amdgpu_kernel void @preload_skip_empty_struct_inreg({} inreg %empty, i32
; GFX90A: bb.1 (%ir-block.0):
; GFX90A-NEXT: liveins: $sgpr6, $sgpr4_sgpr5
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr6
- ; GFX90A-NEXT: [[COPY1:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
- ; GFX90A-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]]
- ; GFX90A-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
+ ; GFX90A-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
+ ; GFX90A-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr6
+ ; GFX90A-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX90A-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
; GFX90A-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; GFX90A-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw nusw inbounds G_PTR_ADD [[INT]], [[C]](s64)
; GFX90A-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from %ir.out.kernarg.offset, addrspace 4)
- ; GFX90A-NEXT: G_STORE [[COPY3]](s32), [[LOAD]](p1) :: (store (s32) into %ir.out.load, addrspace 1)
+ ; GFX90A-NEXT: G_STORE [[COPY2]](s32), [[LOAD]](p1) :: (store (s32) into %ir.out.load, addrspace 1)
; GFX90A-NEXT: S_ENDPGM 0
store i32 %x, ptr addrspace(1) %out, align 4
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
index b58757ddfba93..7e8d4e1ea8b9a 100644
--- a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
+++ b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll
@@ -951,8 +951,8 @@ define amdgpu_kernel void @preload_block_count_xyz(ptr addrspace(1) inreg %out)
; GFX90a-GISEL-NEXT: ; %bb.2:
; GFX90a-GISEL-NEXT: .LBB11_0:
; GFX90a-GISEL-NEXT: s_mov_b32 s0, s10
-; GFX90a-GISEL-NEXT: s_mov_b32 s2, s12
; GFX90a-GISEL-NEXT: s_mov_b32 s1, s11
+; GFX90a-GISEL-NEXT: s_mov_b32 s2, s12
; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, s1
; GFX90a-GISEL-NEXT: v_mov_b32_e32 v2, s2
@@ -1699,12 +1699,12 @@ define amdgpu_kernel void @preloadremainder_xyz(ptr addrspace(1) inreg %out) #0
; GFX90a-GISEL-NEXT: .p2align 8
; GFX90a-GISEL-NEXT: ; %bb.2:
; GFX90a-GISEL-NEXT: .LBB19_0:
-; GFX90a-GISEL-NEXT: s_lshr_b32 s0, s14, 16
-; GFX90a-GISEL-NEXT: s_lshr_b32 s2, s15, 16
-; GFX90a-GISEL-NEXT: s_and_b32 s1, s15, 0xffff
-; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, s1
-; GFX90a-GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX90a-GISEL-NEXT: s_lshr_b32 s4, s14, 16
+; GFX90a-GISEL-NEXT: s_lshr_b32 s6, s15, 16
+; GFX90a-GISEL-NEXT: s_and_b32 s5, s15, 0xffff
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; GFX90a-GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX90a-GISEL-NEXT: v_mov_b32_e32 v3, 0
; GFX90a-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]
; GFX90a-GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/preload-kernargs.ll b/llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
index 8d2ea415829a4..22cac856d37a6 100644
--- a/llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
+++ b/llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
@@ -811,19 +811,19 @@ define amdgpu_kernel void @v8i32_arg(ptr addrspace(1) nocapture inreg %out, <8 x
; GFX1250-GISEL-LABEL: v8i32_arg:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-GISEL-NEXT: s_mov_b32 s5, s15
-; GFX1250-GISEL-NEXT: s_mov_b32 s4, s14
-; GFX1250-GISEL-NEXT: s_mov_b32 s15, s13
-; GFX1250-GISEL-NEXT: s_mov_b32 s14, s12
-; GFX1250-GISEL-NEXT: s_mov_b32 s13, s11
-; GFX1250-GISEL-NEXT: s_mov_b32 s12, s10
-; GFX1250-GISEL-NEXT: s_mov_b32 s7, s17
-; GFX1250-GISEL-NEXT: s_mov_b32 s6, s16
-; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[12:13]
-; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[14:15]
-; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5]
+; GFX1250-GISEL-NEXT: s_mov_b32 s4, s10
+; GFX1250-GISEL-NEXT: s_mov_b32 s5, s11
+; GFX1250-GISEL-NEXT: s_mov_b32 s6, s12
+; GFX1250-GISEL-NEXT: s_mov_b32 s7, s13
+; GFX1250-GISEL-NEXT: s_mov_b32 s8, s14
+; GFX1250-GISEL-NEXT: s_mov_b32 s9, s15
+; GFX1250-GISEL-NEXT: s_mov_b32 s10, s16
+; GFX1250-GISEL-NEXT: s_mov_b32 s11, s17
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[4:5]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[6:7]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[8:9]
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v8, 0
-; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[10:11]
; GFX1250-GISEL-NEXT: s_clause 0x1
; GFX1250-GISEL-NEXT: global_store_b128 v8, v[0:3], s[2:3]
; GFX1250-GISEL-NEXT: global_store_b128 v8, v[4:7], s[2:3] offset:16
@@ -956,12 +956,12 @@ define amdgpu_kernel void @v3i32_preload_arg(ptr addrspace(1) nocapture inreg %o
; GFX942-GISEL-NEXT: .p2align 8
; GFX942-GISEL-NEXT: ; %bb.2:
; GFX942-GISEL-NEXT: .LBB11_0:
-; GFX942-GISEL-NEXT: s_mov_b32 s10, s8
-; GFX942-GISEL-NEXT: s_mov_b32 s8, s6
-; GFX942-GISEL-NEXT: s_mov_b32 s9, s7
-; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s8
-; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, s9
-; GFX942-GISEL-NEXT: v_mov_b32_e32 v2, s10
+; GFX942-GISEL-NEXT: s_mov_b32 s4, s6
+; GFX942-GISEL-NEXT: s_mov_b32 s5, s7
+; GFX942-GISEL-NEXT: s_mov_b32 s6, s8
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX942-GISEL-NEXT: v_mov_b32_e32 v3, 0
; GFX942-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
; GFX942-GISEL-NEXT: s_endpgm
@@ -992,12 +992,11 @@ define amdgpu_kernel void @v3i32_preload_arg(ptr addrspace(1) nocapture inreg %o
; GFX1250-GISEL-LABEL: v3i32_preload_arg:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-GISEL-NEXT: s_mov_b32 s10, s8
-; GFX1250-GISEL-NEXT: s_mov_b32 s8, s6
-; GFX1250-GISEL-NEXT: s_mov_b32 s9, s7
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
-; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, 0
+; GFX1250-GISEL-NEXT: s_mov_b32 s4, s6
+; GFX1250-GISEL-NEXT: s_mov_b32 s5, s7
+; GFX1250-GISEL-NEXT: s_mov_b32 s6, s8
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, 0
; GFX1250-GISEL-NEXT: global_store_b96 v3, v[0:2], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
store <3 x i32> %in, ptr addrspace(1) %out, align 4
@@ -1032,12 +1031,12 @@ define amdgpu_kernel void @v3f32_preload_arg(ptr addrspace(1) nocapture inreg %o
; GFX942-GISEL-NEXT: .p2align 8
; GFX942-GISEL-NEXT: ; %bb.2:
; GFX942-GISEL-NEXT: .LBB12_0:
-; GFX942-GISEL-NEXT: s_mov_b32 s10, s8
-; GFX942-GISEL-NEXT: s_mov_b32 s8, s6
-; GFX942-GISEL-NEXT: s_mov_b32 s9, s7
-; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s8
-; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, s9
-; GFX942-GISEL-NEXT: v_mov_b32_e32 v2, s10
+; GFX942-GISEL-NEXT: s_mov_b32 s4, s6
+; GFX942-GISEL-NEXT: s_mov_b32 s5, s7
+; GFX942-GISEL-NEXT: s_mov_b32 s6, s8
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX942-GISEL-NEXT: v_mov_b32_e32 v3, 0
; GFX942-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
; GFX942-GISEL-NEXT: s_endpgm
@@ -1083,12 +1082,11 @@ define amdgpu_kernel void @v3f32_preload_arg(ptr addrspace(1) nocapture inreg %o
; GFX1250-GISEL-LABEL: v3f32_preload_arg:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-GISEL-NEXT: s_mov_b32 s10, s8
-; GFX1250-GISEL-NEXT: s_mov_b32 s8, s6
-; GFX1250-GISEL-NEXT: s_mov_b32 s9, s7
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
-; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, 0
+; GFX1250-GISEL-NEXT: s_mov_b32 s4, s6
+; GFX1250-GISEL-NEXT: s_mov_b32 s5, s7
+; GFX1250-GISEL-NEXT: s_mov_b32 s6, s8
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, 0
; GFX1250-GISEL-NEXT: global_store_b96 v3, v[0:2], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
store <3 x float> %in, ptr addrspace(1) %out, align 4
@@ -1959,12 +1957,12 @@ define amdgpu_kernel void @v6bfloat_kernel_preload_arg(ptr addrspace(1) inreg %o
; GFX942-GISEL-NEXT: .p2align 8
; GFX942-GISEL-NEXT: ; %bb.2:
; GFX942-GISEL-NEXT: .LBB22_0:
-; GFX942-GISEL-NEXT: s_mov_b32 s10, s8
-; GFX942-GISEL-NEXT: s_mov_b32 s8, s6
-; GFX942-GISEL-NEXT: s_mov_b32 s9, s7
-; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s8
-; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, s9
-; GFX942-GISEL-NEXT: v_mov_b32_e32 v2, s10
+; GFX942-GISEL-NEXT: s_mov_b32 s4, s6
+; GFX942-GISEL-NEXT: s_mov_b32 s5, s7
+; GFX942-GISEL-NEXT: s_mov_b32 s6, s8
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX942-GISEL-NEXT: v_mov_b32_e32 v3, 0
; GFX942-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
; GFX942-GISEL-NEXT: s_endpgm
@@ -1995,12 +1993,11 @@ define amdgpu_kernel void @v6bfloat_kernel_preload_arg(ptr addrspace(1) inreg %o
; GFX1250-GISEL-LABEL: v6bfloat_kernel_preload_arg:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-GISEL-NEXT: s_mov_b32 s10, s8
-; GFX1250-GISEL-NEXT: s_mov_b32 s8, s6
-; GFX1250-GISEL-NEXT: s_mov_b32 s9, s7
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
-; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, 0
+; GFX1250-GISEL-NEXT: s_mov_b32 s4, s6
+; GFX1250-GISEL-NEXT: s_mov_b32 s5, s7
+; GFX1250-GISEL-NEXT: s_mov_b32 s6, s8
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, 0
; GFX1250-GISEL-NEXT: global_store_b96 v3, v[0:2], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
store <6 x bfloat> %in, ptr addrspace(1) %out
@@ -2266,12 +2263,12 @@ define amdgpu_kernel void @fp128_kernel_preload_arg(ptr addrspace(1) inreg %out,
; GFX942-GISEL-NEXT: .p2align 8
; GFX942-GISEL-NEXT: ; %bb.2:
; GFX942-GISEL-NEXT: .LBB25_0:
-; GFX942-GISEL-NEXT: s_mov_b32 s11, s9
-; GFX942-GISEL-NEXT: s_mov_b32 s10, s8
-; GFX942-GISEL-NEXT: s_mov_b32 s9, s7
-; GFX942-GISEL-NEXT: s_mov_b32 s8, s6
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
-; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
+; GFX942-GISEL-NEXT: s_mov_b32 s4, s6
+; GFX942-GISEL-NEXT: s_mov_b32 s5, s7
+; GFX942-GISEL-NEXT: s_mov_b32 s6, s8
+; GFX942-GISEL-NEXT: s_mov_b32 s7, s9
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[4:5]
+; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[6:7]
; GFX942-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX942-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
; GFX942-GISEL-NEXT: s_endpgm
@@ -2318,13 +2315,13 @@ define amdgpu_kernel void @fp128_kernel_preload_arg(ptr addrspace(1) inreg %out,
; GFX1250-GISEL-LABEL: fp128_kernel_preload_arg:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-GISEL-NEXT: s_mov_b32 s11, s9
-; GFX1250-GISEL-NEXT: s_mov_b32 s10, s8
-; GFX1250-GISEL-NEXT: s_mov_b32 s9, s7
-; GFX1250-GISEL-NEXT: s_mov_b32 s8, s6
+; GFX1250-GISEL-NEXT: s_mov_b32 s4, s6
+; GFX1250-GISEL-NEXT: s_mov_b32 s5, s7
+; GFX1250-GISEL-NEXT: s_mov_b32 s6, s8
+; GFX1250-GISEL-NEXT: s_mov_b32 s7, s9
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[4:5]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[6:7]
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v4, 0
-; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
-; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[10:11]
; GFX1250-GISEL-NEXT: global_store_b128 v4, v[0:3], s[2:3]
; GFX1250-GISEL-NEXT: s_endpgm
store fp128 %in, ptr addrspace(1) %out
@@ -2739,8 +2736,8 @@ define amdgpu_kernel void @i16_v3i32_kernel_preload_arg(ptr addrspace(1) inreg %
; GFX942-GISEL-NEXT: s_mov_b32 s12, s6
; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX942-GISEL-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-GISEL-NEXT: s_mov_b32 s14, s8
; GFX942-GISEL-NEXT: s_mov_b32 s13, s7
+; GFX942-GISEL-NEXT: s_mov_b32 s14, s8
; GFX942-GISEL-NEXT: global_store_short v3, v0, s[2:3]
; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, s12
; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, s13
@@ -2801,8 +2798,8 @@ define amdgpu_kernel void @i16_v3i32_kernel_preload_arg(ptr addrspace(1) inreg %
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT: s_mov_b32 s12, s6
-; GFX1250-GISEL-NEXT: s_mov_b32 s14, s8
; GFX1250-GISEL-NEXT: s_mov_b32 s13, s7
+; GFX1250-GISEL-NEXT: s_mov_b32 s14, s8
; GFX1250-GISEL-NEXT: v_mov_b16_e32 v0.l, s4
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s12
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v3, s13 :: v_dual_mov_b32 v4, s14
@@ -2892,10 +2889,10 @@ define amdgpu_kernel void @i16_i16_kernel_preload_arg(ptr addrspace(1) inreg %ou
; GFX1250-GISEL-LABEL: i16_i16_kernel_preload_arg:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-GISEL-NEXT: s_lshr_b32 s0, s4, 16
+; GFX1250-GISEL-NEXT: s_lshr_b32 s1, s4, 16
; GFX1250-GISEL-NEXT: v_mov_b16_e32 v0.l, s4
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-GISEL-NEXT: v_mov_b16_e32 v0.h, s0
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v0.h, s1
; GFX1250-GISEL-NEXT: s_clause 0x1
; GFX1250-GISEL-NEXT: global_store_b16 v1, v0, s[2:3]
; GFX1250-GISEL-NEXT: global_store_d16_hi_b16 v1, v0, s[6:7]
@@ -2992,10 +2989,10 @@ define amdgpu_kernel void @i16_v2i8_kernel_preload_arg(ptr addrspace(1) inreg %o
; GFX1250-GISEL-LABEL: i16_v2i8_kernel_preload_arg:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-GISEL-NEXT: s_lshr_b32 s0, s4, 16
+; GFX1250-GISEL-NEXT: s_lshr_b32 s1, s4, 16
; GFX1250-GISEL-NEXT: v_mov_b16_e32 v0.l, s4
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 0
-; GFX1250-GISEL-NEXT: v_mov_b16_e32 v0.h, s0
+; GFX1250-GISEL-NEXT: v_mov_b16_e32 v0.h, s1
; GFX1250-GISEL-NEXT: s_clause 0x1
; GFX1250-GISEL-NEXT: global_store_b16 v1, v0, s[2:3]
; GFX1250-GISEL-NEXT: global_store_d16_hi_b16 v1, v0, s[6:7]
>From c33f8cdeab1ca6378ae1064162b46f938e43095e Mon Sep 17 00:00:00 2001
From: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
Date: Fri, 3 Jul 2026 17:22:27 +0530
Subject: [PATCH 5/6] [AMDGPU][GlobalISel] Simplify kernarg preload bookkeeping
Track split kernarg offsets and alignments directly in the kernel formal argument lowering path instead of manufacturing CCValAssign locations just to recover offsets later. This avoids the local MVT normalization block and keeps preload allocation independent of CCValAssign storage.
Also expand the MIR preload test coverage for odd-element and bit-element vector arguments and remove unnecessary target attributes from the test.
Co-authored-by: GPT-5 Codex <noreply at openai.com>
Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
---
llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp | 85 +++++++++----------
llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h | 5 +-
.../irtranslator-preload-kernargs.ll | 42 ++++++++-
3 files changed, 81 insertions(+), 51 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
index 8f59ab142c800..651e0519f110f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
@@ -305,12 +305,16 @@ static void lowerPreloadedKernArg(MachineIRBuilder &B, Register DstReg,
// Kernarg preloads are assigned in 32-bit SGPR units.
const LLT S32 = LLT::scalar(32);
- LLT IntDstTy = (DstTy.isPointer() || DstTy.isVector())
- ? LLT::scalar(DstTy.getSizeInBits())
- : DstTy;
- auto BuildCopyFromPreload = [&B](LLT Ty, MCRegister Reg) {
- B.getMBB().addLiveIn(Reg);
- return B.buildCopy(Ty, Register(Reg)).getReg(0);
+ auto BuildCopyFromPreload = [&B](LLT Ty, Register PhysReg) {
+ B.getMBB().addLiveIn(PhysReg.asMCReg());
+ return B.buildCopy(Ty, PhysReg).getReg(0);
+ };
+ auto getRawBitsTy = [](LLT Ty) { return LLT::scalar(Ty.getSizeInBits()); };
+ auto getPreloadStorageTy = [](LLT Ty) {
+ unsigned RoundedBits = alignTo(Ty.getSizeInBits(), 32);
+ if (!Ty.isPointer() && !Ty.isVector() && RoundedBits == Ty.getSizeInBits())
+ return Ty;
+ return LLT::scalar(RoundedBits);
};
Register Value;
@@ -320,15 +324,15 @@ static void lowerPreloadedKernArg(MachineIRBuilder &B, Register DstReg,
if (PreloadRegs.size() == 1) {
if (IsPackedSubDword) {
// Extract sub-dword preloads from their containing 32-bit SGPR word.
- Register Raw = BuildCopyFromPreload(S32, PreloadRegs[0]);
+ Register Raw = BuildCopyFromPreload(S32, Register(PreloadRegs[0]));
uint64_t OffsetDiff = Offset - alignDown(Offset, 4);
Register ShiftAmt = B.buildConstant(S32, OffsetDiff * 8).getReg(0);
Value = B.buildLShr(S32, Raw, ShiftAmt).getReg(0);
ValueTy = S32;
} else {
- // Copy the physical preload storage width, then narrow to the IR size.
- ValueTy = LLT::scalar(alignTo(IntDstTy.getSizeInBits(), 32));
- Value = BuildCopyFromPreload(ValueTy, PreloadRegs[0]);
+ // The physical register may cover more bits than the IR value uses.
+ ValueTy = getPreloadStorageTy(DstTy);
+ Value = BuildCopyFromPreload(ValueTy, Register(PreloadRegs[0]));
}
} else {
assert(!IsPackedSubDword && "packed sub-dword preload should use one SGPR");
@@ -336,15 +340,17 @@ static void lowerPreloadedKernArg(MachineIRBuilder &B, Register DstReg,
SmallVector<Register, 4> Regs;
Regs.reserve(PreloadRegs.size());
for (MCRegister Reg : PreloadRegs) {
- Regs.push_back(BuildCopyFromPreload(S32, Reg));
+ Regs.push_back(BuildCopyFromPreload(S32, Register(Reg)));
}
ValueTy = LLT::scalar(PreloadRegs.size() * 32);
Value = B.buildMergeLikeInstr(ValueTy, Regs).getReg(0);
}
- if (ValueTy.getSizeInBits() != IntDstTy.getSizeInBits())
- Value = B.buildAnyExtOrTrunc(IntDstTy, Value).getReg(0);
+ LLT AdjustedTy =
+ (DstTy.isPointer() || DstTy.isVector()) ? getRawBitsTy(DstTy) : DstTy;
+ if (ValueTy != AdjustedTy)
+ Value = B.buildAnyExtOrTrunc(AdjustedTy, Value).getReg(0);
if (DstTy.isPointer())
Value = B.buildIntToPtr(DstTy, Value).getReg(0);
@@ -358,10 +364,11 @@ static void lowerPreloadedKernArg(MachineIRBuilder &B, Register DstReg,
// kernarg preload.
static void allocatePreloadKernArgSGPRs(
CCState &CCInfo, ArrayRef<CallLowering::ArgInfo> SplitArgs,
- ArrayRef<CCValAssign> ArgLocs, MachineFunction &MF,
- const GCNSubtarget &Subtarget, const SIRegisterInfo &TRI,
- SIMachineFunctionInfo &Info) {
- assert(SplitArgs.size() == ArgLocs.size());
+ ArrayRef<uint64_t> SplitArgOffsets, ArrayRef<Align> SplitArgAlignments,
+ MachineFunction &MF, const GCNSubtarget &Subtarget,
+ const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) {
+ assert(SplitArgs.size() == SplitArgOffsets.size());
+ assert(SplitArgs.size() == SplitArgAlignments.size());
const Function &F = MF.getFunction();
const DataLayout &DL = F.getDataLayout();
@@ -388,13 +395,8 @@ static void allocatePreloadKernArgSGPRs(
for (unsigned ArgIdx = Arg.getArgNo();
InIdx < SplitArgs.size() && SplitArgs[InIdx].OrigArgIndex == ArgIdx;
++InIdx) {
- const CCValAssign &ArgLoc = ArgLocs[InIdx];
- assert(ArgLoc.isMemLoc());
- const Align KernelArgBaseAlign = Align(16);
- unsigned ArgOffset = ArgLoc.getLocMemOffset();
- Align Alignment = commonAlignment(KernelArgBaseAlign, ArgOffset);
- // CCValAssign may need a rounded legal MVT, but preload SGPR accounting
- // must follow the original kernarg byte layout.
+ unsigned ArgOffset = SplitArgOffsets[InIdx];
+ Align Alignment = SplitArgAlignments[InIdx];
unsigned NumAllocSGPRs =
alignTo(DL.getTypeAllocSize(SplitArgs[InIdx].Ty), 4) / 4;
@@ -411,7 +413,7 @@ static void allocatePreloadKernArgSGPRs(
ArgOffset += ImplicitArgOffset;
}
- if (ArgLoc.getLocVT().getStoreSize() < 4 && Alignment < 4) {
+ if (DL.getTypeStoreSize(SplitArgs[InIdx].Ty) < 4 && Alignment < 4) {
// Packed sub-dword values share the previous 32-bit SGPR. The extract
// happens later when materializing the argument value.
assert(InIdx >= 1 && "No previous SGPR");
@@ -605,8 +607,7 @@ void AMDGPUCallLowering::lowerParameterPtr(Register DstReg, MachineIRBuilder &B,
}
bool AMDGPUCallLowering::lowerParameter(MachineIRBuilder &B, ArgInfo &Arg,
- const CCValAssign &ArgLoc,
- Align Alignment,
+ uint64_t Offset, Align Alignment,
unsigned InputArgIndex) const {
MachineFunction &MF = B.getMF();
const Function &F = MF.getFunction();
@@ -630,7 +631,6 @@ bool AMDGPUCallLowering::lowerParameter(MachineIRBuilder &B, ArgInfo &Arg,
assert(Arg.Regs.size() == 1);
- uint64_t Offset = ArgLoc.getLocMemOffset();
auto PreloadArg = Info->getArgInfo().PreloadKernArgs.find(InputArgIndex);
if (PreloadArg != Info->getArgInfo().PreloadKernArgs.end()) {
lowerPreloadedKernArg(B, Arg.Regs[0], ArgTy, Offset, Alignment,
@@ -733,6 +733,7 @@ bool AMDGPUCallLowering::lowerFormalArgumentsKernel(
allocateHSAUserSGPRs(CCInfo, B, MF, *TRI, *Info);
SmallVector<ArgInfo, 16> SplitArgs;
+ SmallVector<uint64_t, 16> SplitArgOffsets;
SmallVector<Align, 16> SplitArgAlignments;
unsigned VRegIdx = 0;
@@ -764,19 +765,9 @@ bool AMDGPUCallLowering::lowerFormalArgumentsKernel(
for (unsigned SplitIdx = 0, NumSplitArgs = ArgSplitArgs.size();
SplitIdx != NumSplitArgs; ++SplitIdx) {
- unsigned InputArgIndex = SplitArgs.size();
ArgSplitArgs[SplitIdx].OrigValue = &Arg;
- EVT LocVT = TLI.getValueType(DL, ArgSplitArgs[SplitIdx].Ty, true);
- if (LocVT.isVector() && LocVT.getVectorNumElements() == 1)
- LocVT = LocVT.getScalarType();
- if (LocVT.isVector() && !LocVT.isPow2VectorType())
- LocVT = LocVT.getPow2VectorType(F.getContext());
- else if (!LocVT.isSimple() && !LocVT.isVector())
- LocVT = LocVT.getRoundIntegerType(F.getContext());
- CCInfo.addLoc(CCValAssign::getCustomMem(
- InputArgIndex, LocVT.getSimpleVT(),
- ArgOffset + FieldOffsets[SplitIdx].getFixedValue(),
- LocVT.getSimpleVT(), CCValAssign::Full));
+ SplitArgOffsets.push_back(ArgOffset +
+ FieldOffsets[SplitIdx].getFixedValue());
SplitArgAlignments.push_back(
commonAlignment(ArgBaseAlign, FieldOffsets[SplitIdx]));
SplitArgs.push_back(ArgSplitArgs[SplitIdx]);
@@ -786,8 +777,9 @@ bool AMDGPUCallLowering::lowerFormalArgumentsKernel(
}
if (Subtarget->hasKernargPreload())
- allocatePreloadKernArgSGPRs(CCInfo, SplitArgs, ArgLocs, MF, *Subtarget,
- *TRI, *Info);
+ allocatePreloadKernArgSGPRs(CCInfo, SplitArgs, SplitArgOffsets,
+ SplitArgAlignments, MF, *Subtarget, *TRI,
+ *Info);
unsigned i = 0;
unsigned InputArgIndex = 0;
@@ -817,20 +809,19 @@ bool AMDGPUCallLowering::lowerFormalArgumentsKernel(
assert(VRegs[i].size() == 1 &&
"expected only one register for byval pointers");
if (ByRefAS == AMDGPUAS::CONSTANT_ADDRESS) {
- lowerParameterPtr(VRegs[i][0], B,
- ArgLocs[FirstInputArgIndex].getLocMemOffset());
+ lowerParameterPtr(VRegs[i][0], B, SplitArgOffsets[FirstInputArgIndex]);
} else {
const LLT ConstPtrTy = LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64);
Register PtrReg = MRI.createGenericVirtualRegister(ConstPtrTy);
- lowerParameterPtr(PtrReg, B,
- ArgLocs[FirstInputArgIndex].getLocMemOffset());
+ lowerParameterPtr(PtrReg, B, SplitArgOffsets[FirstInputArgIndex]);
B.buildAddrSpaceCast(VRegs[i][0], PtrReg);
}
} else {
for (unsigned Part = 0; Part != NumInputParts; ++Part) {
unsigned InputArgIndex = FirstInputArgIndex + Part;
- if (!lowerParameter(B, SplitArgs[InputArgIndex], ArgLocs[InputArgIndex],
+ if (!lowerParameter(B, SplitArgs[InputArgIndex],
+ SplitArgOffsets[InputArgIndex],
SplitArgAlignments[InputArgIndex], InputArgIndex))
return false;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h
index b775db64554f7..371154a4c564c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h
@@ -26,9 +26,8 @@ class AMDGPUCallLowering final : public CallLowering {
void lowerParameterPtr(Register DstReg, MachineIRBuilder &B,
uint64_t Offset) const;
- bool lowerParameter(MachineIRBuilder &B, ArgInfo &AI,
- const CCValAssign &ArgLoc, Align Alignment,
- unsigned InputArgIndex) const;
+ bool lowerParameter(MachineIRBuilder &B, ArgInfo &AI, uint64_t Offset,
+ Align Alignment, unsigned InputArgIndex) const;
bool canLowerReturn(MachineFunction &MF, CallingConv::ID CallConv,
SmallVectorImpl<BaseArgInfo> &Outs,
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-preload-kernargs.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-preload-kernargs.ll
index 9c388affbcb0d..9c78ccd412490 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-preload-kernargs.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-preload-kernargs.ll
@@ -132,6 +132,46 @@ define amdgpu_kernel void @preload_v1i32_inreg(<1 x i32> inreg %x, ptr addrspace
ret void
}
+define amdgpu_kernel void @preload_v3i16_inreg(<3 x i16> inreg %x, ptr addrspace(1) %out) #0 {
+ ; GFX90A-LABEL: name: preload_v3i16_inreg
+ ; GFX90A: bb.1 (%ir-block.0):
+ ; GFX90A-NEXT: liveins: $sgpr4_sgpr5, $sgpr6_sgpr7
+ ; GFX90A-NEXT: {{ $}}
+ ; GFX90A-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
+ ; GFX90A-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $sgpr6_sgpr7
+ ; GFX90A-NEXT: [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[COPY1]](s64)
+ ; GFX90A-NEXT: [[BITCAST:%[0-9]+]]:_(<3 x s16>) = G_BITCAST [[TRUNC]](s48)
+ ; GFX90A-NEXT: [[COPY2:%[0-9]+]]:_(<3 x s16>) = COPY [[BITCAST]](<3 x s16>)
+ ; GFX90A-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
+ ; GFX90A-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; GFX90A-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw nusw inbounds G_PTR_ADD [[INT]], [[C]](s64)
+ ; GFX90A-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from %ir.out.kernarg.offset, addrspace 4)
+ ; GFX90A-NEXT: G_STORE [[COPY2]](<3 x s16>), [[LOAD]](p1) :: (store (<3 x s16>) into %ir.out.load, align 8, addrspace 1)
+ ; GFX90A-NEXT: S_ENDPGM 0
+ store <3 x i16> %x, ptr addrspace(1) %out, align 8
+ ret void
+}
+
+define amdgpu_kernel void @preload_v8i1_inreg(<8 x i1> inreg %x, ptr addrspace(1) %out) #0 {
+ ; GFX90A-LABEL: name: preload_v8i1_inreg
+ ; GFX90A: bb.1 (%ir-block.0):
+ ; GFX90A-NEXT: liveins: $sgpr6, $sgpr4_sgpr5
+ ; GFX90A-NEXT: {{ $}}
+ ; GFX90A-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
+ ; GFX90A-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr6
+ ; GFX90A-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
+ ; GFX90A-NEXT: [[BITCAST:%[0-9]+]]:_(<8 x s1>) = G_BITCAST [[TRUNC]](s8)
+ ; GFX90A-NEXT: [[COPY2:%[0-9]+]]:_(<8 x s1>) = COPY [[BITCAST]](<8 x s1>)
+ ; GFX90A-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
+ ; GFX90A-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; GFX90A-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw nusw inbounds G_PTR_ADD [[INT]], [[C]](s64)
+ ; GFX90A-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p1) from %ir.out.kernarg.offset, addrspace 4)
+ ; GFX90A-NEXT: G_STORE [[COPY2]](<8 x s1>), [[LOAD]](p1) :: (store (<8 x s1>) into %ir.out.load, addrspace 1)
+ ; GFX90A-NEXT: S_ENDPGM 0
+ store <8 x i1> %x, ptr addrspace(1) %out, align 1
+ ret void
+}
+
define amdgpu_kernel void @preload_skip_empty_struct_inreg({} inreg %empty, i32 inreg %x, ptr addrspace(1) %out) #0 {
; GFX90A-LABEL: name: preload_skip_empty_struct_inreg
; GFX90A: bb.1 (%ir-block.0):
@@ -150,4 +190,4 @@ define amdgpu_kernel void @preload_skip_empty_struct_inreg({} inreg %empty, i32
ret void
}
-attributes #0 = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-no-wwm" "target-cpu"="gfx90a" }
+attributes #0 = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }
>From 940dcdfd05fb7379dc13f6f5634534e37f23f5b9 Mon Sep 17 00:00:00 2001
From: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
Date: Fri, 17 Jul 2026 09:35:54 +0530
Subject: [PATCH 6/6] [AMDGPU][GlobalISel] Simplify hidden kernarg check
Check the hidden-argument attribute directly at the fallback diagnostic while keeping the check after preload materialization.
Co-authored-by: GPT-5 Codex <noreply at openai.com>
Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
---
llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
index 651e0519f110f..5428ceea7847b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
@@ -612,9 +612,6 @@ bool AMDGPUCallLowering::lowerParameter(MachineIRBuilder &B, ArgInfo &Arg,
MachineFunction &MF = B.getMF();
const Function &F = MF.getFunction();
const DataLayout &DL = F.getDataLayout();
- const Argument *IRArg = dyn_cast_if_present<Argument>(Arg.OrigValue);
- const bool IsHiddenArg =
- IRArg && IRArg->hasAttribute("amdgpu-hidden-argument");
const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
const SITargetLowering &TLI = *getTLI<SITargetLowering>();
MachinePointerInfo PtrInfo = TLI.getKernargSegmentPtrInfo(MF);
@@ -638,7 +635,8 @@ bool AMDGPUCallLowering::lowerParameter(MachineIRBuilder &B, ArgInfo &Arg,
return true;
}
- if (IsHiddenArg) {
+ const Argument *IRArg = dyn_cast_if_present<Argument>(Arg.OrigValue);
+ if (IRArg && IRArg->hasAttribute("amdgpu-hidden-argument")) {
F.getContext().diagnose(DiagnosticInfoUnsupported(
F, "hidden argument in kernel signature was not preloaded"));
return false;
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