[llvm] dd2e6e0 - [RISCV][RVY] Fix DwarfRegAlias for X10_Y to X15_Y (#210104)

[via llvm-commits]

Author: Alexander Richardson
Date: 2026-07-16T17:55:24Z
New Revision: dd2e6e03c75918dce69e9d1f46e7b356ef31c60d

URL: https://github.com/llvm/llvm-project/commit/dd2e6e03c75918dce69e9d1f46e7b356ef31c60d
DIFF: https://github.com/llvm/llvm-project/commit/dd2e6e03c75918dce69e9d1f46e7b356ef31c60d.diff

LOG: [RISCV][RVY] Fix DwarfRegAlias for X10_Y to X15_Y (#210104)

The initial commit had typos here missing the leading 1.
This was not noticed since we don't have any tests yet that
emit .cfi_offset etc.

Fixes 5eb3969c7a0b192d74bf4730f854d4cfc25a6c77

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVRegisterInfo.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index 9ed8d744e9db6..fc9fb66d59f4b 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -237,12 +237,12 @@ let RegAltNameIndices = [ABIRegAltName] in {
   }
   def X8_Y : RISCVCapReg<X8, "x8", ["s0", "fp"]>, DwarfRegAlias<X8>;
   def X9_Y : RISCVCapReg<X9, "x9", ["s1"]>, DwarfRegAlias<X9>;
-  def X10_Y : RISCVCapReg<X10, "x10", ["a0"]>, DwarfRegAlias<X0>;
-  def X11_Y : RISCVCapReg<X11, "x11", ["a1"]>, DwarfRegAlias<X1>;
-  def X12_Y : RISCVCapReg<X12, "x12", ["a2"]>, DwarfRegAlias<X2>;
-  def X13_Y : RISCVCapReg<X13, "x13", ["a3"]>, DwarfRegAlias<X3>;
-  def X14_Y : RISCVCapReg<X14, "x14", ["a4"]>, DwarfRegAlias<X4>;
-  def X15_Y : RISCVCapReg<X15, "x15", ["a5"]>, DwarfRegAlias<X5>;
+  def X10_Y : RISCVCapReg<X10, "x10", ["a0"]>, DwarfRegAlias<X10>;
+  def X11_Y : RISCVCapReg<X11, "x11", ["a1"]>, DwarfRegAlias<X11>;
+  def X12_Y : RISCVCapReg<X12, "x12", ["a2"]>, DwarfRegAlias<X12>;
+  def X13_Y : RISCVCapReg<X13, "x13", ["a3"]>, DwarfRegAlias<X13>;
+  def X14_Y : RISCVCapReg<X14, "x14", ["a4"]>, DwarfRegAlias<X14>;
+  def X15_Y : RISCVCapReg<X15, "x15", ["a5"]>, DwarfRegAlias<X15>;
   let CostPerUse = [0, 1] in {
   def X16_Y : RISCVCapReg<X16, "x16", ["a6"]>, DwarfRegAlias<X16>;
   def X17_Y : RISCVCapReg<X17, "x17", ["a7"]>, DwarfRegAlias<X17>;