[llvm] AMDGPU: Migrate more tests to amdgpu triples (PR #210113)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 16 10:13:26 PDT 2026
https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/210113
These were missed in previous conversions for whatever reason.
Some are new tests added after I did the bulk migration, some
are special cases.
>From 9d66f406e06be6e72adf37d2f7e1eedb0b694d8e Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Thu, 16 Jul 2026 12:46:37 +0200
Subject: [PATCH] AMDGPU: Migrate more tests to amdgpu triples
These were missed in previous conversions for whatever reason.
Some are new tests added after I did the bulk migration, some
are special cases.
---
llvm/test/Analysis/CostModel/AMDGPU/fsub.ll | 2 +-
.../Analysis/CostModel/AMDGPU/fused_costs.ll | 2 -
.../DotMachineCFG/AMDGPU/functions.mir | 4 +-
.../DotMachineCFG/AMDGPU/irreducible.mir | 8 +-
llvm/test/Analysis/Lint/const-store.ll | 4 +-
llvm/test/Analysis/MemorySSA/ptr-const-mem.ll | 2 +-
.../AMDGPU/MIR/always-uniform-gmir.mir | 4 +-
.../AMDGPU/MIR/atomics-gmir.mir | 4 +-
.../UniformityAnalysis/AMDGPU/MIR/atomics.mir | 4 +-
.../AMDGPU/MIR/hidden-diverge-gmir.mir | 4 +-
.../AMDGPU/MIR/hidden-loop-diverge.mir | 4 +-
.../MIR/irreducible/branch-outside-gmir.mir | 4 +-
.../irreducible/diverged-entry-basic-gmir.mir | 4 +-
.../MIR/irreducible/exit-divergence-gmir.mir | 4 +-
.../MIR/irreducible/irreducible-2-gmir.mir | 4 +-
.../AMDGPU/MIR/join-loopexit-gmir.mir | 4 +-
.../AMDGPU/MIR/loads-gmir.mir | 4 +-
.../AMDGPU/MIR/never-uniform-gmir.mir | 4 +-
.../AMDGPU/MIR/temporal-divergence.mir | 4 +-
.../AMDGPU/deprecated/hidden-diverge.mir | 4 +-
.../AMDGPU/deprecated/irreducible-1.mir | 4 +-
.../AMDGPU/irreducible/irreducible-2.ll | 2 +-
.../amdgpu-image-atomic-attributes.ll | 4 +-
.../inst-select-extendedLLTs-err.mir | 2 +-
.../GlobalISel/inst-select-extendedLLTs.mir | 2 +-
...llvm.amdgcn.raw.ptr.buffer.offset-split.ll | 4 +-
.../GlobalISel/merge-values-s16-true16.ll | 2 +-
...mizations_dpp_lds_expected_active_lanes.ll | 12 +-
.../AMDGPU/buffer-fat-pointers-memcpy.ll | 2 -
...scer-subranges-another-copymi-not-live.mir | 2 -
...oalescer-subranges-another-prune-error.mir | 3 -
.../AMDGPU/coalescer-subregjoin-fullcopy.mir | 2 -
.../coalescer-with-subregs-bad-identical.mir | 3 -
.../CodeGen/AMDGPU/coexec-rewrite-mfma.ll | 2 -
.../divergent-branch-uniform-condition.ll | 4 +-
...eliminate-frame-index-flat-scratch-svs.mir | 4 +-
.../AMDGPU/expand-mov-b64-globaladdr-hsa.ll | 2 +-
.../expand-mov-b64-globaladdr-rel32.mir | 2 +-
.../AMDGPU/expand-mov-b64-globaladdr.ll | 4 +-
.../CodeGen/AMDGPU/expand-variadic-call.ll | 2 +-
.../AMDGPU/fcanonicalize-elimination.ll | 4 -
.../AMDGPU/finalize-isel-kill-scc-vcc.mir | 2 +-
.../AMDGPU/flat-error-unsupported-gpu-hsa.ll | 2 +-
...96582-late-codegenprepare-crash-non-po2.ll | 2 +-
.../AMDGPU/lds-dma-workgroup-release.ll | 2 +-
...lvm.amdgcn.raw.ptr.buffer.load-exported.ll | 8 +-
...mdgcn.struct.ptr.buffer.format.i8.xfail.ll | 4 +-
.../AMDGPU/lower-buffer-fat-pointers-calls.ll | 16 +-
.../lower-buffer-fat-pointers-constants.ll | 87 ++---
...ointers-contents-legalization-alignment.ll | 258 ++++++-------
...ffer-fat-pointers-contents-legalization.ll | 352 +++++++++---------
.../lower-buffer-fat-pointers-control-flow.ll | 28 +-
.../lower-buffer-fat-pointers-mem-transfer.ll | 6 +-
.../lower-buffer-fat-pointers-memops.ll | 16 +-
.../lower-buffer-fat-pointers-p7-in-memory.ll | 14 +-
.../lower-buffer-fat-pointers-pointer-ops.ll | 106 +++---
...fer-fat-pointers-unoptimized-debug-data.ll | 114 +++---
.../mcinstlower-external-symbol-reloc.mir | 4 +-
llvm/test/CodeGen/AMDGPU/noop-shader-O0.ll | 2 -
.../CodeGen/AMDGPU/pack-half-to-lshl-or.ll | 12 +-
.../CodeGen/AMDGPU/packed_shl64_combine.ll | 2 +-
.../AMDGPU/phi-elimination-assertion.mir | 4 +-
.../CodeGen/AMDGPU/phi-elimination-end-cf.mir | 4 +-
.../CodeGen/AMDGPU/rewrite-out-arguments-2.ll | 2 +-
.../AMDGPU/s-barrier-signal-var-gep.ll | 8 +-
.../sched-handleMoveUp-dead-def-join.mir | 1 -
.../si-pre-allocate-wwwmregs-dbg-noreg.mir | 13 +-
.../CodeGen/AMDGPU/strict_fptrunc_bf16.ll | 4 +-
.../AMDGPU/subreg-coalescer-undef-use.ll | 1 -
llvm/test/CodeGen/AMDGPU/v_mov_b64-isel.ll | 6 +-
.../CodeGen/AMDGPU/vgpr-setreg-pred-block.mir | 2 +-
.../GlobalISel/irtranslator-byte-type.ll | 2 +-
llvm/test/CodeGen/Generic/bfloat-op.ll | 2 +-
llvm/test/CodeGen/Generic/bfloat.ll | 2 +-
llvm/test/CodeGen/Generic/half-op.ll | 2 +-
llvm/test/CodeGen/Generic/half.ll | 2 +-
llvm/test/CodeGen/Generic/live-debug-label.ll | 2 +-
.../MIR/AMDGPU/empty-custom-regmask.mir | 2 +-
.../MIR/AMDGPU/expected-target-index-name.mir | 2 +-
llvm/test/CodeGen/MIR/AMDGPU/intrinsics.mir | 2 +-
...nvalid-frame-index-invalid-fixed-stack.mir | 2 +-
.../invalid-frame-index-invalid-stack.mir | 2 +-
.../AMDGPU/invalid-frame-index-no-stack.mir | 2 +-
.../MIR/AMDGPU/invalid-frame-index.mir | 2 +-
.../MIR/AMDGPU/invalid-frame-index2.mir | 2 +-
.../AMDGPU/invalid-target-index-operand.mir | 2 +-
.../llc-target-cpu-attr-from-cmdline-ir.mir | 10 +-
.../llc-target-cpu-attr-from-cmdline.mir | 4 +-
.../AMDGPU/long-branch-reg-all-sgpr-used.ll | 2 +-
.../test/CodeGen/MIR/AMDGPU/lr-split-flag.mir | 2 +-
...unction-info-dynlds-align-invalid-case.mir | 2 +-
...ine-function-info-long-branch-reg-debug.ll | 2 +-
.../machine-function-info-long-branch-reg.ll | 2 +-
.../AMDGPU/machine-function-info-no-ir.mir | 4 +-
...ne-function-info-register-parse-error1.mir | 2 +-
...ne-function-info-register-parse-error2.mir | 2 +-
.../MIR/AMDGPU/mfi-frame-offset-reg-class.mir | 2 +-
.../mfi-parse-error-frame-offset-reg.mir | 2 +-
.../mfi-parse-error-scratch-rsrc-reg.mir | 2 +-
.../mfi-parse-error-stack-ptr-offset-reg.mir | 2 +-
.../AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir | 2 +-
.../AMDGPU/mfi-stack-ptr-offset-reg-class.mir | 2 +-
.../MIR/AMDGPU/mir-canon-multi-def.mir | 2 +-
.../CodeGen/MIR/AMDGPU/mir-canon-multi.mir | 4 +-
.../MIR/AMDGPU/noconvergent-invalid.mir | 2 +-
llvm/test/CodeGen/MIR/AMDGPU/noconvergent.mir | 2 +-
.../parse-lanemask-operand-empty-lanemask.mir | 2 +-
...arse-lanemask-operand-invalid-lanemask.mir | 2 +-
.../parse-lanemask-operand-missing-lparen.mir | 2 +-
.../parse-lanemask-operand-missing-rparen.mir | 2 +-
.../MIR/AMDGPU/parse-lanemask-operand.mir | 2 +-
.../MIR/AMDGPU/parse-order-reserved-regs.mir | 6 +-
.../s_wait_alu_missing_operand_crash.mir | 2 +-
.../s_waitcnt_missing_operand_crash.mir | 2 +-
.../AMDGPU/sgpr-for-exec-copy-invalid-reg.mir | 2 +-
.../MIR/AMDGPU/spill-phys-vgprs-invalid.mir | 2 +-
.../MIR/AMDGPU/spill-phys-vgprs-not-a-reg.mir | 2 +-
.../CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir | 2 +-
.../CodeGen/MIR/AMDGPU/stack-id-assert.mir | 2 +-
llvm/test/CodeGen/MIR/AMDGPU/stack-id.mir | 2 +-
llvm/test/CodeGen/MIR/AMDGPU/target-flags.mir | 2 +-
.../MIR/AMDGPU/target-index-operands.mir | 2 +-
.../CodeGen/MIR/AMDGPU/target-memoperands.mir | 2 +-
.../AMDGPU/vgpr-for-agpr-copy-invalid-reg.mir | 2 +-
.../AMDGPU/wwm-reserved-regs-invalid-reg.mir | 2 +-
.../AMDGPU/wwm-reserved-regs-not-a-reg.mir | 2 +-
.../CodeGen/MIR/AMDGPU/wwm-reserved-regs.mir | 4 +-
.../AMDGPU/asan_do_not_internalize.ll | 8 +-
.../AMDGPU/asan_instrument_mem_intrinsics.ll | 2 +-
.../InstrProfiling/amdgpu-3d-grid.ll | 2 +-
.../amdgpu-contiguous-counters.ll | 2 +-
.../InstrProfiling/amdgpu-instrumentation.ll | 4 +-
.../InstrProfiling/amdgpu-uniform-counters.ll | 2 +-
.../InstrProfiling/amdgpu-wave32.ll | 2 +-
.../InstrProfiling/amdgpu-wave64.ll | 2 +-
.../InstrProfiling/platform.ll | 2 +-
.../LTO/AMDGPU/closed-world-assumption.ll | 6 +-
.../AMDGPU/undef-virt-reg-entry-block.mir | 2 +-
...licit-virtreg-invalid-physreg-liveness.mir | 2 +-
.../AMDGPU/verify-implicit-def.mir | 2 +-
.../MachineVerifier/AMDGPU/writelane_m0.mir | 16 +-
.../convergencectrl/AMDGPU/cycles.mir | 2 +-
.../convergencectrl/AMDGPU/mixed2.mir | 2 +-
.../convergencectrl/AMDGPU/region-nesting.mir | 2 +-
.../stack-protector-offset.mir | 2 +-
llvm/test/ThinLTO/AMDGPU/force-import-all.ll | 4 +-
.../Attributor/heap_to_stack_gpu.ll | 2 +-
.../Attributor/memory_locations_gpu.ll | 2 +-
.../reduced/openmp_opt_constant_type_crash.ll | 2 +-
.../Attributor/value-simplify-gpu.ll | 2 +-
.../FunctionAttrs/make-buffer-rsrc.ll | 2 -
.../AMDGPU/addrspace-7-doesnt-crash.ll | 2 +-
.../AMDGPU/phi-with-incoming-from-load.ll | 2 +-
.../InstCombine/AMDGPU/select-from-load.ll | 2 +-
.../LICM/AMDGPU/buffer-rsrc-ptrs.ll | 2 +-
.../AMDGPU/adjust-alloca-alignment.ll | 10 +-
.../AMDGPU/dont-adjust-globalobj-alignment.ll | 4 +-
.../LoopLoadElim/pr46854-adress-spaces.ll | 2 +-
.../AMDGPU/lsr-icmpzero-mixed-ptr-width.ll | 6 +-
.../AMDGPU/lsr-void-inseltpoison.ll | 2 +-
.../AMDGPU/scev-mul-expansion-cost.ll | 2 +-
.../OpenMP/add_attributes_amdgcn.ll | 2 +-
.../test/Transforms/OpenMP/barrier_removal.ll | 2 +-
.../OpenMP/indirect_call_kernel_info_crash.ll | 2 +-
.../OpenMP/spmdization_constant_prop.ll | 14 +-
.../OpenMP/spmdization_kernel_env_dep.ll | 4 +-
.../OpenMP/value-simplify-openmp-opt.ll | 2 +-
.../amdgpu-disable-value-profiling.ll | 2 +-
llvm/test/Transforms/PhaseOrdering/varargs.ll | 4 +-
.../AMDGPU/lower-gep.ll | 2 +-
.../AMDGPU/pr23975.ll | 2 +-
.../StructurizeCFG/hoist-zerocost-nested.ll | 2 +-
.../rebuild-ssa-infinite-loop-inseltpoison.ll | 2 +-
.../rebuild-ssa-infinite-loop.ll | 2 +-
.../Inputs/amdgpu_no_merge_comments.ll | 2 +-
.../amdgpu_no_merge_comments.ll.expected | 2 +-
.../llvm-objdump/ELF/AMDGPU/source-lines.ll | 2 -
.../Offloading/Inputs/binary.yaml | 4 +-
.../tools/llvm-objdump/Offloading/coff.test | 4 +-
.../tools/llvm-objdump/Offloading/elf.test | 4 +-
180 files changed, 734 insertions(+), 796 deletions(-)
diff --git a/llvm/test/Analysis/CostModel/AMDGPU/fsub.ll b/llvm/test/Analysis/CostModel/AMDGPU/fsub.ll
index 3b9ba5ac2a06b..8a6462165e526 100644
--- a/llvm/test/Analysis/CostModel/AMDGPU/fsub.ll
+++ b/llvm/test/Analysis/CostModel/AMDGPU/fsub.ll
@@ -6,7 +6,7 @@
; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgpu9.0a-unknown-amdhsa -mattr=+half-rate-64-ops < %s | FileCheck -check-prefixes=FASTF16-SIZE,GFX90A-FASTF64-SIZE %s
; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgpu9.00-unknown-amdhsa -mattr=+half-rate-64-ops < %s | FileCheck -check-prefixes=NOPACKEDF32-SIZE,FASTF16-SIZE %s
; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgpu6.01-unknown-amdhsa -mattr=-half-rate-64-ops < %s | FileCheck -check-prefixes=NOPACKEDF32-SIZE,SLOWF64-SIZE %s
-; RUN opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250-SIZE %s
+; RUN opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgpu12.50-unknown-amdhsa < %s | FileCheck -check-prefixes=GFX1250-SIZE %s
; END.
define amdgpu_kernel void @fsub_f32() #0 {
diff --git a/llvm/test/Analysis/CostModel/AMDGPU/fused_costs.ll b/llvm/test/Analysis/CostModel/AMDGPU/fused_costs.ll
index d976a03e3b50d..98773ba7292f4 100644
--- a/llvm/test/Analysis/CostModel/AMDGPU/fused_costs.ll
+++ b/llvm/test/Analysis/CostModel/AMDGPU/fused_costs.ll
@@ -10,8 +10,6 @@
; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgpu10.30-unknown-amdhsa -denormal-fp-math-f32=preserve-sign -denormal-fp-math=preserve-sign -fp-contract=on < %s | FileCheck -check-prefixes=SLOWF64-SIZE,FUSED-SIZE,FASTF32-SIZE %s
; END.
-target triple = "amdgcn--"
-
define void @fmul_fadd_f32() #0 {
; SLOWF32-LABEL: 'fmul_fadd_f32'
; SLOWF32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f32 = fmul float undef, undef
diff --git a/llvm/test/Analysis/DotMachineCFG/AMDGPU/functions.mir b/llvm/test/Analysis/DotMachineCFG/AMDGPU/functions.mir
index e3527f589e7a1..1c29a62324767 100644
--- a/llvm/test/Analysis/DotMachineCFG/AMDGPU/functions.mir
+++ b/llvm/test/Analysis/DotMachineCFG/AMDGPU/functions.mir
@@ -1,7 +1,7 @@
-# RUN: llc -mtriple=amdgcn-- -run-pass=dot-machine-cfg -mcfg-dot-filename-prefix=%t -mcfg-func-name=func2 -o - %s -filetype=null 2>&1
+# RUN: llc -mtriple=amdgpu6.00-- -run-pass=dot-machine-cfg -mcfg-dot-filename-prefix=%t -mcfg-func-name=func2 -o - %s -filetype=null 2>&1
# RUN: FileCheck %s -input-file=%t.func2.dot --check-prefix=MCFG
-# RUN: llc -mtriple=amdgcn-- -passes=dot-machine-cfg -mcfg-dot-filename-prefix=%t -mcfg-func-name=func2 -o - %s -filetype=null 2>&1
+# RUN: llc -mtriple=amdgpu6.00-- -passes=dot-machine-cfg -mcfg-dot-filename-prefix=%t -mcfg-func-name=func2 -o - %s -filetype=null 2>&1
# RUN: FileCheck %s -input-file=%t.func2.dot --check-prefix=MCFG
# MCFG-NOT: digraph "Machine CFG for 'func1' function"
diff --git a/llvm/test/Analysis/DotMachineCFG/AMDGPU/irreducible.mir b/llvm/test/Analysis/DotMachineCFG/AMDGPU/irreducible.mir
index ed84f5590ff41..5c32c7f5bba75 100644
--- a/llvm/test/Analysis/DotMachineCFG/AMDGPU/irreducible.mir
+++ b/llvm/test/Analysis/DotMachineCFG/AMDGPU/irreducible.mir
@@ -1,11 +1,11 @@
-# RUN: llc -mtriple=amdgcn-- -run-pass=dot-machine-cfg -mcfg-dot-filename-prefix=%t -o - %s -filetype=null 2>&1
+# RUN: llc -mtriple=amdgpu6.00-- -run-pass=dot-machine-cfg -mcfg-dot-filename-prefix=%t -o - %s -filetype=null 2>&1
# RUN: FileCheck %s -input-file=%t.irreducible.dot --check-prefix=MCFG
-# RUN: llc -mtriple=amdgcn-- -run-pass=dot-machine-cfg -mcfg-dot-filename-prefix=%t -dot-mcfg-only -o - %s -filetype=null 2>&1
+# RUN: llc -mtriple=amdgpu6.00-- -run-pass=dot-machine-cfg -mcfg-dot-filename-prefix=%t -dot-mcfg-only -o - %s -filetype=null 2>&1
# RUN: FileCheck %s -input-file=%t.irreducible.dot --check-prefix=MCFG-ONLY
-# RUN: llc -mtriple=amdgcn-- -passes=dot-machine-cfg -mcfg-dot-filename-prefix=%t -o - %s -filetype=null 2>&1
+# RUN: llc -mtriple=amdgpu6.00-- -passes=dot-machine-cfg -mcfg-dot-filename-prefix=%t -o - %s -filetype=null 2>&1
# RUN: FileCheck %s -input-file=%t.irreducible.dot --check-prefix=MCFG
-# RUN: llc -mtriple=amdgcn-- -passes=dot-machine-cfg -mcfg-dot-filename-prefix=%t -dot-mcfg-only -o - %s -filetype=null 2>&1
+# RUN: llc -mtriple=amdgpu6.00-- -passes=dot-machine-cfg -mcfg-dot-filename-prefix=%t -dot-mcfg-only -o - %s -filetype=null 2>&1
# RUN: FileCheck %s -input-file=%t.irreducible.dot --check-prefix=MCFG-ONLY
# MCFG: digraph "Machine CFG for 'irreducible' function"
diff --git a/llvm/test/Analysis/Lint/const-store.ll b/llvm/test/Analysis/Lint/const-store.ll
index 748f752b2975f..584fefd53b8b5 100644
--- a/llvm/test/Analysis/Lint/const-store.ll
+++ b/llvm/test/Analysis/Lint/const-store.ll
@@ -1,5 +1,5 @@
-; RUN: not opt --mtriple=amdgcn --passes='lint<abort-on-error>' %s -disable-output 2>&1 | FileCheck %s
-; RUN: opt --mtriple=amdgcn --mcpu=gfx1030 --passes=lint %s -disable-output 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK0
+; RUN: not opt --mtriple=amdgpu6.00 --passes='lint<abort-on-error>' %s -disable-output 2>&1 | FileCheck %s
+; RUN: opt --mtriple=amdgpu10.30 --passes=lint %s -disable-output 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK0
; RUN: opt --mtriple=x86_64 --passes='lint<abort-on-error>' %s -disable-output 2>&1 | FileCheck %s --allow-empty --check-prefix=NOERR
; NOERR: {{^$}}
diff --git a/llvm/test/Analysis/MemorySSA/ptr-const-mem.ll b/llvm/test/Analysis/MemorySSA/ptr-const-mem.ll
index badcfbba0f5f0..3199f6946a759 100644
--- a/llvm/test/Analysis/MemorySSA/ptr-const-mem.ll
+++ b/llvm/test/Analysis/MemorySSA/ptr-const-mem.ll
@@ -1,5 +1,5 @@
; RUN: opt -aa-pipeline=basic-aa -passes='print<memoryssa>' -verify-memoryssa -disable-output -memssa-check-limit=0 < %s 2>&1 | FileCheck %s
-target triple = "amdgcn"
+target triple = "amdgpu6.00"
@g4 = external unnamed_addr constant i8, align 1
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform-gmir.mir b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform-gmir.mir
index 8f44855b3caff..773df75a4dcdf 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform-gmir.mir
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform-gmir.mir
@@ -1,6 +1,6 @@
# NOTE: This file is Generic MIR translation of test/Analysis/UniformityAnalysis/AMDGPU/always_uniform.ll test file
-# RUN: llc -mtriple=amdgcn-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
-# RUN: llc -mtriple=amdgcn-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
---
name: readfirstlane
body: |
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/atomics-gmir.mir b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/atomics-gmir.mir
index d7862e8373121..8292118fe7d2d 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/atomics-gmir.mir
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/atomics-gmir.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
-# RUN: llc -mtriple=amdgcn-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu7.00-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu7.00-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
---
name: test1
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/atomics.mir b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/atomics.mir
index 432582197f652..f84120b6713d7 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/atomics.mir
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/atomics.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
-# RUN: llc -mtriple=amdgcn-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
---
name: test1
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-diverge-gmir.mir b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-diverge-gmir.mir
index 27c53815feb06..118272d8d73ed 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-diverge-gmir.mir
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-diverge-gmir.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
-# RUN: llc -mtriple=amdgcn-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
# CHECK-LABEL: MachineUniformityInfo for function: @hidden_diverge
# CHECK-LABEL: BLOCK bb.0
# CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.x)
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-loop-diverge.mir b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-loop-diverge.mir
index fd811e276c593..f06bbebe12676 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-loop-diverge.mir
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-loop-diverge.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
-# RUN: llc -mtriple=amdgcn-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
# CHECK-LABEL: MachineUniformityInfo for function: @hidden_loop_diverge
# CHECK-LABEL: BLOCK bb.0
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/branch-outside-gmir.mir b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/branch-outside-gmir.mir
index c61113b976a69..5c735787da8bb 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/branch-outside-gmir.mir
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/branch-outside-gmir.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
-# RUN: llc -mtriple=amdgcn-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
# CHECK-LABEL: MachineUniformityInfo for function: @basic
# CHECK-NEXT: CYCLES ASSUMED DIVERGENT:
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/diverged-entry-basic-gmir.mir b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/diverged-entry-basic-gmir.mir
index dfa05f44bd7eb..b6de0d6ec093d 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/diverged-entry-basic-gmir.mir
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/diverged-entry-basic-gmir.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
-# RUN: llc -mtriple=amdgcn-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu7.00-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu7.00-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
# CHECK-LABEL: MachineUniformityInfo for function: @divergent_cycle_1
# CHECK-NEXT: CYCLES ASSUMED DIVERGENT:
# CHECK-NEXT: depth=1: entries(bb.3 bb.1) bb.4 bb.2
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/exit-divergence-gmir.mir b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/exit-divergence-gmir.mir
index 8627db017eaf0..fb938e93c7665 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/exit-divergence-gmir.mir
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/exit-divergence-gmir.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
-# RUN: llc -mtriple=amdgcn-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu7.00-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu7.00-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
# CHECK-LABEL: MachineUniformityInfo for function: @basic
# CHECK-NOT: CYCLES ASSUMED DIVERGENT:
# CHECK: CYCLES WITH DIVERGENT EXIT:
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/irreducible-2-gmir.mir b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/irreducible-2-gmir.mir
index 575092d6f4be6..90aad6fadbaf7 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/irreducible-2-gmir.mir
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/irreducible-2-gmir.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
-# RUN: llc -mtriple=amdgcn-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
# bb0(div)
# / \
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/join-loopexit-gmir.mir b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/join-loopexit-gmir.mir
index ffafb9b3ba633..8a1a713020b4f 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/join-loopexit-gmir.mir
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/join-loopexit-gmir.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
-# RUN: llc -mtriple=amdgcn-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
# CHECK-LABEL: MachineUniformityInfo for function: @test
# CHECK-LABEL: BLOCK bb.0
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/loads-gmir.mir b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/loads-gmir.mir
index d799cd2057f47..cfda128bbbc52 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/loads-gmir.mir
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/loads-gmir.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
-# RUN: llc -mtriple=amdgcn-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
---
name: loads
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/never-uniform-gmir.mir b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/never-uniform-gmir.mir
index e59410179b526..24825209b090f 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/never-uniform-gmir.mir
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/never-uniform-gmir.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
-# RUN: llc -mtriple=amdgcn-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
# whole wave func setup (original exec mask) is a divergence source
---
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/temporal-divergence.mir b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/temporal-divergence.mir
index a0f637b24e5ab..4251549ba1c1b 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/temporal-divergence.mir
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/temporal-divergence.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
-# RUN: llc -mtriple=amdgcn-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
---
# CHECK-LABEL: MachineUniformityInfo for function: @temporal_diverge
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/deprecated/hidden-diverge.mir b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/deprecated/hidden-diverge.mir
index 7d3eaee02c387..637b348e41dcb 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/deprecated/hidden-diverge.mir
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/deprecated/hidden-diverge.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
-# RUN: llc -mtriple=amdgcn-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
# This test was generated using SelectionDAG, where the compilation flow does
# not match the assumptions made in MachineUA. For now, this test mostly serves
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/deprecated/irreducible-1.mir b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/deprecated/irreducible-1.mir
index 97dfbd05cf242..6cd12b37aea33 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/deprecated/irreducible-1.mir
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/deprecated/irreducible-1.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
-# RUN: llc -mtriple=amdgcn-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00-- -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
# This test was generated using SelectionDAG, where the compilation flow does
# not match the assumptions made in MachineUA. For now, this test mostly serves
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/irreducible-2.ll b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/irreducible-2.ll
index 91b444647f8bf..05466fe1c2699 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/irreducible-2.ll
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/irreducible-2.ll
@@ -1,4 +1,4 @@
-; RUN: opt %s -mtriple amdgcn-- -passes='print<uniformity>' -disable-output 2>&1 | FileCheck %s
+; RUN: opt %s -mtriple=amdgpu6.00-- -passes='print<uniformity>' -disable-output 2>&1 | FileCheck %s
define amdgpu_kernel void @cycle_diverge_enter(i32 %n, i32 %a, i32 %b) #0 {
; entry(div)
diff --git a/llvm/test/Assembler/amdgpu-image-atomic-attributes.ll b/llvm/test/Assembler/amdgpu-image-atomic-attributes.ll
index bc03908d5f218..6d12c8c63a8a3 100644
--- a/llvm/test/Assembler/amdgpu-image-atomic-attributes.ll
+++ b/llvm/test/Assembler/amdgpu-image-atomic-attributes.ll
@@ -1,4 +1,4 @@
-; RUN: opt -S -mtriple=amdgcn-unknown-unknown < %s | FileCheck %s
+; RUN: opt -S -mtriple=amdgpu-unknown-unknown < %s | FileCheck %s
define amdgpu_ps float @atomic_swap_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
main_body:
@@ -188,4 +188,4 @@ declare i32 @llvm.amdgcn.image.atomic.add.2darraymsaa.i32.i32(i32, i32, i32, i32
;.
; CHECK: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nounwind willreturn }
-;.
\ No newline at end of file
+;.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extendedLLTs-err.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extendedLLTs-err.mir
index 340f4ab72c590..277fa3082ecfa 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extendedLLTs-err.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extendedLLTs-err.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -o /dev/null 2>&1 | FileCheck -check-prefix=ERR %s
+# RUN: llc -mtriple=amdgpu12.50 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -o /dev/null 2>&1 | FileCheck -check-prefix=ERR %s
# ERR: remark: <unknown>:0:0: cannot select: %2:vcc(s1) = G_FCMP floatpred(oeq), %1:vgpr(s32), %0:vgpr (in function: g_fcmp_op2_fconstant_s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extendedLLTs.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extendedLLTs.mir
index 43863c6719318..b13c1dbbc9f04 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extendedLLTs.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extendedLLTs.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -o - 2> %t | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgpu12.50 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -o - 2> %t | FileCheck -check-prefix=GCN %s
# G_ADD i32: -> tablegen S_ADD_I32;
# G_ADD s32: -> manual S_ADD_U32; selectG_ADD_SUB
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.offset-split.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.offset-split.ll
index d905fa73c3a88..ac231b5a35e39 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.offset-split.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.offset-split.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -verify-machineinstrs < %s | FileCheck --check-prefix=GFX8 %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 -amdgpu-enable-delay-alu=0 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX1250 %s
+; RUN: llc -global-isel -mtriple=amdgpu8.03-mesa-mesa3d -verify-machineinstrs < %s | FileCheck --check-prefix=GFX8 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.50-mesa-mesa3d -amdgpu-enable-delay-alu=0 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX1250 %s
define amdgpu_ps float @raw_ptr_buffer_load_f32__sgpr_rsrc__voffset67108860_soffset16(ptr addrspace(8) inreg %rsrc) {
; GFX8-LABEL: raw_ptr_buffer_load_f32__sgpr_rsrc__voffset67108860_soffset16:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/merge-values-s16-true16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/merge-values-s16-true16.ll
index fc0df6181b7d9..fc1be777b09a3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/merge-values-s16-true16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/merge-values-s16-true16.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1150 < %s | FileCheck -check-prefix=GFX1150 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.50-amd-amdhsa < %s | FileCheck -check-prefix=GFX1150 %s
declare i32 @llvm.amdgcn.workitem.id.x()
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_dpp_lds_expected_active_lanes.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_dpp_lds_expected_active_lanes.ll
index 94509810a5ebd..cfaa9278c507f 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_dpp_lds_expected_active_lanes.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_dpp_lds_expected_active_lanes.ll
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
;
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32 -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1032 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1064 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32 -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1132 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1164 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32 -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1232 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1264 %s
+; RUN: llc -mtriple=amdgpu10.10 -mattr=+wavefrontsize32 -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1032 %s
+; RUN: llc -mtriple=amdgpu10.10 -mattr=+wavefrontsize64 -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1064 %s
+; RUN: llc -mtriple=amdgpu11.00 -mattr=+wavefrontsize32 -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1132 %s
+; RUN: llc -mtriple=amdgpu11.00 -mattr=+wavefrontsize64 -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1164 %s
+; RUN: llc -mtriple=amdgpu12.00 -mattr=+wavefrontsize32 -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1232 %s
+; RUN: llc -mtriple=amdgpu12.00 -mattr=+wavefrontsize64 -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1264 %s
declare i32 @llvm.amdgcn.workitem.id.x()
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
index ba9f363d66e11..70106cf0838cd 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
@@ -12,8 +12,6 @@
; for buffer-related memcpy() calls turns into something reasonable in
; the backend, despite the wide intermediate vectors
-target triple = "amdgcn--"
-
;; memcpy
declare void @llvm.memcpy.p7.p7.i32(ptr addrspace(7), ptr addrspace(7), i32, i1)
diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir b/llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir
index 124759ee40798..58994a9acf9aa 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir
+++ b/llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir
@@ -6,8 +6,6 @@
# GCN: {{^body}}
--- |
- target triple = "amdgcn--amdpal"
-
define amdgpu_cs void @_amdgpu_cs_main(<3 x i32>) #0 {
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir b/llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir
index b28a8f76f3647..88717d21a05be 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir
+++ b/llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir
@@ -6,9 +6,6 @@
# GCN: {{^body}}
--- |
- target triple = "amdgcn--amdpal"
-
- ; Function Attrs: nounwind
define amdgpu_ps void @_amdgpu_ps_main(float %arg) #0 {
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir b/llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir
index ba7a78409aa30..3beb6b6f02d36 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir
+++ b/llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir
@@ -15,8 +15,6 @@
#
--- |
- target triple = "amdgcn--amdpal"
-
define amdgpu_ps void @main() {
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir b/llvm/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir
index 70de17b45a962..481befdb0e187 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir
+++ b/llvm/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir
@@ -6,9 +6,6 @@
# GCN: {{^body}}
--- |
- target triple = "amdgcn--amdpal"
-
- ; Function Attrs: nounwind
define amdgpu_cs void @_amdgpu_cs_main(<3 x i32> %arg) #0 {
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/coexec-rewrite-mfma.ll b/llvm/test/CodeGen/AMDGPU/coexec-rewrite-mfma.ll
index 23453728d70c1..17e1012c05f6a 100644
--- a/llvm/test/CodeGen/AMDGPU/coexec-rewrite-mfma.ll
+++ b/llvm/test/CodeGen/AMDGPU/coexec-rewrite-mfma.ll
@@ -13,8 +13,6 @@
; CHECK-COUNT-28: v_mfma_f32_16x16x32_f16 a
; CHECK-NOT: v_mfma_f32_16x16x32_f16 v
-target triple = "amdgcn-amd-amdhsa"
-
define amdgpu_kernel void @v5_local_prefetch() #0 {
.lr.ph:
%0 = load <8 x half>, ptr addrspace(3) null, align 16
diff --git a/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll b/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
index 68abe6a409e66..1f347ea68e0ab 100644
--- a/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
+++ b/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
@@ -4,7 +4,7 @@
; checks are looking for the absence of specific metadata, which
; cannot be expressed reliably by the generated checks.
-; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck %s -check-prefix=ISA
+; RUN: llc < %s | FileCheck %s -check-prefix=ISA
; RUN: opt --amdgpu-annotate-uniform -S %s | FileCheck %s -check-prefix=UNIFORM
; RUN: opt --amdgpu-annotate-uniform --si-annotate-control-flow -S %s | FileCheck %s -check-prefix=CONTROLFLOW
@@ -13,7 +13,7 @@
; not. This test ensures that the divergence of the branch is tested,
; not its condition, so that branch is correctly emitted as divergent.
-target triple = "amdgcn-mesa-mesa3d"
+target triple = "amdgpu9.00-mesa-mesa3d"
define amdgpu_ps void @main(i32 %0, float %1) {
; ISA-LABEL: main:
diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-flat-scratch-svs.mir b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-flat-scratch-svs.mir
index 1d377af057377..083312e451426 100644
--- a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-flat-scratch-svs.mir
+++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-flat-scratch-svs.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -run-pass=prolog-epilog -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX950 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -run-pass=prolog-epilog -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX11 %s
+# RUN: llc -mtriple=amdgpu9.50-amd-amdhsa -run-pass=prolog-epilog -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX950 %s
+# RUN: llc -mtriple=amdgpu11.00-amd-amdhsa -run-pass=prolog-epilog -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX11 %s
# When flat scratch is enabled and no SGPR can be scavenged to replace a frame
# index (and there is no frame register available, as in an entry function with
diff --git a/llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr-hsa.ll b/llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr-hsa.ll
index eee79fae87040..4c4890d346e14 100644
--- a/llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr-hsa.ll
+++ b/llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr-hsa.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck --check-prefix=HSA %s
+; RUN: llc -mtriple=amdgpu11.00-amd-amdhsa < %s | FileCheck --check-prefix=HSA %s
; Verify that V_MOV_B64_PSEUDO and S_MOV_B64_IMM_PSEUDO preserve non-ABS
; relocation intent on HSA and lower via gotpcrel32 lo/hi address materialization.
diff --git a/llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr-rel32.mir b/llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr-rel32.mir
index 3827dc2dd1eb1..d1f4b994c6224 100644
--- a/llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr-rel32.mir
+++ b/llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr-rel32.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs -run-pass=postrapseudos -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu11.00-amd-amdhsa -verify-machineinstrs -run-pass=postrapseudos -o - %s | FileCheck %s
# This test verifies that rel32 target flags on 64-bit global-address pseudos
# are split into rel32 lo/hi flags when post-RA pseudos are expanded.
diff --git a/llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr.ll b/llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr.ll
index f59b2d1f59847..6316bd2c2d450 100644
--- a/llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr.ll
+++ b/llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10 %s
-; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1100 < %s | FileCheck --check-prefix=GFX11 %s
+; RUN: llc -mtriple=amdgpu10.10--amdpal < %s | FileCheck --check-prefix=GFX10 %s
+; RUN: llc -mtriple=amdgpu11.00--amdpal < %s | FileCheck --check-prefix=GFX11 %s
; Verify that V_MOV_B64_PSEUDO and S_MOV_B64_IMM_PSEUDO are expanded into a
; pair of 32-bit moves of the absolute hi/lo halves of a global address when
diff --git a/llvm/test/CodeGen/AMDGPU/expand-variadic-call.ll b/llvm/test/CodeGen/AMDGPU/expand-variadic-call.ll
index 839d0ba35cf11..fcdf01d96ba9c 100644
--- a/llvm/test/CodeGen/AMDGPU/expand-variadic-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/expand-variadic-call.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: -p --function-signature
; RUN: opt -S --passes=expand-variadics --expand-variadics-override=lowering < %s | FileCheck %s
-target triple = "amdgcn-amd-amdhsa"
+target triple = "amdgpu7.00-amd-amdhsa"
; Check the variables are lowered to the locations this target expects
diff --git a/llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll b/llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll
index 125c9f09be8b1..838042b79ae94 100644
--- a/llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll
@@ -913,10 +913,6 @@ define float @v_test_canonicalize_maximumnum(float %a, float %b) {
ret float %canonicalized
}
-; Avoid failing the test on FreeBSD11.0 which will match the GCN-NOT: 1.0
-; in the .amd_amdgpu_isa "amdgcn-unknown-freebsd11.0--gfx802" directive
-; GCN: .amd_amdgpu_isa
-
declare float @llvm.canonicalize.f32(float) #0
declare float @llvm.copysign.f32(float, float) #0
declare float @llvm.amdgcn.fmul.legacy(float, float) #0
diff --git a/llvm/test/CodeGen/AMDGPU/finalize-isel-kill-scc-vcc.mir b/llvm/test/CodeGen/AMDGPU/finalize-isel-kill-scc-vcc.mir
index c33ed34e8cb40..ce65c4d4d2102 100644
--- a/llvm/test/CodeGen/AMDGPU/finalize-isel-kill-scc-vcc.mir
+++ b/llvm/test/CodeGen/AMDGPU/finalize-isel-kill-scc-vcc.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgcn -run-pass finalize-isel -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu10.10 -run-pass finalize-isel -verify-machineinstrs %s -o - | FileCheck %s
---
name: phi_use_def_before_kill
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/AMDGPU/flat-error-unsupported-gpu-hsa.ll b/llvm/test/CodeGen/AMDGPU/flat-error-unsupported-gpu-hsa.ll
index 1984d455bd82a..b5e33f4b840c2 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-error-unsupported-gpu-hsa.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-error-unsupported-gpu-hsa.ll
@@ -1,7 +1,7 @@
; RUN: not --crash llc -mtriple=amdgpu6.00-amd-amdhsa -filetype=obj -filetype=null %s 2>&1 | FileCheck -check-prefix=ERROR %s
; RUN: not --crash llc -mtriple=amdgpu6.00-mesa-mesa3d -filetype=obj -filetype=null %s 2>&1 | FileCheck -check-prefix=ERROR %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -o - %s | FileCheck -check-prefix=HSA-DEFAULT %s
+; RUN: llc -mtriple=amdgpu-amd-amdhsa -o - %s | FileCheck -check-prefix=HSA-DEFAULT %s
; Flat instructions should not select if the target device doesn't
; support them. The default device should be able to select for HSA.
diff --git a/llvm/test/CodeGen/AMDGPU/issue196582-late-codegenprepare-crash-non-po2.ll b/llvm/test/CodeGen/AMDGPU/issue196582-late-codegenprepare-crash-non-po2.ll
index 8735e32739d16..174fbe91f03a5 100644
--- a/llvm/test/CodeGen/AMDGPU/issue196582-late-codegenprepare-crash-non-po2.ll
+++ b/llvm/test/CodeGen/AMDGPU/issue196582-late-codegenprepare-crash-non-po2.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
-; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-late-codegenprepare %s | FileCheck %s
+; RUN: opt -S -mtriple=amdgpu7.00-amd-amdhsa -passes=amdgpu-late-codegenprepare %s | FileCheck %s
; Make sure we don't crash on vectors with non-power-of-2 element types.
; The LiveRegOptimizer's convertToOptType cannot bitcast-pack these into
diff --git a/llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll b/llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll
index e2b05662ff99f..a958563be4007 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll
+++ b/llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll
@@ -2,7 +2,7 @@
; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck %s --check-prefixes=GFX900
; RUN: llc -mtriple=amdgpu9.0a-amd-amdhsa < %s | FileCheck %s --check-prefixes=GFX90A
; RUN: sed 's/attributes #0 = { nounwind }/attributes #0 = { nounwind "amdgpu-tg-split" }/' %s | llc -mtriple=amdgpu9.0a-amd-amdhsa | FileCheck %s --check-prefixes=GFX90A-TGSPLIT
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck %s --check-prefixes=GFX942
+; RUN: llc -mtriple=amdgpu9.42-amd-amdhsa < %s | FileCheck %s --check-prefixes=GFX942
; RUN: sed 's/attributes #0 = { nounwind }/attributes #0 = { nounwind "amdgpu-tg-split" }/' %s | llc -mtriple=amdgpu9.42-amd-amdhsa | FileCheck %s --check-prefixes=GFX942-TGSPLIT
; RUN: llc -mtriple=amdgpu10.10-amd-amdhsa < %s | FileCheck %s -check-prefixes=GFX10WGP
; RUN: llc -mtriple=amdgpu10.10-amd-amdhsa -mattr=+cumode < %s | FileCheck %s -check-prefixes=GFX10CU
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load-exported.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load-exported.ll
index 147e9000eb33f..5f7dd28a08010 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load-exported.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load-exported.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-;RUN: llc < %s -mtriple=amdgcn -mcpu=verde | FileCheck %s --check-prefixes=PREGFX10
-;RUN: llc < %s -mtriple=amdgcn -mcpu=tonga | FileCheck %s --check-prefixes=PREGFX10
-;RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 | FileCheck %s --check-prefixes=GFX10
-;RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 | FileCheck %s --check-prefixes=GFX11
+;RUN: llc < %s -mtriple=amdgpu6.01 | FileCheck %s --check-prefixes=PREGFX10
+;RUN: llc < %s -mtriple=amdgpu8.02 | FileCheck %s --check-prefixes=PREGFX10
+;RUN: llc < %s -mtriple=amdgpu10.10 | FileCheck %s --check-prefixes=GFX10
+;RUN: llc < %s -mtriple=amdgpu11.00 -amdgpu-enable-delay-alu=0 | FileCheck %s --check-prefixes=GFX11
define amdgpu_ps void @buffer_load_x1_offen_merged_and(ptr addrspace(8) inreg %rsrc, i32 %a) {
; PREGFX10-LABEL: buffer_load_x1_offen_merged_and:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.format.i8.xfail.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.format.i8.xfail.ll
index 28c4669e978e5..f5f8471f4dc1f 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.format.i8.xfail.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.format.i8.xfail.ll
@@ -1,5 +1,5 @@
-; RUN: not llc -mtriple=amdgcn -mcpu=gfx900 -filetype=null %s 2>&1 | FileCheck %s
-; RUN: not llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -filetype=null %s 2>&1 | FileCheck %s
+; RUN: not llc -global-isel=0 -mtriple=amdgpu9.00 -filetype=null %s 2>&1 | FileCheck %s
+; RUN: not llc -global-isel -mtriple=amdgpu9.00 -filetype=null %s 2>&1 | FileCheck %s
; An i8 buffer.load.format / buffer.store.format has no corresponding real
; instruction (no byte-granularity format access exists in hardware), so both
diff --git a/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-calls.ll b/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-calls.ll
index f03c4ec746cfe..cf346a8fa2064 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-calls.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-calls.ll
@@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
-; RUN: opt -S -mcpu=gfx900 -amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
-; RUN: opt -S -mcpu=gfx900 -passes=amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
+; RUN: opt -S -amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
+; RUN: opt -S -passes=amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
-target triple = "amdgcn--"
+target triple = "amdgpu9.00--"
define ptr addrspace(7) @recur.inner.1(ptr addrspace(7) %x, i32 %v) {
; CHECK-LABEL: define { ptr addrspace(8), i32 } @recur.inner.1
-; CHECK-SAME: ({ ptr addrspace(8), i32 } [[X:%.*]], i32 [[V:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } [[X:%.*]], i32 [[V:%.*]]) {
; CHECK-NEXT: bb:
; CHECK-NEXT: [[X_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[X]], 0
; CHECK-NEXT: [[X_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[X]], 1
@@ -43,7 +43,7 @@ end:
define ptr addrspace(7) @recur.inner.2(i32 %v, ptr addrspace(7) %x) {
; CHECK-LABEL: define { ptr addrspace(8), i32 } @recur.inner.2
-; CHECK-SAME: (i32 [[V:%.*]], { ptr addrspace(8), i32 } [[X:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: (i32 [[V:%.*]], { ptr addrspace(8), i32 } [[X:%.*]]) {
; CHECK-NEXT: [[X_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[X]], 0
; CHECK-NEXT: [[X_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[X]], 1
; CHECK-NEXT: [[INC:%.*]] = add i32 [[X_OFF]], 4
@@ -58,7 +58,7 @@ define ptr addrspace(7) @recur.inner.2(i32 %v, ptr addrspace(7) %x) {
define void @recur.outer(ptr addrspace(7) %x, ptr %arg) {
; CHECK-LABEL: define void @recur.outer
-; CHECK-SAME: ({ ptr addrspace(8), i32 } [[X:%.*]], ptr [[ARG:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } [[X:%.*]], ptr [[ARG:%.*]]) {
; CHECK-NEXT: [[BOUND:%.*]] = load i32, ptr [[ARG]], align 4
; CHECK-NEXT: [[RET:%.*]] = call { ptr addrspace(8), i32 } @recur.inner.1({ ptr addrspace(8), i32 } [[X]], i32 [[BOUND]])
; CHECK-NEXT: [[RET_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[RET]], 0
@@ -79,7 +79,7 @@ define void @recur.outer(ptr addrspace(7) %x, ptr %arg) {
declare ptr addrspace(7) @extern(ptr addrspace(7) %arg)
define void @caller(ptr addrspace(7) noundef nonnull %arg) {
; CHECK-LABEL: define void @caller
-; CHECK-SAME: ({ ptr addrspace(8), i32 } noundef [[ARG:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } noundef [[ARG:%.*]]) {
; CHECK-NEXT: [[ARG_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[ARG]], 0
; CHECK-NEXT: [[ARG_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[ARG]], 1
; CHECK-NEXT: [[V:%.*]] = call { ptr addrspace(8), i32 } @extern({ ptr addrspace(8), i32 } [[ARG]])
@@ -104,7 +104,7 @@ define void @caller(ptr addrspace(7) noundef nonnull %arg) {
define internal noalias noundef nonnull ptr addrspace(7) @foo(ptr addrspace(7) noalias noundef nonnull %arg) {
; CHECK-LABEL: define internal noundef { ptr addrspace(8), i32 } @foo
-; CHECK-SAME: ({ ptr addrspace(8), i32 } noundef [[ARG:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } noundef [[ARG:%.*]]) {
; CHECK-NEXT: [[ARG_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[ARG]], 0
; CHECK-NEXT: [[ARG_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[ARG]], 1
; CHECK-NEXT: [[RET:%.*]] = add nuw i32 [[ARG_OFF]], 4
diff --git a/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-constants.ll b/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-constants.ll
index 06064db0d0646..e471178394303 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-constants.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-constants.ll
@@ -1,79 +1,70 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
-; RUN: opt -S -mcpu=gfx900 -amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
-; RUN: opt -S -mcpu=gfx900 -passes=amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
+; RUN: opt -S -amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
+; RUN: opt -S -passes=amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
-target triple = "amdgcn--"
+target triple = "amdgpu9.00--"
@buf = external addrspace(8) global i8
@flat = external global i8
define ptr addrspace(7) @null() {
-; CHECK-LABEL: define { ptr addrspace(8), i32 } @null
-; CHECK-SAME: () #[[ATTR0:[0-9]+]] {
+; CHECK-LABEL: define { ptr addrspace(8), i32 } @null() {
; CHECK-NEXT: ret { ptr addrspace(8), i32 } zeroinitializer
;
ret ptr addrspace(7) null
}
define <2 x ptr addrspace(7)> @null_vector() {
-; CHECK-LABEL: define { <2 x ptr addrspace(8)>, <2 x i32> } @null_vector
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define { <2 x ptr addrspace(8)>, <2 x i32> } @null_vector() {
; CHECK-NEXT: ret { <2 x ptr addrspace(8)>, <2 x i32> } zeroinitializer
;
ret <2 x ptr addrspace(7)> zeroinitializer
}
define ptr addrspace(7) @undef() {
-; CHECK-LABEL: define { ptr addrspace(8), i32 } @undef
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define { ptr addrspace(8), i32 } @undef() {
; CHECK-NEXT: ret { ptr addrspace(8), i32 } undef
;
ret ptr addrspace(7) undef
}
define <2 x ptr addrspace(7)> @undef_vec() {
-; CHECK-LABEL: define { <2 x ptr addrspace(8)>, <2 x i32> } @undef_vec
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define { <2 x ptr addrspace(8)>, <2 x i32> } @undef_vec() {
; CHECK-NEXT: ret { <2 x ptr addrspace(8)>, <2 x i32> } undef
;
ret <2 x ptr addrspace(7)> undef
}
define ptr addrspace(7) @poison() {
-; CHECK-LABEL: define { ptr addrspace(8), i32 } @poison
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define { ptr addrspace(8), i32 } @poison() {
; CHECK-NEXT: ret { ptr addrspace(8), i32 } poison
;
ret ptr addrspace(7) poison
}
define <2 x ptr addrspace(7)> @poison_vec() {
-; CHECK-LABEL: define { <2 x ptr addrspace(8)>, <2 x i32> } @poison_vec
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define { <2 x ptr addrspace(8)>, <2 x i32> } @poison_vec() {
; CHECK-NEXT: ret { <2 x ptr addrspace(8)>, <2 x i32> } poison
;
ret <2 x ptr addrspace(7)> poison
}
define ptr addrspace(7) @cast_global() {
-; CHECK-LABEL: define { ptr addrspace(8), i32 } @cast_global
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define { ptr addrspace(8), i32 } @cast_global() {
; CHECK-NEXT: ret { ptr addrspace(8), i32 } { ptr addrspace(8) @buf, i32 0 }
;
ret ptr addrspace(7) addrspacecast (ptr addrspace(8) @buf to ptr addrspace(7))
}
define ptr addrspace(7) @cast_null() {
-; CHECK-LABEL: define { ptr addrspace(8), i32 } @cast_null
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define { ptr addrspace(8), i32 } @cast_null() {
; CHECK-NEXT: ret { ptr addrspace(8), i32 } zeroinitializer
;
ret ptr addrspace(7) addrspacecast (ptr addrspace(8) null to ptr addrspace(7))
}
define <2 x ptr addrspace(7)> @cast_vec() {
-; CHECK-LABEL: define { <2 x ptr addrspace(8)>, <2 x i32> } @cast_vec
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define { <2 x ptr addrspace(8)>, <2 x i32> } @cast_vec() {
; CHECK-NEXT: ret { <2 x ptr addrspace(8)>, <2 x i32> } { <2 x ptr addrspace(8)> <ptr addrspace(8) @buf, ptr addrspace(8) null>, <2 x i32> zeroinitializer }
;
ret <2 x ptr addrspace(7)> addrspacecast (
@@ -82,8 +73,7 @@ define <2 x ptr addrspace(7)> @cast_vec() {
}
define ptr addrspace(7) @gep() {
-; CHECK-LABEL: define { ptr addrspace(8), i32 } @gep
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define { ptr addrspace(8), i32 } @gep() {
; CHECK-NEXT: ret { ptr addrspace(8), i32 } { ptr addrspace(8) @buf, i32 36 }
;
ret ptr addrspace(7) getelementptr inbounds (
@@ -93,8 +83,7 @@ define ptr addrspace(7) @gep() {
}
define <2 x ptr addrspace(7)> @gep_vector() {
-; CHECK-LABEL: define { <2 x ptr addrspace(8)>, <2 x i32> } @gep_vector
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define { <2 x ptr addrspace(8)>, <2 x i32> } @gep_vector() {
; CHECK-NEXT: ret { <2 x ptr addrspace(8)>, <2 x i32> } { <2 x ptr addrspace(8)> <ptr addrspace(8) @buf, ptr addrspace(8) null>, <2 x i32> <i32 12, i32 4> }
;
ret <2 x ptr addrspace(7)> getelementptr (
@@ -106,32 +95,28 @@ define <2 x ptr addrspace(7)> @gep_vector() {
}
define ptr @gep_of_p7() {
-; CHECK-LABEL: define ptr @gep_of_p7
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define ptr @gep_of_p7() {
; CHECK-NEXT: ret ptr getelementptr inbounds (ptr addrspace(7), ptr @flat, i64 2)
;
ret ptr getelementptr inbounds (ptr addrspace(7), ptr @flat, i64 2)
}
define ptr @gep_of_p7_vector() {
-; CHECK-LABEL: define ptr @gep_of_p7_vector
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define ptr @gep_of_p7_vector() {
; CHECK-NEXT: ret ptr getelementptr (<2 x ptr addrspace(7)>, ptr @flat, i64 2)
;
ret ptr getelementptr (<2 x ptr addrspace(7)>, ptr @flat, i64 2)
}
define ptr @gep_of_p7_struct() {
-; CHECK-LABEL: define ptr @gep_of_p7_struct
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define ptr @gep_of_p7_struct() {
; CHECK-NEXT: ret ptr getelementptr ({ ptr addrspace(7), i32 }, ptr @flat, i64 2)
;
ret ptr getelementptr ({ptr addrspace(7), i32}, ptr @flat, i64 2)
}
define ptr addrspace(7) @gep_p7_from_p7() {
-; CHECK-LABEL: define { ptr addrspace(8), i32 } @gep_p7_from_p7
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define { ptr addrspace(8), i32 } @gep_p7_from_p7() {
; CHECK-NEXT: ret { ptr addrspace(8), i32 } { ptr addrspace(8) @buf, i32 48 }
;
ret ptr addrspace(7) getelementptr (ptr addrspace(7),
@@ -140,8 +125,7 @@ define ptr addrspace(7) @gep_p7_from_p7() {
}
define i160 @ptrtoint() {
-; CHECK-LABEL: define i160 @ptrtoint
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define i160 @ptrtoint() {
; CHECK-NEXT: [[TMP1:%.*]] = shl nuw i160 ptrtoint (ptr addrspace(8) @buf to i160), 32
; CHECK-NEXT: [[TMP2:%.*]] = or i160 [[TMP1]], 12
; CHECK-NEXT: ret i160 [[TMP2]]
@@ -153,8 +137,7 @@ define i160 @ptrtoint() {
}
define i256 @ptrtoint_long() {
-; CHECK-LABEL: define i256 @ptrtoint_long
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define i256 @ptrtoint_long() {
; CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i256 ptrtoint (ptr addrspace(8) @buf to i256), 32
; CHECK-NEXT: [[TMP2:%.*]] = or i256 [[TMP1]], 12
; CHECK-NEXT: ret i256 [[TMP2]]
@@ -166,8 +149,7 @@ define i256 @ptrtoint_long() {
}
define i64 @ptrtoint_short() {
-; CHECK-LABEL: define i64 @ptrtoint_short
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define i64 @ptrtoint_short() {
; CHECK-NEXT: [[TMP1:%.*]] = shl i64 ptrtoint (ptr addrspace(8) @buf to i64), 32
; CHECK-NEXT: [[TMP2:%.*]] = or i64 [[TMP1]], 12
; CHECK-NEXT: ret i64 [[TMP2]]
@@ -179,8 +161,7 @@ define i64 @ptrtoint_short() {
}
define i32 @ptrtoint_very_short() {
-; CHECK-LABEL: define i32 @ptrtoint_very_short
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define i32 @ptrtoint_very_short() {
; CHECK-NEXT: ret i32 12
;
ret i32 ptrtoint(
@@ -191,32 +172,28 @@ define i32 @ptrtoint_very_short() {
define <2 x i160> @ptrtoint_vec() {
-; CHECK-LABEL: define <2 x i160> @ptrtoint_vec
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define <2 x i160> @ptrtoint_vec() {
; CHECK-NEXT: ret <2 x i160> zeroinitializer
;
ret <2 x i160> ptrtoint (<2 x ptr addrspace(7)> zeroinitializer to <2 x i160>)
}
define ptr addrspace(7) @inttoptr() {
-; CHECK-LABEL: define { ptr addrspace(8), i32 } @inttoptr
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define { ptr addrspace(8), i32 } @inttoptr() {
; CHECK-NEXT: ret { ptr addrspace(8), i32 } zeroinitializer
;
ret ptr addrspace(7) inttoptr (i160 0 to ptr addrspace(7))
}
define <2 x ptr addrspace(7)> @inttoptr_vec() {
-; CHECK-LABEL: define { <2 x ptr addrspace(8)>, <2 x i32> } @inttoptr_vec
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define { <2 x ptr addrspace(8)>, <2 x i32> } @inttoptr_vec() {
; CHECK-NEXT: ret { <2 x ptr addrspace(8)>, <2 x i32> } { <2 x ptr addrspace(8)> splat (ptr addrspace(8) null), <2 x i32> <i32 1, i32 2> }
;
ret <2 x ptr addrspace(7)> inttoptr (<2 x i160> <i160 1, i160 2> to <2 x ptr addrspace(7)>)
}
define i32 @fancy_zero() {
-; CHECK-LABEL: define i32 @fancy_zero
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define i32 @fancy_zero() {
; CHECK-NEXT: ret i32 0
;
ret i32 ptrtoint (
@@ -225,8 +202,7 @@ define i32 @fancy_zero() {
}
define i32 @load_null() {
-; CHECK-LABEL: define i32 @load_null
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define i32 @load_null() {
; CHECK-NEXT: [[X:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 null, i32 0, i32 0, i32 0)
; CHECK-NEXT: ret i32 [[X]]
;
@@ -235,8 +211,7 @@ define i32 @load_null() {
}
define void @store_null() {
-; CHECK-LABEL: define void @store_null
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define void @store_null() {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 0, ptr addrspace(8) align 4 null, i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -245,8 +220,7 @@ define void @store_null() {
}
define i32 @load_poison() {
-; CHECK-LABEL: define i32 @load_poison
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define i32 @load_poison() {
; CHECK-NEXT: [[X:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 poison, i32 poison, i32 0, i32 0)
; CHECK-NEXT: ret i32 [[X]]
;
@@ -255,8 +229,7 @@ define i32 @load_poison() {
}
define void @store_poison() {
-; CHECK-LABEL: define void @store_poison
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define void @store_poison() {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 0, ptr addrspace(8) align 4 poison, i32 poison, i32 0, i32 0)
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-contents-legalization-alignment.ll b/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-contents-legalization-alignment.ll
index 9b99d6fa5bb1d..95d0ed9114731 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-contents-legalization-alignment.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-contents-legalization-alignment.ll
@@ -1,15 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
-; RUN: sed 's/BUFFER_OOB_MODE/2/' %s | opt -S -mcpu=gfx900 -passes=amdgpu-lower-buffer-fat-pointers | FileCheck %s --check-prefix=STRICT
+; RUN: sed 's/BUFFER_OOB_MODE/2/' %s | opt -S -passes=amdgpu-lower-buffer-fat-pointers | FileCheck %s --check-prefix=STRICT
;; Note: unaligned-access-mode is default on HSA targets
-; RUN: sed 's/BUFFER_OOB_MODE/2/' %s | opt -S -mcpu=gfx900 -passes=amdgpu-lower-buffer-fat-pointers -mattr=+unaligned-access-mode | FileCheck %s --check-prefix=UNALIGNED_ONLY
-; RUN: sed 's/BUFFER_OOB_MODE/1/' %s | opt -S -mcpu=gfx900 -passes=amdgpu-lower-buffer-fat-pointers | FileCheck %s --check-prefix=RELAXED_OOB_ONLY
-; RUN: sed 's/BUFFER_OOB_MODE/1/' %s | opt -S -mcpu=gfx900 -passes=amdgpu-lower-buffer-fat-pointers -mattr=+unaligned-access-mode | FileCheck %s --check-prefix=BOTH_FLAGS
+; RUN: sed 's/BUFFER_OOB_MODE/2/' %s | opt -S -passes=amdgpu-lower-buffer-fat-pointers -mattr=+unaligned-access-mode | FileCheck %s --check-prefix=UNALIGNED_ONLY
+; RUN: sed 's/BUFFER_OOB_MODE/1/' %s | opt -S -passes=amdgpu-lower-buffer-fat-pointers | FileCheck %s --check-prefix=RELAXED_OOB_ONLY
+; RUN: sed 's/BUFFER_OOB_MODE/1/' %s | opt -S -passes=amdgpu-lower-buffer-fat-pointers -mattr=+unaligned-access-mode | FileCheck %s --check-prefix=BOTH_FLAGS
-target triple = "amdgcn--"
+target triple = "amdgpu9.00--"
define i32 @load_i32_align4(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define i32 @load_i32_align4(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0:[0-9]+]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: ret i32 [[RET]]
;
@@ -19,7 +19,7 @@ define i32 @load_i32_align4(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret i32 [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define i32 @load_i32_align4(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0:[0-9]+]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret i32 [[RET]]
;
@@ -36,7 +36,7 @@ define i32 @load_i32_align4(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_i32_align4(i32 %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_i32_align4(
-; STRICT-SAME: i32 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: i32 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
@@ -46,7 +46,7 @@ define void @store_i32_align4(i32 %data, ptr addrspace(8) inreg %buf, i32 %off)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_i32_align4(
-; RELAXED_OOB_ONLY-SAME: i32 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: i32 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
@@ -64,7 +64,7 @@ define void @store_i32_align4(i32 %data, ptr addrspace(8) inreg %buf, i32 %off)
define i32 @load_i32_align2(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define i32 @load_i32_align2(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i16> poison, i16 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
@@ -79,7 +79,7 @@ define i32 @load_i32_align2(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret i32 [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define i32 @load_i32_align2(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i16> poison, i16 [[RET_OFF_0]], i64 0
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_2:%.*]] = add nuw i32 [[Q]], 2
@@ -101,7 +101,7 @@ define i32 @load_i32_align2(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_i32_align2(i32 %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_i32_align2(
-; STRICT-SAME: i32 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: i32 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[DATA_LEGAL:%.*]] = bitcast i32 [[DATA]] to <2 x i16>
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i16> [[DATA_LEGAL]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_0]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
@@ -116,7 +116,7 @@ define void @store_i32_align2(i32 %data, ptr addrspace(8) inreg %buf, i32 %off)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_i32_align2(
-; RELAXED_OOB_ONLY-SAME: i32 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: i32 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast i32 [[DATA]] to <2 x i16>
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i16> [[DATA_LEGAL]], i64 0
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_0]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
@@ -138,7 +138,7 @@ define void @store_i32_align2(i32 %data, ptr addrspace(8) inreg %buf, i32 %off)
define i32 @load_i32_align1(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define i32 @load_i32_align1(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <4 x i8> poison, i8 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
@@ -159,7 +159,7 @@ define i32 @load_i32_align1(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret i32 [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define i32 @load_i32_align1(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <4 x i8> poison, i8 [[RET_OFF_0]], i64 0
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_1:%.*]] = add nuw i32 [[Q]], 1
@@ -187,7 +187,7 @@ define i32 @load_i32_align1(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_i32_align1(i32 %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_i32_align1(
-; STRICT-SAME: i32 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: i32 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[DATA_LEGAL:%.*]] = bitcast i32 [[DATA]] to <4 x i8>
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <4 x i8> [[DATA_LEGAL]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
@@ -208,7 +208,7 @@ define void @store_i32_align1(i32 %data, ptr addrspace(8) inreg %buf, i32 %off)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_i32_align1(
-; RELAXED_OOB_ONLY-SAME: i32 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: i32 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast i32 [[DATA]] to <4 x i8>
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <4 x i8> [[DATA_LEGAL]], i64 0
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
@@ -236,7 +236,7 @@ define void @store_i32_align1(i32 %data, ptr addrspace(8) inreg %buf, i32 %off)
define i64 @load_i64_align4(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define i64 @load_i64_align4(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET:%.*]] = call i64 @llvm.amdgcn.raw.ptr.buffer.load.i64(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: ret i64 [[RET]]
;
@@ -246,7 +246,7 @@ define i64 @load_i64_align4(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret i64 [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define i64 @load_i64_align4(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = call i64 @llvm.amdgcn.raw.ptr.buffer.load.i64(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret i64 [[RET]]
;
@@ -263,7 +263,7 @@ define i64 @load_i64_align4(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_i64_align4(i64 %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_i64_align4(
-; STRICT-SAME: i64 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: i64 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i64(i64 [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
@@ -273,7 +273,7 @@ define void @store_i64_align4(i64 %data, ptr addrspace(8) inreg %buf, i32 %off)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_i64_align4(
-; RELAXED_OOB_ONLY-SAME: i64 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: i64 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i64(i64 [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
@@ -290,7 +290,7 @@ define void @store_i64_align4(i64 %data, ptr addrspace(8) inreg %buf, i32 %off)
define i64 @load_i64_align1(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define i64 @load_i64_align1(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <8 x i8> poison, i8 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
@@ -323,7 +323,7 @@ define i64 @load_i64_align1(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret i64 [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define i64 @load_i64_align1(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <8 x i8> poison, i8 [[RET_OFF_0]], i64 0
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_1:%.*]] = add nuw i32 [[Q]], 1
@@ -363,7 +363,7 @@ define i64 @load_i64_align1(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_i64_align1(i64 %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_i64_align1(
-; STRICT-SAME: i64 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: i64 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[DATA_LEGAL:%.*]] = bitcast i64 [[DATA]] to <8 x i8>
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
@@ -396,7 +396,7 @@ define void @store_i64_align1(i64 %data, ptr addrspace(8) inreg %buf, i32 %off)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_i64_align1(
-; RELAXED_OOB_ONLY-SAME: i64 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: i64 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast i64 [[DATA]] to <8 x i8>
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 0
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
@@ -436,7 +436,7 @@ define void @store_i64_align1(i64 %data, ptr addrspace(8) inreg %buf, i32 %off)
define <2 x i32> @load_v2i32_align4(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <2 x i32> @load_v2i32_align4(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i32> poison, i32 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_4:%.*]] = add i32 [[Q]], 4
@@ -454,7 +454,7 @@ define <2 x i32> @load_v2i32_align4(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret <2 x i32> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <2 x i32> @load_v2i32_align4(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret <2 x i32> [[RET]]
;
@@ -471,7 +471,7 @@ define <2 x i32> @load_v2i32_align4(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_v2i32_align4(<2 x i32> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v2i32_align4(
-; STRICT-SAME: <2 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: <2 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i32> [[DATA]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_0]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 4
@@ -489,7 +489,7 @@ define void @store_v2i32_align4(<2 x i32> %data, ptr addrspace(8) inreg %buf, i3
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v2i32_align4(
-; RELAXED_OOB_ONLY-SAME: <2 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: <2 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
@@ -506,7 +506,7 @@ define void @store_v2i32_align4(<2 x i32> %data, ptr addrspace(8) inreg %buf, i3
define <2 x i32> @load_v2i32_align2(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <2 x i32> @load_v2i32_align2(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <4 x i16> poison, i16 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
@@ -531,7 +531,7 @@ define <2 x i32> @load_v2i32_align2(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret <2 x i32> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <2 x i32> @load_v2i32_align2(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <4 x i16> poison, i16 [[RET_OFF_0]], i64 0
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_2:%.*]] = add nuw i32 [[Q]], 2
@@ -559,7 +559,7 @@ define <2 x i32> @load_v2i32_align2(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_v2i32_align2(<2 x i32> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v2i32_align2(
-; STRICT-SAME: <2 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: <2 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[DATA_LEGAL:%.*]] = bitcast <2 x i32> [[DATA]] to <4 x i16>
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <4 x i16> [[DATA_LEGAL]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_0]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
@@ -584,7 +584,7 @@ define void @store_v2i32_align2(<2 x i32> %data, ptr addrspace(8) inreg %buf, i3
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v2i32_align2(
-; RELAXED_OOB_ONLY-SAME: <2 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: <2 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast <2 x i32> [[DATA]] to <4 x i16>
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <4 x i16> [[DATA_LEGAL]], i64 0
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_0]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
@@ -612,7 +612,7 @@ define void @store_v2i32_align2(<2 x i32> %data, ptr addrspace(8) inreg %buf, i3
define <2 x i32> @load_v2i32_align1(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <2 x i32> @load_v2i32_align1(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <8 x i8> poison, i8 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
@@ -649,7 +649,7 @@ define <2 x i32> @load_v2i32_align1(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret <2 x i32> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <2 x i32> @load_v2i32_align1(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <8 x i8> poison, i8 [[RET_OFF_0]], i64 0
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_1:%.*]] = add nuw i32 [[Q]], 1
@@ -689,7 +689,7 @@ define <2 x i32> @load_v2i32_align1(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_v2i32_align1(<2 x i32> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v2i32_align1(
-; STRICT-SAME: <2 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: <2 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[DATA_LEGAL:%.*]] = bitcast <2 x i32> [[DATA]] to <8 x i8>
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
@@ -726,7 +726,7 @@ define void @store_v2i32_align1(<2 x i32> %data, ptr addrspace(8) inreg %buf, i3
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v2i32_align1(
-; RELAXED_OOB_ONLY-SAME: <2 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: <2 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast <2 x i32> [[DATA]] to <8 x i8>
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 0
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
@@ -766,7 +766,7 @@ define void @store_v2i32_align1(<2 x i32> %data, ptr addrspace(8) inreg %buf, i3
define <3 x i32> @load_v3i32_align4(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <3 x i32> @load_v3i32_align4(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <3 x i32> poison, i32 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_4:%.*]] = add i32 [[Q]], 4
@@ -790,7 +790,7 @@ define <3 x i32> @load_v3i32_align4(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret <3 x i32> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <3 x i32> @load_v3i32_align4(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = call <3 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v3i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret <3 x i32> [[RET]]
;
@@ -807,7 +807,7 @@ define <3 x i32> @load_v3i32_align4(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_v3i32_align4(<3 x i32> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v3i32_align4(
-; STRICT-SAME: <3 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: <3 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <3 x i32> [[DATA]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_0]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 4
@@ -831,7 +831,7 @@ define void @store_v3i32_align4(<3 x i32> %data, ptr addrspace(8) inreg %buf, i3
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v3i32_align4(
-; RELAXED_OOB_ONLY-SAME: <3 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: <3 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
@@ -848,7 +848,7 @@ define void @store_v3i32_align4(<3 x i32> %data, ptr addrspace(8) inreg %buf, i3
define <3 x i32> @load_v3i32_align8(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <3 x i32> @load_v3i32_align8(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_EXT_0:%.*]] = shufflevector <2 x i32> [[RET_OFF_0]], <2 x i32> poison, <3 x i32> <i32 0, i32 1, i32 poison>
; STRICT-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <3 x i32> poison, <3 x i32> [[RET_EXT_0]], <3 x i32> <i32 3, i32 4, i32 2>
@@ -868,7 +868,7 @@ define <3 x i32> @load_v3i32_align8(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret <3 x i32> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <3 x i32> @load_v3i32_align8(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = call <3 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v3i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret <3 x i32> [[RET]]
;
@@ -885,7 +885,7 @@ define <3 x i32> @load_v3i32_align8(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_v3i32_align8(<3 x i32> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v3i32_align8(
-; STRICT-SAME: <3 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: <3 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <3 x i32> [[DATA]], <3 x i32> poison, <2 x i32> <i32 0, i32 1>
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 8
@@ -903,7 +903,7 @@ define void @store_v3i32_align8(<3 x i32> %data, ptr addrspace(8) inreg %buf, i3
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v3i32_align8(
-; RELAXED_OOB_ONLY-SAME: <3 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: <3 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> [[DATA]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
@@ -920,7 +920,7 @@ define void @store_v3i32_align8(<3 x i32> %data, ptr addrspace(8) inreg %buf, i3
define <3 x i32> @load_v3i32_align16(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <3 x i32> @load_v3i32_align16(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET:%.*]] = call <3 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v3i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: ret <3 x i32> [[RET]]
;
@@ -930,7 +930,7 @@ define <3 x i32> @load_v3i32_align16(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret <3 x i32> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <3 x i32> @load_v3i32_align16(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = call <3 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v3i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret <3 x i32> [[RET]]
;
@@ -947,7 +947,7 @@ define <3 x i32> @load_v3i32_align16(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_v3i32_align16(<3 x i32> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v3i32_align16(
-; STRICT-SAME: <3 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: <3 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> [[DATA]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: ret void
;
@@ -957,7 +957,7 @@ define void @store_v3i32_align16(<3 x i32> %data, ptr addrspace(8) inreg %buf, i
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v3i32_align16(
-; RELAXED_OOB_ONLY-SAME: <3 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: <3 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> [[DATA]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
@@ -974,7 +974,7 @@ define void @store_v3i32_align16(<3 x i32> %data, ptr addrspace(8) inreg %buf, i
define <4 x i32> @load_v4i32_align8(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <4 x i32> @load_v4i32_align8(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_EXT_0:%.*]] = shufflevector <2 x i32> [[RET_OFF_0]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; STRICT-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <4 x i32> poison, <4 x i32> [[RET_EXT_0]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
@@ -996,7 +996,7 @@ define <4 x i32> @load_v4i32_align8(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret <4 x i32> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <4 x i32> @load_v4i32_align8(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret <4 x i32> [[RET]]
;
@@ -1013,7 +1013,7 @@ define <4 x i32> @load_v4i32_align8(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_v4i32_align8(<4 x i32> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v4i32_align8(
-; STRICT-SAME: <4 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: <4 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <4 x i32> [[DATA]], <4 x i32> poison, <2 x i32> <i32 0, i32 1>
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 8
@@ -1031,7 +1031,7 @@ define void @store_v4i32_align8(<4 x i32> %data, ptr addrspace(8) inreg %buf, i3
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v4i32_align8(
-; RELAXED_OOB_ONLY-SAME: <4 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: <4 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
@@ -1048,7 +1048,7 @@ define void @store_v4i32_align8(<4 x i32> %data, ptr addrspace(8) inreg %buf, i3
define <8 x i32> @load_v8i32_align16(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <8 x i32> @load_v8i32_align16(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i32> [[RET_OFF_0]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; STRICT-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <8 x i32> poison, <8 x i32> [[RET_EXT_0]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
@@ -1070,7 +1070,7 @@ define <8 x i32> @load_v8i32_align16(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret <8 x i32> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <8 x i32> @load_v8i32_align16(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i32> [[RET_OFF_0]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; RELAXED_OOB_ONLY-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <8 x i32> poison, <8 x i32> [[RET_EXT_0]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
@@ -1099,7 +1099,7 @@ define <8 x i32> @load_v8i32_align16(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_v8i32_align16(<8 x i32> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v8i32_align16(
-; STRICT-SAME: <8 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: <8 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_4:%.*]] = add i32 [[Q]], 16
@@ -1117,7 +1117,7 @@ define void @store_v8i32_align16(<8 x i32> %data, ptr addrspace(8) inreg %buf, i
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v8i32_align16(
-; RELAXED_OOB_ONLY-SAME: <8 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: <8 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_4:%.*]] = add nuw i32 [[Q]], 16
@@ -1142,7 +1142,7 @@ define void @store_v8i32_align16(<8 x i32> %data, ptr addrspace(8) inreg %buf, i
define <8 x i32> @load_v8i32_align8(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <8 x i32> @load_v8i32_align8(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_EXT_0:%.*]] = shufflevector <2 x i32> [[RET_OFF_0]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; STRICT-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <8 x i32> poison, <8 x i32> [[RET_EXT_0]], <8 x i32> <i32 8, i32 9, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
@@ -1180,7 +1180,7 @@ define <8 x i32> @load_v8i32_align8(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret <8 x i32> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <8 x i32> @load_v8i32_align8(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i32> [[RET_OFF_0]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; RELAXED_OOB_ONLY-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <8 x i32> poison, <8 x i32> [[RET_EXT_0]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
@@ -1209,7 +1209,7 @@ define <8 x i32> @load_v8i32_align8(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_v8i32_align8(<8 x i32> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v8i32_align8(
-; STRICT-SAME: <8 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: <8 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <2 x i32> <i32 0, i32 1>
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 8
@@ -1239,7 +1239,7 @@ define void @store_v8i32_align8(<8 x i32> %data, ptr addrspace(8) inreg %buf, i3
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v8i32_align8(
-; RELAXED_OOB_ONLY-SAME: <8 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: <8 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_4:%.*]] = add nuw i32 [[Q]], 16
@@ -1264,7 +1264,7 @@ define void @store_v8i32_align8(<8 x i32> %data, ptr addrspace(8) inreg %buf, i3
define <8 x i32> @load_v8i32_align4(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <8 x i32> @load_v8i32_align4(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <8 x i32> poison, i32 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_4:%.*]] = add i32 [[Q]], 4
@@ -1318,7 +1318,7 @@ define <8 x i32> @load_v8i32_align4(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret <8 x i32> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <8 x i32> @load_v8i32_align4(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i32> [[RET_OFF_0]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; RELAXED_OOB_ONLY-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <8 x i32> poison, <8 x i32> [[RET_EXT_0]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
@@ -1347,7 +1347,7 @@ define <8 x i32> @load_v8i32_align4(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_v8i32_align4(<8 x i32> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v8i32_align4(
-; STRICT-SAME: <8 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: <8 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <8 x i32> [[DATA]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_0]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 4
@@ -1401,7 +1401,7 @@ define void @store_v8i32_align4(<8 x i32> %data, ptr addrspace(8) inreg %buf, i3
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v8i32_align4(
-; RELAXED_OOB_ONLY-SAME: <8 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: <8 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <8 x i32> [[DATA]], <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_4:%.*]] = add nuw i32 [[Q]], 16
@@ -1426,7 +1426,7 @@ define void @store_v8i32_align4(<8 x i32> %data, ptr addrspace(8) inreg %buf, i3
define <10 x i32> @load_v10i32_align16(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <10 x i32> @load_v10i32_align16(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i32> [[RET_OFF_0]], <4 x i32> poison, <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; STRICT-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <10 x i32> poison, <10 x i32> [[RET_EXT_0]], <10 x i32> <i32 10, i32 11, i32 12, i32 13, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
@@ -1456,7 +1456,7 @@ define <10 x i32> @load_v10i32_align16(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret <10 x i32> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <10 x i32> @load_v10i32_align16(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i32> [[RET_OFF_0]], <4 x i32> poison, <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; RELAXED_OOB_ONLY-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <10 x i32> poison, <10 x i32> [[RET_EXT_0]], <10 x i32> <i32 10, i32 11, i32 12, i32 13, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
@@ -1493,7 +1493,7 @@ define <10 x i32> @load_v10i32_align16(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_v10i32_align16(<10 x i32> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v10i32_align16(
-; STRICT-SAME: <10 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: <10 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_4:%.*]] = add i32 [[Q]], 16
@@ -1517,7 +1517,7 @@ define void @store_v10i32_align16(<10 x i32> %data, ptr addrspace(8) inreg %buf,
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v10i32_align16(
-; RELAXED_OOB_ONLY-SAME: <10 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: <10 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 16 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_4:%.*]] = add nuw i32 [[Q]], 16
@@ -1548,7 +1548,7 @@ define void @store_v10i32_align16(<10 x i32> %data, ptr addrspace(8) inreg %buf,
define <10 x i32> @load_v10i32_align8(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <10 x i32> @load_v10i32_align8(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_EXT_0:%.*]] = shufflevector <2 x i32> [[RET_OFF_0]], <2 x i32> poison, <10 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; STRICT-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <10 x i32> poison, <10 x i32> [[RET_EXT_0]], <10 x i32> <i32 10, i32 11, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
@@ -1594,7 +1594,7 @@ define <10 x i32> @load_v10i32_align8(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret <10 x i32> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <10 x i32> @load_v10i32_align8(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i32> [[RET_OFF_0]], <4 x i32> poison, <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; RELAXED_OOB_ONLY-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <10 x i32> poison, <10 x i32> [[RET_EXT_0]], <10 x i32> <i32 10, i32 11, i32 12, i32 13, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
@@ -1631,7 +1631,7 @@ define <10 x i32> @load_v10i32_align8(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_v10i32_align8(<10 x i32> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v10i32_align8(
-; STRICT-SAME: <10 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: <10 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <2 x i32> <i32 0, i32 1>
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_2:%.*]] = add i32 [[Q]], 8
@@ -1667,7 +1667,7 @@ define void @store_v10i32_align8(<10 x i32> %data, ptr addrspace(8) inreg %buf,
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v10i32_align8(
-; RELAXED_OOB_ONLY-SAME: <10 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: <10 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <10 x i32> [[DATA]], <10 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_4:%.*]] = add nuw i32 [[Q]], 16
@@ -1698,7 +1698,7 @@ define void @store_v10i32_align8(<10 x i32> %data, ptr addrspace(8) inreg %buf,
define i16 @load_i16_align1(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define i16 @load_i16_align1(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i8> poison, i8 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
@@ -1713,7 +1713,7 @@ define i16 @load_i16_align1(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret i16 [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define i16 @load_i16_align1(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i8> poison, i8 [[RET_OFF_0]], i64 0
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_1:%.*]] = add nuw i32 [[Q]], 1
@@ -1735,7 +1735,7 @@ define i16 @load_i16_align1(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_i16_align1(i16 %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_i16_align1(
-; STRICT-SAME: i16 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: i16 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[DATA_LEGAL:%.*]] = bitcast i16 [[DATA]] to <2 x i8>
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i8> [[DATA_LEGAL]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
@@ -1750,7 +1750,7 @@ define void @store_i16_align1(i16 %data, ptr addrspace(8) inreg %buf, i32 %off)
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_i16_align1(
-; RELAXED_OOB_ONLY-SAME: i16 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: i16 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast i16 [[DATA]] to <2 x i8>
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i8> [[DATA_LEGAL]], i64 0
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
@@ -1772,7 +1772,7 @@ define void @store_i16_align1(i16 %data, ptr addrspace(8) inreg %buf, i32 %off)
define <2 x i16> @load_v2i16_align4(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <2 x i16> @load_v2i16_align4(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i16> poison, i16 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
@@ -1790,7 +1790,7 @@ define <2 x i16> @load_v2i16_align4(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret <2 x i16> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <2 x i16> @load_v2i16_align4(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = call <2 x i16> @llvm.amdgcn.raw.ptr.buffer.load.v2i16(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret <2 x i16> [[RET]]
;
@@ -1807,7 +1807,7 @@ define <2 x i16> @load_v2i16_align4(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_v2i16_align4(<2 x i16> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v2i16_align4(
-; STRICT-SAME: <2 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: <2 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i16> [[DATA]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_0]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 2
@@ -1825,7 +1825,7 @@ define void @store_v2i16_align4(<2 x i16> %data, ptr addrspace(8) inreg %buf, i3
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v2i16_align4(
-; RELAXED_OOB_ONLY-SAME: <2 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: <2 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i16(<2 x i16> [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
;
@@ -1842,7 +1842,7 @@ define void @store_v2i16_align4(<2 x i16> %data, ptr addrspace(8) inreg %buf, i3
define <2 x i16> @load_v2i16_align2(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <2 x i16> @load_v2i16_align2(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i16> poison, i16 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_2:%.*]] = add i32 [[Q]], 2
@@ -1860,7 +1860,7 @@ define <2 x i16> @load_v2i16_align2(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret <2 x i16> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <2 x i16> @load_v2i16_align2(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i16> poison, i16 [[RET_OFF_0]], i64 0
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_2:%.*]] = add nuw i32 [[Q]], 2
@@ -1881,7 +1881,7 @@ define <2 x i16> @load_v2i16_align2(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_v2i16_align2(<2 x i16> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v2i16_align2(
-; STRICT-SAME: <2 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: <2 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i16> [[DATA]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_0]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 2
@@ -1899,7 +1899,7 @@ define void @store_v2i16_align2(<2 x i16> %data, ptr addrspace(8) inreg %buf, i3
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v2i16_align2(
-; RELAXED_OOB_ONLY-SAME: <2 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: <2 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i16> [[DATA]], i64 0
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_0]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_1:%.*]] = add nuw i32 [[Q]], 2
@@ -1920,7 +1920,7 @@ define void @store_v2i16_align2(<2 x i16> %data, ptr addrspace(8) inreg %buf, i3
define <2 x i16> @load_v2i16_align1(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <2 x i16> @load_v2i16_align1(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <4 x i8> poison, i8 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
@@ -1945,7 +1945,7 @@ define <2 x i16> @load_v2i16_align1(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret <2 x i16> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <2 x i16> @load_v2i16_align1(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <4 x i8> poison, i8 [[RET_OFF_0]], i64 0
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_1:%.*]] = add nuw i32 [[Q]], 1
@@ -1973,7 +1973,7 @@ define <2 x i16> @load_v2i16_align1(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_v2i16_align1(<2 x i16> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v2i16_align1(
-; STRICT-SAME: <2 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: <2 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[DATA_LEGAL:%.*]] = bitcast <2 x i16> [[DATA]] to <4 x i8>
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <4 x i8> [[DATA_LEGAL]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
@@ -1998,7 +1998,7 @@ define void @store_v2i16_align1(<2 x i16> %data, ptr addrspace(8) inreg %buf, i3
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v2i16_align1(
-; RELAXED_OOB_ONLY-SAME: <2 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: <2 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast <2 x i16> [[DATA]] to <4 x i8>
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <4 x i8> [[DATA_LEGAL]], i64 0
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
@@ -2026,7 +2026,7 @@ define void @store_v2i16_align1(<2 x i16> %data, ptr addrspace(8) inreg %buf, i3
define <2 x i8> @load_v2i8_align2(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <2 x i8> @load_v2i8_align2(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i8> poison, i8 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
@@ -2044,7 +2044,7 @@ define <2 x i8> @load_v2i8_align2(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret <2 x i8> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <2 x i8> @load_v2i8_align2(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET_LOADABLE:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = bitcast i16 [[RET_LOADABLE]] to <2 x i8>
; RELAXED_OOB_ONLY-NEXT: ret <2 x i8> [[RET]]
@@ -2063,7 +2063,7 @@ define <2 x i8> @load_v2i8_align2(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_v2i8_align2(<2 x i8> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v2i8_align2(
-; STRICT-SAME: <2 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: <2 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i8> [[DATA]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 1
@@ -2081,7 +2081,7 @@ define void @store_v2i8_align2(<2 x i8> %data, ptr addrspace(8) inreg %buf, i32
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v2i8_align2(
-; RELAXED_OOB_ONLY-SAME: <2 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: <2 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast <2 x i8> [[DATA]] to i16
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_LEGAL]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
@@ -2100,7 +2100,7 @@ define void @store_v2i8_align2(<2 x i8> %data, ptr addrspace(8) inreg %buf, i32
define <2 x i8> @load_v2i8_align1(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <2 x i8> @load_v2i8_align1(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i8> poison, i8 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
@@ -2118,7 +2118,7 @@ define <2 x i8> @load_v2i8_align1(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret <2 x i8> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <2 x i8> @load_v2i8_align1(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i8> poison, i8 [[RET_OFF_0]], i64 0
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_1:%.*]] = add nuw i32 [[Q]], 1
@@ -2140,7 +2140,7 @@ define <2 x i8> @load_v2i8_align1(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_v2i8_align1(<2 x i8> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v2i8_align1(
-; STRICT-SAME: <2 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: <2 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i8> [[DATA]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 1
@@ -2158,7 +2158,7 @@ define void @store_v2i8_align1(<2 x i8> %data, ptr addrspace(8) inreg %buf, i32
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v2i8_align1(
-; RELAXED_OOB_ONLY-SAME: <2 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: <2 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i8> [[DATA]], i64 0
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_1:%.*]] = add nuw i32 [[Q]], 1
@@ -2180,7 +2180,7 @@ define void @store_v2i8_align1(<2 x i8> %data, ptr addrspace(8) inreg %buf, i32
define <4 x i8> @load_v4i8_align4(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <4 x i8> @load_v4i8_align4(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <4 x i8> poison, i8 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
@@ -2210,7 +2210,7 @@ define <4 x i8> @load_v4i8_align4(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret <4 x i8> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <4 x i8> @load_v4i8_align4(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET_LOADABLE:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = bitcast i32 [[RET_LOADABLE]] to <4 x i8>
; RELAXED_OOB_ONLY-NEXT: ret <4 x i8> [[RET]]
@@ -2229,7 +2229,7 @@ define <4 x i8> @load_v4i8_align4(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_v4i8_align4(<4 x i8> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v4i8_align4(
-; STRICT-SAME: <4 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: <4 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <4 x i8> [[DATA]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 1
@@ -2259,7 +2259,7 @@ define void @store_v4i8_align4(<4 x i8> %data, ptr addrspace(8) inreg %buf, i32
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v4i8_align4(
-; RELAXED_OOB_ONLY-SAME: <4 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: <4 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast <4 x i8> [[DATA]] to i32
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_LEGAL]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
@@ -2278,7 +2278,7 @@ define void @store_v4i8_align4(<4 x i8> %data, ptr addrspace(8) inreg %buf, i32
define <4 x i8> @load_v4i8_align2(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <4 x i8> @load_v4i8_align2(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <4 x i8> poison, i8 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
@@ -2308,7 +2308,7 @@ define <4 x i8> @load_v4i8_align2(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret <4 x i8> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <4 x i8> @load_v4i8_align2(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x i16> poison, i16 [[RET_OFF_0]], i64 0
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_2:%.*]] = add nuw i32 [[Q]], 2
@@ -2331,7 +2331,7 @@ define <4 x i8> @load_v4i8_align2(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_v4i8_align2(<4 x i8> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v4i8_align2(
-; STRICT-SAME: <4 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: <4 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <4 x i8> [[DATA]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 1
@@ -2361,7 +2361,7 @@ define void @store_v4i8_align2(<4 x i8> %data, ptr addrspace(8) inreg %buf, i32
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v4i8_align2(
-; RELAXED_OOB_ONLY-SAME: <4 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: <4 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast <4 x i8> [[DATA]] to <2 x i16>
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x i16> [[DATA_LEGAL]], i64 0
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_0]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
@@ -2384,7 +2384,7 @@ define void @store_v4i8_align2(<4 x i8> %data, ptr addrspace(8) inreg %buf, i32
define <4 x i8> @load_v4i8_align1(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <4 x i8> @load_v4i8_align1(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <4 x i8> poison, i8 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
@@ -2414,7 +2414,7 @@ define <4 x i8> @load_v4i8_align1(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret <4 x i8> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <4 x i8> @load_v4i8_align1(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <4 x i8> poison, i8 [[RET_OFF_0]], i64 0
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_1:%.*]] = add nuw i32 [[Q]], 1
@@ -2442,7 +2442,7 @@ define <4 x i8> @load_v4i8_align1(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_v4i8_align1(<4 x i8> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v4i8_align1(
-; STRICT-SAME: <4 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: <4 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <4 x i8> [[DATA]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[Q_PART_1:%.*]] = add i32 [[Q]], 1
@@ -2472,7 +2472,7 @@ define void @store_v4i8_align1(<4 x i8> %data, ptr addrspace(8) inreg %buf, i32
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v4i8_align1(
-; RELAXED_OOB_ONLY-SAME: <4 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: <4 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <4 x i8> [[DATA]], i64 0
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[Q_PART_1:%.*]] = add nuw i32 [[Q]], 1
@@ -2500,7 +2500,7 @@ define void @store_v4i8_align1(<4 x i8> %data, ptr addrspace(8) inreg %buf, i32
define <16 x i4> @load_v16i4_align8(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <16 x i4> @load_v16i4_align8(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <8 x i8> poison, i8 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
@@ -2556,7 +2556,7 @@ define <16 x i4> @load_v16i4_align8(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret <16 x i4> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <16 x i4> @load_v16i4_align8(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET_LOADABLE:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = bitcast <2 x i32> [[RET_LOADABLE]] to <16 x i4>
; RELAXED_OOB_ONLY-NEXT: ret <16 x i4> [[RET]]
@@ -2575,7 +2575,7 @@ define <16 x i4> @load_v16i4_align8(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_v16i4_align8(<16 x i4> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v16i4_align8(
-; STRICT-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[DATA_LEGAL:%.*]] = bitcast <16 x i4> [[DATA]] to <8 x i8>
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
@@ -2631,7 +2631,7 @@ define void @store_v16i4_align8(<16 x i4> %data, ptr addrspace(8) inreg %buf, i3
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v16i4_align8(
-; RELAXED_OOB_ONLY-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast <16 x i4> [[DATA]] to <2 x i32>
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_LEGAL]], ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
@@ -2650,7 +2650,7 @@ define void @store_v16i4_align8(<16 x i4> %data, ptr addrspace(8) inreg %buf, i3
define <16 x i4> @load_v16i4_align4(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <16 x i4> @load_v16i4_align4(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <8 x i8> poison, i8 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
@@ -2706,7 +2706,7 @@ define <16 x i4> @load_v16i4_align4(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret <16 x i4> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <16 x i4> @load_v16i4_align4(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET_LOADABLE:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = bitcast <2 x i32> [[RET_LOADABLE]] to <16 x i4>
; RELAXED_OOB_ONLY-NEXT: ret <16 x i4> [[RET]]
@@ -2725,7 +2725,7 @@ define <16 x i4> @load_v16i4_align4(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_v16i4_align4(<16 x i4> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v16i4_align4(
-; STRICT-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[DATA_LEGAL:%.*]] = bitcast <16 x i4> [[DATA]] to <8 x i8>
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
@@ -2781,7 +2781,7 @@ define void @store_v16i4_align4(<16 x i4> %data, ptr addrspace(8) inreg %buf, i3
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v16i4_align4(
-; RELAXED_OOB_ONLY-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast <16 x i4> [[DATA]] to <2 x i32>
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_LEGAL]], ptr addrspace(8) align 4 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret void
@@ -2800,7 +2800,7 @@ define void @store_v16i4_align4(<16 x i4> %data, ptr addrspace(8) inreg %buf, i3
define <16 x i4> @load_v16i4_align2(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <16 x i4> @load_v16i4_align2(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <8 x i8> poison, i8 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
@@ -2856,7 +2856,7 @@ define <16 x i4> @load_v16i4_align2(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret <16 x i4> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <16 x i4> @load_v16i4_align2(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <4 x i16> poison, i16 [[RET_OFF_0]], i64 0
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_2:%.*]] = add nuw i32 [[Q]], 2
@@ -2885,7 +2885,7 @@ define <16 x i4> @load_v16i4_align2(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_v16i4_align2(<16 x i4> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v16i4_align2(
-; STRICT-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[DATA_LEGAL:%.*]] = bitcast <16 x i4> [[DATA]] to <8 x i8>
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
@@ -2941,7 +2941,7 @@ define void @store_v16i4_align2(<16 x i4> %data, ptr addrspace(8) inreg %buf, i3
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v16i4_align2(
-; RELAXED_OOB_ONLY-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast <16 x i4> [[DATA]] to <4 x i16>
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <4 x i16> [[DATA_LEGAL]], i64 0
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_0]], ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
@@ -2970,7 +2970,7 @@ define void @store_v16i4_align2(<16 x i4> %data, ptr addrspace(8) inreg %buf, i3
define <16 x i4> @load_v16i4_align1(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <16 x i4> @load_v16i4_align1(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: [[RET_SLICE_0:%.*]] = insertelement <8 x i8> poison, i8 [[RET_OFF_0]], i64 0
; STRICT-NEXT: [[Q_OFF_PTR_1:%.*]] = add i32 [[Q]], 1
@@ -3026,7 +3026,7 @@ define <16 x i4> @load_v16i4_align1(ptr addrspace(8) inreg %buf, i32 %off) {
; UNALIGNED_ONLY-NEXT: ret <16 x i4> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <16 x i4> @load_v16i4_align1(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: [[RET_SLICE_0:%.*]] = insertelement <8 x i8> poison, i8 [[RET_OFF_0]], i64 0
; RELAXED_OOB_ONLY-NEXT: [[Q_OFF_PTR_1:%.*]] = add nuw i32 [[Q]], 1
@@ -3067,7 +3067,7 @@ define <16 x i4> @load_v16i4_align1(ptr addrspace(8) inreg %buf, i32 %off) {
define void @store_v16i4_align1(<16 x i4> %data, ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define void @store_v16i4_align1(
-; STRICT-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; STRICT-NEXT: [[DATA_LEGAL:%.*]] = bitcast <16 x i4> [[DATA]] to <8 x i8>
; STRICT-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 0
; STRICT-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
@@ -3123,7 +3123,7 @@ define void @store_v16i4_align1(<16 x i4> %data, ptr addrspace(8) inreg %buf, i3
; UNALIGNED_ONLY-NEXT: ret void
;
; RELAXED_OOB_ONLY-LABEL: define void @store_v16i4_align1(
-; RELAXED_OOB_ONLY-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: <16 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]], i32 [[Q:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[DATA_LEGAL:%.*]] = bitcast <16 x i4> [[DATA]] to <8 x i8>
; RELAXED_OOB_ONLY-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <8 x i8> [[DATA_LEGAL]], i64 0
; RELAXED_OOB_ONLY-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 [[Q]], i32 0, i32 0)
@@ -3164,7 +3164,7 @@ define void @store_v16i4_align1(<16 x i4> %data, ptr addrspace(8) inreg %buf, i3
define <4 x i32> @load_v4i32_align8_nneg(ptr addrspace(8) inreg %buf, i32 %off) {
; STRICT-LABEL: define <4 x i32> @load_v4i32_align8_nneg(
-; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[OFF:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[OFF:%.*]]) {
; STRICT-NEXT: [[Q:%.*]] = call i32 @llvm.umin.i32(i32 [[OFF]], i32 2147483640)
; STRICT-NEXT: [[RET:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; STRICT-NEXT: ret <4 x i32> [[RET]]
@@ -3176,7 +3176,7 @@ define <4 x i32> @load_v4i32_align8_nneg(ptr addrspace(8) inreg %buf, i32 %off)
; UNALIGNED_ONLY-NEXT: ret <4 x i32> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <4 x i32> @load_v4i32_align8_nneg(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[OFF:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(8) inreg [[BUF:%.*]], i32 [[OFF:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[Q:%.*]] = call i32 @llvm.umin.i32(i32 [[OFF]], i32 2147483640)
; RELAXED_OOB_ONLY-NEXT: [[RET:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 8 [[BUF]], i32 [[Q]], i32 0, i32 0)
; RELAXED_OOB_ONLY-NEXT: ret <4 x i32> [[RET]]
@@ -3196,7 +3196,7 @@ define <4 x i32> @load_v4i32_align8_nneg(ptr addrspace(8) inreg %buf, i32 %off)
define <8 x half> @load_v8f16_align2_not_oob(ptr addrspace(1) inreg %ptr, i32 %off) {
; STRICT-LABEL: define <8 x half> @load_v8f16_align2_not_oob(
-; STRICT-SAME: ptr addrspace(1) inreg [[PTR:%.*]], i32 [[OFF:%.*]]) #[[ATTR0]] {
+; STRICT-SAME: ptr addrspace(1) inreg [[PTR:%.*]], i32 [[OFF:%.*]]) {
; STRICT-NEXT: [[BUF:%.*]] = call ptr addrspace(8) @llvm.amdgcn.make.buffer.rsrc.p8.p1(ptr addrspace(1) [[PTR]], i16 0, i64 8192, i32 159744)
; STRICT-NEXT: [[Q:%.*]] = call i32 @llvm.umin.i32(i32 [[OFF]], i32 1024)
; STRICT-NEXT: [[RET_OFF_0:%.*]] = call half @llvm.amdgcn.raw.ptr.buffer.load.f16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
@@ -3232,7 +3232,7 @@ define <8 x half> @load_v8f16_align2_not_oob(ptr addrspace(1) inreg %ptr, i32 %o
; UNALIGNED_ONLY-NEXT: ret <8 x half> [[RET]]
;
; RELAXED_OOB_ONLY-LABEL: define <8 x half> @load_v8f16_align2_not_oob(
-; RELAXED_OOB_ONLY-SAME: ptr addrspace(1) inreg [[PTR:%.*]], i32 [[OFF:%.*]]) #[[ATTR0]] {
+; RELAXED_OOB_ONLY-SAME: ptr addrspace(1) inreg [[PTR:%.*]], i32 [[OFF:%.*]]) {
; RELAXED_OOB_ONLY-NEXT: [[BUF:%.*]] = call ptr addrspace(8) @llvm.amdgcn.make.buffer.rsrc.p8.p1(ptr addrspace(1) [[PTR]], i16 0, i64 8192, i32 159744)
; RELAXED_OOB_ONLY-NEXT: [[Q:%.*]] = call i32 @llvm.umin.i32(i32 [[OFF]], i32 1024)
; RELAXED_OOB_ONLY-NEXT: [[RET_OFF_0:%.*]] = call half @llvm.amdgcn.raw.ptr.buffer.load.f16(ptr addrspace(8) align 2 [[BUF]], i32 [[Q]], i32 0, i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-contents-legalization.ll b/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-contents-legalization.ll
index 0f1bda254e206..5efed9e569f2f 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-contents-legalization.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-contents-legalization.ll
@@ -1,17 +1,17 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
-; RUN: opt -S -mcpu=gfx900 -passes=amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
+; RUN: opt -S -passes=amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
; Note: if you're adding tests here, also add them to
; buffer-fat-pointers-contents-legalization.ll to make sure the output of this
; transformation can codegen.
-target triple = "amdgcn--"
+target triple = "amdgpu9.00--"
;;; Legal types. These are natively supported, no casts should be performed.
define i8 @load_i8(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define i8 @load_i8(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret i8 [[RET]]
;
@@ -22,7 +22,7 @@ define i8 @load_i8(ptr addrspace(8) inreg %buf) {
define void @store_i8(i8 %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_i8(
-; CHECK-SAME: i8 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: i8 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA]], ptr addrspace(8) align 1 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -33,7 +33,7 @@ define void @store_i8(i8 %data, ptr addrspace(8) inreg %buf) {
define i16 @load_i16(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define i16 @load_i16(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret i16 [[RET]]
;
@@ -44,7 +44,7 @@ define i16 @load_i16(ptr addrspace(8) inreg %buf) {
define void @store_i16(i16 %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_i16(
-; CHECK-SAME: i16 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: i16 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA]], ptr addrspace(8) align 2 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -55,7 +55,7 @@ define void @store_i16(i16 %data, ptr addrspace(8) inreg %buf) {
define i32 @load_i32(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define i32 @load_i32(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret i32 [[RET]]
;
@@ -66,7 +66,7 @@ define i32 @load_i32(ptr addrspace(8) inreg %buf) {
define void @store_i32(i32 %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_i32(
-; CHECK-SAME: i32 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: i32 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -77,7 +77,7 @@ define void @store_i32(i32 %data, ptr addrspace(8) inreg %buf) {
define i64 @load_i64(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define i64 @load_i64(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call i64 @llvm.amdgcn.raw.ptr.buffer.load.i64(ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret i64 [[RET]]
;
@@ -88,7 +88,7 @@ define i64 @load_i64(ptr addrspace(8) inreg %buf) {
define void @store_i64(i64 %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_i64(
-; CHECK-SAME: i64 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: i64 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i64(i64 [[DATA]], ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -99,7 +99,7 @@ define void @store_i64(i64 %data, ptr addrspace(8) inreg %buf) {
define i128 @load_i128(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define i128 @load_i128(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call i128 @llvm.amdgcn.raw.ptr.buffer.load.i128(ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret i128 [[RET]]
;
@@ -110,7 +110,7 @@ define i128 @load_i128(ptr addrspace(8) inreg %buf) {
define void @store_i128(i128 %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_i128(
-; CHECK-SAME: i128 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: i128 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i128(i128 [[DATA]], ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -121,7 +121,7 @@ define void @store_i128(i128 %data, ptr addrspace(8) inreg %buf) {
define <1 x i32> @load_v1i32(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <1 x i32> @load_v1i32(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_LOADABLE:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET:%.*]] = bitcast i32 [[RET_LOADABLE]] to <1 x i32>
; CHECK-NEXT: ret <1 x i32> [[RET]]
@@ -133,7 +133,7 @@ define <1 x i32> @load_v1i32(ptr addrspace(8) inreg %buf) {
define void @store_v1i32(<1 x i32> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v1i32(
-; CHECK-SAME: <1 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <1 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_STORABLE:%.*]] = bitcast <1 x i32> [[DATA]] to i32
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_STORABLE]], ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
@@ -145,7 +145,7 @@ define void @store_v1i32(<1 x i32> %data, ptr addrspace(8) inreg %buf) {
define <2 x i32> @load_v2i32(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <2 x i32> @load_v2i32(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret <2 x i32> [[RET]]
;
@@ -156,7 +156,7 @@ define <2 x i32> @load_v2i32(ptr addrspace(8) inreg %buf) {
define void @store_v2i32(<2 x i32> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v2i32(
-; CHECK-SAME: <2 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <2 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA]], ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -167,7 +167,7 @@ define void @store_v2i32(<2 x i32> %data, ptr addrspace(8) inreg %buf) {
define <3 x i32> @load_v3i32(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <3 x i32> @load_v3i32(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call <3 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v3i32(ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret <3 x i32> [[RET]]
;
@@ -178,7 +178,7 @@ define <3 x i32> @load_v3i32(ptr addrspace(8) inreg %buf) {
define void @store_v3i32(<3 x i32> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v3i32(
-; CHECK-SAME: <3 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <3 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> [[DATA]], ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -189,7 +189,7 @@ define void @store_v3i32(<3 x i32> %data, ptr addrspace(8) inreg %buf) {
define <4 x i32> @load_v4i32(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <4 x i32> @load_v4i32(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret <4 x i32> [[RET]]
;
@@ -200,7 +200,7 @@ define <4 x i32> @load_v4i32(ptr addrspace(8) inreg %buf) {
define void @store_v4i32(<4 x i32> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v4i32(
-; CHECK-SAME: <4 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <4 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA]], ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -211,7 +211,7 @@ define void @store_v4i32(<4 x i32> %data, ptr addrspace(8) inreg %buf) {
define <2 x i16> @load_v2i16(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <2 x i16> @load_v2i16(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call <2 x i16> @llvm.amdgcn.raw.ptr.buffer.load.v2i16(ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret <2 x i16> [[RET]]
;
@@ -222,7 +222,7 @@ define <2 x i16> @load_v2i16(ptr addrspace(8) inreg %buf) {
define void @store_v2i16(<2 x i16> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v2i16(
-; CHECK-SAME: <2 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <2 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i16(<2 x i16> [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -233,7 +233,7 @@ define void @store_v2i16(<2 x i16> %data, ptr addrspace(8) inreg %buf) {
define <4 x i16> @load_v4i16(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <4 x i16> @load_v4i16(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call <4 x i16> @llvm.amdgcn.raw.ptr.buffer.load.v4i16(ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret <4 x i16> [[RET]]
;
@@ -244,7 +244,7 @@ define <4 x i16> @load_v4i16(ptr addrspace(8) inreg %buf) {
define void @store_v4i16(<4 x i16> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v4i16(
-; CHECK-SAME: <4 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <4 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i16(<4 x i16> [[DATA]], ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -255,7 +255,7 @@ define void @store_v4i16(<4 x i16> %data, ptr addrspace(8) inreg %buf) {
define <8 x i16> @load_v8i16(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <8 x i16> @load_v8i16(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call <8 x i16> @llvm.amdgcn.raw.ptr.buffer.load.v8i16(ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret <8 x i16> [[RET]]
;
@@ -266,7 +266,7 @@ define <8 x i16> @load_v8i16(ptr addrspace(8) inreg %buf) {
define void @store_v8i16(<8 x i16> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v8i16(
-; CHECK-SAME: <8 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <8 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v8i16(<8 x i16> [[DATA]], ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -277,7 +277,7 @@ define void @store_v8i16(<8 x i16> %data, ptr addrspace(8) inreg %buf) {
define <2 x i64> @load_v2i64(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <2 x i64> @load_v2i64(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call <2 x i64> @llvm.amdgcn.raw.ptr.buffer.load.v2i64(ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret <2 x i64> [[RET]]
;
@@ -288,7 +288,7 @@ define <2 x i64> @load_v2i64(ptr addrspace(8) inreg %buf) {
define void @store_v2i64(<2 x i64> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v2i64(
-; CHECK-SAME: <2 x i64> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <2 x i64> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i64(<2 x i64> [[DATA]], ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -299,7 +299,7 @@ define void @store_v2i64(<2 x i64> %data, ptr addrspace(8) inreg %buf) {
define half @load_f16(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define half @load_f16(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call half @llvm.amdgcn.raw.ptr.buffer.load.f16(ptr addrspace(8) align 2 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret half [[RET]]
;
@@ -310,7 +310,7 @@ define half @load_f16(ptr addrspace(8) inreg %buf) {
define void @store_f16(half %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_f16(
-; CHECK-SAME: half [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: half [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.f16(half [[DATA]], ptr addrspace(8) align 2 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -321,7 +321,7 @@ define void @store_f16(half %data, ptr addrspace(8) inreg %buf) {
define bfloat @load_bf16(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define bfloat @load_bf16(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call bfloat @llvm.amdgcn.raw.ptr.buffer.load.bf16(ptr addrspace(8) align 2 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret bfloat [[RET]]
;
@@ -332,7 +332,7 @@ define bfloat @load_bf16(ptr addrspace(8) inreg %buf) {
define void @store_bf16(bfloat %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_bf16(
-; CHECK-SAME: bfloat [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: bfloat [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.bf16(bfloat [[DATA]], ptr addrspace(8) align 2 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -343,7 +343,7 @@ define void @store_bf16(bfloat %data, ptr addrspace(8) inreg %buf) {
define <2 x half> @load_v2f16(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <2 x half> @load_v2f16(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call <2 x half> @llvm.amdgcn.raw.ptr.buffer.load.v2f16(ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret <2 x half> [[RET]]
;
@@ -354,7 +354,7 @@ define <2 x half> @load_v2f16(ptr addrspace(8) inreg %buf) {
define void @store_v2f16(<2 x half> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v2f16(
-; CHECK-SAME: <2 x half> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <2 x half> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2f16(<2 x half> [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -365,7 +365,7 @@ define void @store_v2f16(<2 x half> %data, ptr addrspace(8) inreg %buf) {
define <2 x half> @load_v2f16_align2(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <2 x half> @load_v2f16_align2(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_OFF_0:%.*]] = call half @llvm.amdgcn.raw.ptr.buffer.load.f16(ptr addrspace(8) align 2 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x half> poison, half [[RET_OFF_0]], i64 0
; CHECK-NEXT: [[RET_OFF_2:%.*]] = call half @llvm.amdgcn.raw.ptr.buffer.load.f16(ptr addrspace(8) align 2 [[BUF]], i32 2, i32 0, i32 0)
@@ -379,7 +379,7 @@ define <2 x half> @load_v2f16_align2(ptr addrspace(8) inreg %buf) {
define void @store_v2f16_align2(<2 x half> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v2f16_align2(
-; CHECK-SAME: <2 x half> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <2 x half> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <2 x half> [[DATA]], i64 0
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.f16(half [[DATA_SLICE_0]], ptr addrspace(8) align 2 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <2 x half> [[DATA]], i64 1
@@ -393,7 +393,7 @@ define void @store_v2f16_align2(<2 x half> %data, ptr addrspace(8) inreg %buf) {
define <4 x bfloat> @load_v4bf16(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <4 x bfloat> @load_v4bf16(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call <4 x bfloat> @llvm.amdgcn.raw.ptr.buffer.load.v4bf16(ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret <4 x bfloat> [[RET]]
;
@@ -404,7 +404,7 @@ define <4 x bfloat> @load_v4bf16(ptr addrspace(8) inreg %buf) {
define void @store_v4bf16(<4 x bfloat> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v4bf16(
-; CHECK-SAME: <4 x bfloat> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <4 x bfloat> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4bf16(<4 x bfloat> [[DATA]], ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -415,7 +415,7 @@ define void @store_v4bf16(<4 x bfloat> %data, ptr addrspace(8) inreg %buf) {
define <8 x half> @load_v8f16(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <8 x half> @load_v8f16(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call <8 x half> @llvm.amdgcn.raw.ptr.buffer.load.v8f16(ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret <8 x half> [[RET]]
;
@@ -426,7 +426,7 @@ define <8 x half> @load_v8f16(ptr addrspace(8) inreg %buf) {
define void @store_v8f16(<8 x half> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v8f16(
-; CHECK-SAME: <8 x half> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <8 x half> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v8f16(<8 x half> [[DATA]], ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -437,7 +437,7 @@ define void @store_v8f16(<8 x half> %data, ptr addrspace(8) inreg %buf) {
define float @load_f32(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define float @load_f32(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret float [[RET]]
;
@@ -448,7 +448,7 @@ define float @load_f32(ptr addrspace(8) inreg %buf) {
define void @store_f32(float %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_f32(
-; CHECK-SAME: float [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: float [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -459,7 +459,7 @@ define void @store_f32(float %data, ptr addrspace(8) inreg %buf) {
define <2 x float> @load_v2f32(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <2 x float> @load_v2f32(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call <2 x float> @llvm.amdgcn.raw.ptr.buffer.load.v2f32(ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret <2 x float> [[RET]]
;
@@ -470,7 +470,7 @@ define <2 x float> @load_v2f32(ptr addrspace(8) inreg %buf) {
define void @store_v2f32(<2 x float> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v2f32(
-; CHECK-SAME: <2 x float> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <2 x float> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2f32(<2 x float> [[DATA]], ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -481,7 +481,7 @@ define void @store_v2f32(<2 x float> %data, ptr addrspace(8) inreg %buf) {
define <3 x float> @load_v3f32(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <3 x float> @load_v3f32(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call <3 x float> @llvm.amdgcn.raw.ptr.buffer.load.v3f32(ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret <3 x float> [[RET]]
;
@@ -492,7 +492,7 @@ define <3 x float> @load_v3f32(ptr addrspace(8) inreg %buf) {
define void @store_v3f32(<3 x float> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v3f32(
-; CHECK-SAME: <3 x float> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <3 x float> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v3f32(<3 x float> [[DATA]], ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -503,7 +503,7 @@ define void @store_v3f32(<3 x float> %data, ptr addrspace(8) inreg %buf) {
define <4 x float> @load_v4f32(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <4 x float> @load_v4f32(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call <4 x float> @llvm.amdgcn.raw.ptr.buffer.load.v4f32(ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret <4 x float> [[RET]]
;
@@ -514,7 +514,7 @@ define <4 x float> @load_v4f32(ptr addrspace(8) inreg %buf) {
define void @store_v4f32(<4 x float> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v4f32(
-; CHECK-SAME: <4 x float> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <4 x float> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4f32(<4 x float> [[DATA]], ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -525,7 +525,7 @@ define void @store_v4f32(<4 x float> %data, ptr addrspace(8) inreg %buf) {
define ptr addrspace(0) @load_p0(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define ptr @load_p0(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call ptr @llvm.amdgcn.raw.ptr.buffer.load.p0(ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret ptr [[RET]]
;
@@ -536,7 +536,7 @@ define ptr addrspace(0) @load_p0(ptr addrspace(8) inreg %buf) {
define void @store_p0(ptr addrspace(0) %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_p0(
-; CHECK-SAME: ptr [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.p0(ptr [[DATA]], ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -547,7 +547,7 @@ define void @store_p0(ptr addrspace(0) %data, ptr addrspace(8) inreg %buf) {
define ptr addrspace(1) @load_p1(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define ptr addrspace(1) @load_p1(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call ptr addrspace(1) @llvm.amdgcn.raw.ptr.buffer.load.p1(ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret ptr addrspace(1) [[RET]]
;
@@ -558,7 +558,7 @@ define ptr addrspace(1) @load_p1(ptr addrspace(8) inreg %buf) {
define void @store_p1(ptr addrspace(1) %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_p1(
-; CHECK-SAME: ptr addrspace(1) [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(1) [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.p1(ptr addrspace(1) [[DATA]], ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -569,7 +569,7 @@ define void @store_p1(ptr addrspace(1) %data, ptr addrspace(8) inreg %buf) {
define ptr addrspace(2) @load_p2(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define ptr addrspace(2) @load_p2(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call ptr addrspace(2) @llvm.amdgcn.raw.ptr.buffer.load.p2(ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret ptr addrspace(2) [[RET]]
;
@@ -580,7 +580,7 @@ define ptr addrspace(2) @load_p2(ptr addrspace(8) inreg %buf) {
define void @store_p2(ptr addrspace(2) %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_p2(
-; CHECK-SAME: ptr addrspace(2) [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(2) [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.p2(ptr addrspace(2) [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -591,7 +591,7 @@ define void @store_p2(ptr addrspace(2) %data, ptr addrspace(8) inreg %buf) {
define ptr addrspace(3) @load_p3(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define ptr addrspace(3) @load_p3(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call ptr addrspace(3) @llvm.amdgcn.raw.ptr.buffer.load.p3(ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret ptr addrspace(3) [[RET]]
;
@@ -602,7 +602,7 @@ define ptr addrspace(3) @load_p3(ptr addrspace(8) inreg %buf) {
define void @store_p3(ptr addrspace(3) %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_p3(
-; CHECK-SAME: ptr addrspace(3) [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(3) [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.p3(ptr addrspace(3) [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -613,7 +613,7 @@ define void @store_p3(ptr addrspace(3) %data, ptr addrspace(8) inreg %buf) {
define ptr addrspace(4) @load_p4(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define ptr addrspace(4) @load_p4(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call ptr addrspace(4) @llvm.amdgcn.raw.ptr.buffer.load.p4(ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret ptr addrspace(4) [[RET]]
;
@@ -624,7 +624,7 @@ define ptr addrspace(4) @load_p4(ptr addrspace(8) inreg %buf) {
define void @store_p4(ptr addrspace(4) %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_p4(
-; CHECK-SAME: ptr addrspace(4) [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(4) [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.p4(ptr addrspace(4) [[DATA]], ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -635,7 +635,7 @@ define void @store_p4(ptr addrspace(4) %data, ptr addrspace(8) inreg %buf) {
define ptr addrspace(5) @load_p5(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define ptr addrspace(5) @load_p5(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call ptr addrspace(5) @llvm.amdgcn.raw.ptr.buffer.load.p5(ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret ptr addrspace(5) [[RET]]
;
@@ -646,7 +646,7 @@ define ptr addrspace(5) @load_p5(ptr addrspace(8) inreg %buf) {
define void @store_p5(ptr addrspace(5) %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_p5(
-; CHECK-SAME: ptr addrspace(5) [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(5) [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.p5(ptr addrspace(5) [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -657,7 +657,7 @@ define void @store_p5(ptr addrspace(5) %data, ptr addrspace(8) inreg %buf) {
define ptr addrspace(6) @load_p6(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define ptr addrspace(6) @load_p6(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call ptr addrspace(6) @llvm.amdgcn.raw.ptr.buffer.load.p6(ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret ptr addrspace(6) [[RET]]
;
@@ -668,7 +668,7 @@ define ptr addrspace(6) @load_p6(ptr addrspace(8) inreg %buf) {
define void @store_p6(ptr addrspace(6) %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_p6(
-; CHECK-SAME: ptr addrspace(6) [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(6) [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.p6(ptr addrspace(6) [[DATA]], ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -679,7 +679,7 @@ define void @store_p6(ptr addrspace(6) %data, ptr addrspace(8) inreg %buf) {
define ptr addrspace(8) @load_p8(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define ptr addrspace(8) @load_p8(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call ptr addrspace(8) @llvm.amdgcn.raw.ptr.buffer.load.p8(ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret ptr addrspace(8) [[RET]]
;
@@ -690,7 +690,7 @@ define ptr addrspace(8) @load_p8(ptr addrspace(8) inreg %buf) {
define void @store_p8(ptr addrspace(8) %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_p8(
-; CHECK-SAME: ptr addrspace(8) [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.p8(ptr addrspace(8) [[DATA]], ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -701,7 +701,7 @@ define void @store_p8(ptr addrspace(8) %data, ptr addrspace(8) inreg %buf) {
define <2 x ptr addrspace(1)> @load_v2p1(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <2 x ptr addrspace(1)> @load_v2p1(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call <2 x ptr addrspace(1)> @llvm.amdgcn.raw.ptr.buffer.load.v2p1(ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret <2 x ptr addrspace(1)> [[RET]]
;
@@ -712,7 +712,7 @@ define <2 x ptr addrspace(1)> @load_v2p1(ptr addrspace(8) inreg %buf) {
define void @store_v2p1(<2 x ptr addrspace(1)> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v2p1(
-; CHECK-SAME: <2 x ptr addrspace(1)> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <2 x ptr addrspace(1)> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2p1(<2 x ptr addrspace(1)> [[DATA]], ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -723,7 +723,7 @@ define void @store_v2p1(<2 x ptr addrspace(1)> %data, ptr addrspace(8) inreg %bu
define <2 x ptr addrspace(5)> @load_v2p5(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <2 x ptr addrspace(5)> @load_v2p5(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call <2 x ptr addrspace(5)> @llvm.amdgcn.raw.ptr.buffer.load.v2p5(ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret <2 x ptr addrspace(5)> [[RET]]
;
@@ -734,7 +734,7 @@ define <2 x ptr addrspace(5)> @load_v2p5(ptr addrspace(8) inreg %buf) {
define void @store_v2p5(<2 x ptr addrspace(5)> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v2p5(
-; CHECK-SAME: <2 x ptr addrspace(5)> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <2 x ptr addrspace(5)> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2p5(<2 x ptr addrspace(5)> [[DATA]], ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -745,7 +745,7 @@ define void @store_v2p5(<2 x ptr addrspace(5)> %data, ptr addrspace(8) inreg %bu
define <3 x ptr addrspace(5)> @load_v3p5(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <3 x ptr addrspace(5)> @load_v3p5(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call <3 x ptr addrspace(5)> @llvm.amdgcn.raw.ptr.buffer.load.v3p5(ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret <3 x ptr addrspace(5)> [[RET]]
;
@@ -756,7 +756,7 @@ define <3 x ptr addrspace(5)> @load_v3p5(ptr addrspace(8) inreg %buf) {
define void @store_v3p5(<3 x ptr addrspace(5)> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v3p5(
-; CHECK-SAME: <3 x ptr addrspace(5)> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <3 x ptr addrspace(5)> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v3p5(<3 x ptr addrspace(5)> [[DATA]], ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -767,7 +767,7 @@ define void @store_v3p5(<3 x ptr addrspace(5)> %data, ptr addrspace(8) inreg %bu
define <4 x ptr addrspace(5)> @load_v4p5(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <4 x ptr addrspace(5)> @load_v4p5(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call <4 x ptr addrspace(5)> @llvm.amdgcn.raw.ptr.buffer.load.v4p5(ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret <4 x ptr addrspace(5)> [[RET]]
;
@@ -778,7 +778,7 @@ define <4 x ptr addrspace(5)> @load_v4p5(ptr addrspace(8) inreg %buf) {
define void @store_v4p5(<4 x ptr addrspace(5)> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v4p5(
-; CHECK-SAME: <4 x ptr addrspace(5)> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <4 x ptr addrspace(5)> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4p5(<4 x ptr addrspace(5)> [[DATA]], ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
@@ -791,7 +791,7 @@ define void @store_v4p5(<4 x ptr addrspace(5)> %data, ptr addrspace(8) inreg %bu
define <6 x half> @load_v6f16(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <6 x half> @load_v6f16(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_LOADABLE:%.*]] = call <3 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v3i32(ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET:%.*]] = bitcast <3 x i32> [[RET_LOADABLE]] to <6 x half>
; CHECK-NEXT: ret <6 x half> [[RET]]
@@ -803,7 +803,7 @@ define <6 x half> @load_v6f16(ptr addrspace(8) inreg %buf) {
define void @store_v6f16(<6 x half> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v6f16(
-; CHECK-SAME: <6 x half> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <6 x half> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_STORABLE:%.*]] = bitcast <6 x half> [[DATA]] to <3 x i32>
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> [[DATA_STORABLE]], ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
@@ -817,7 +817,7 @@ define void @store_v6f16(<6 x half> %data, ptr addrspace(8) inreg %buf) {
define <5 x float> @load_v5f32(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <5 x float> @load_v5f32(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_OFF_0:%.*]] = call <4 x float> @llvm.amdgcn.raw.ptr.buffer.load.v4f32(ptr addrspace(8) align 32 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x float> [[RET_OFF_0]], <4 x float> poison, <5 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison>
; CHECK-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <5 x float> poison, <5 x float> [[RET_EXT_0]], <5 x i32> <i32 5, i32 6, i32 7, i32 8, i32 4>
@@ -832,7 +832,7 @@ define <5 x float> @load_v5f32(ptr addrspace(8) inreg %buf) {
define void @store_v5f32(<5 x float> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v5f32(
-; CHECK-SAME: <5 x float> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <5 x float> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <5 x float> [[DATA]], <5 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4f32(<4 x float> [[DATA_SLICE_0]], ptr addrspace(8) align 32 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[DATA_SLICE_4:%.*]] = extractelement <5 x float> [[DATA]], i64 4
@@ -846,7 +846,7 @@ define void @store_v5f32(<5 x float> %data, ptr addrspace(8) inreg %buf) {
define <6 x float> @load_v6f32(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <6 x float> @load_v6f32(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_OFF_0:%.*]] = call <4 x float> @llvm.amdgcn.raw.ptr.buffer.load.v4f32(ptr addrspace(8) align 32 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x float> [[RET_OFF_0]], <4 x float> poison, <6 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison>
; CHECK-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <6 x float> poison, <6 x float> [[RET_EXT_0]], <6 x i32> <i32 6, i32 7, i32 8, i32 9, i32 4, i32 5>
@@ -862,7 +862,7 @@ define <6 x float> @load_v6f32(ptr addrspace(8) inreg %buf) {
define void @store_v6f32(<6 x float> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v6f32(
-; CHECK-SAME: <6 x float> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <6 x float> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <6 x float> [[DATA]], <6 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4f32(<4 x float> [[DATA_SLICE_0]], ptr addrspace(8) align 32 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[DATA_SLICE_4:%.*]] = shufflevector <6 x float> [[DATA]], <6 x float> poison, <2 x i32> <i32 4, i32 5>
@@ -876,7 +876,7 @@ define void @store_v6f32(<6 x float> %data, ptr addrspace(8) inreg %buf) {
define <7 x float> @load_v7f32(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <7 x float> @load_v7f32(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_OFF_0:%.*]] = call <4 x float> @llvm.amdgcn.raw.ptr.buffer.load.v4f32(ptr addrspace(8) align 32 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x float> [[RET_OFF_0]], <4 x float> poison, <7 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <7 x float> poison, <7 x float> [[RET_EXT_0]], <7 x i32> <i32 7, i32 8, i32 9, i32 10, i32 4, i32 5, i32 6>
@@ -892,7 +892,7 @@ define <7 x float> @load_v7f32(ptr addrspace(8) inreg %buf) {
define void @store_v7f32(<7 x float> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v7f32(
-; CHECK-SAME: <7 x float> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <7 x float> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <7 x float> [[DATA]], <7 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4f32(<4 x float> [[DATA_SLICE_0]], ptr addrspace(8) align 32 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[DATA_SLICE_4:%.*]] = shufflevector <7 x float> [[DATA]], <7 x float> poison, <3 x i32> <i32 4, i32 5, i32 6>
@@ -906,7 +906,7 @@ define void @store_v7f32(<7 x float> %data, ptr addrspace(8) inreg %buf) {
define <8 x float> @load_v8f32(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <8 x float> @load_v8f32(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_OFF_0:%.*]] = call <4 x float> @llvm.amdgcn.raw.ptr.buffer.load.v4f32(ptr addrspace(8) align 32 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x float> [[RET_OFF_0]], <4 x float> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <8 x float> poison, <8 x float> [[RET_EXT_0]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
@@ -922,7 +922,7 @@ define <8 x float> @load_v8f32(ptr addrspace(8) inreg %buf) {
define void @store_v8f32(<8 x float> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v8f32(
-; CHECK-SAME: <8 x float> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <8 x float> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <8 x float> [[DATA]], <8 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4f32(<4 x float> [[DATA_SLICE_0]], ptr addrspace(8) align 32 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[DATA_SLICE_4:%.*]] = shufflevector <8 x float> [[DATA]], <8 x float> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -936,7 +936,7 @@ define void @store_v8f32(<8 x float> %data, ptr addrspace(8) inreg %buf) {
define <10 x float> @load_v10f32(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <10 x float> @load_v10f32(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_OFF_0:%.*]] = call <4 x float> @llvm.amdgcn.raw.ptr.buffer.load.v4f32(ptr addrspace(8) align 64 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x float> [[RET_OFF_0]], <4 x float> poison, <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <10 x float> poison, <10 x float> [[RET_EXT_0]], <10 x i32> <i32 10, i32 11, i32 12, i32 13, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
@@ -955,7 +955,7 @@ define <10 x float> @load_v10f32(ptr addrspace(8) inreg %buf) {
define void @store_v10f32(<10 x float> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v10f32(
-; CHECK-SAME: <10 x float> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <10 x float> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <10 x float> [[DATA]], <10 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4f32(<4 x float> [[DATA_SLICE_0]], ptr addrspace(8) align 64 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[DATA_SLICE_4:%.*]] = shufflevector <10 x float> [[DATA]], <10 x float> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -971,7 +971,7 @@ define void @store_v10f32(<10 x float> %data, ptr addrspace(8) inreg %buf) {
define <6 x i32> @load_v6i32(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <6 x i32> @load_v6i32(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_OFF_0:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 32 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i32> [[RET_OFF_0]], <4 x i32> poison, <6 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison>
; CHECK-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <6 x i32> poison, <6 x i32> [[RET_EXT_0]], <6 x i32> <i32 6, i32 7, i32 8, i32 9, i32 4, i32 5>
@@ -987,7 +987,7 @@ define <6 x i32> @load_v6i32(ptr addrspace(8) inreg %buf) {
define void @store_v6i32(<6 x i32> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v6i32(
-; CHECK-SAME: <6 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <6 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <6 x i32> [[DATA]], <6 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 32 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[DATA_SLICE_4:%.*]] = shufflevector <6 x i32> [[DATA]], <6 x i32> poison, <2 x i32> <i32 4, i32 5>
@@ -1001,7 +1001,7 @@ define void @store_v6i32(<6 x i32> %data, ptr addrspace(8) inreg %buf) {
define <4 x ptr addrspace(1)> @load_v4p1(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <4 x ptr addrspace(1)> @load_v4p1(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_OFF_0:%.*]] = call <2 x ptr addrspace(1)> @llvm.amdgcn.raw.ptr.buffer.load.v2p1(ptr addrspace(8) align 32 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET_EXT_0:%.*]] = shufflevector <2 x ptr addrspace(1)> [[RET_OFF_0]], <2 x ptr addrspace(1)> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <4 x ptr addrspace(1)> poison, <4 x ptr addrspace(1)> [[RET_EXT_0]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
@@ -1017,7 +1017,7 @@ define <4 x ptr addrspace(1)> @load_v4p1(ptr addrspace(8) inreg %buf) {
define void @store_v4p1(<4 x ptr addrspace(1)> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v4p1(
-; CHECK-SAME: <4 x ptr addrspace(1)> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <4 x ptr addrspace(1)> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <4 x ptr addrspace(1)> [[DATA]], <4 x ptr addrspace(1)> poison, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2p1(<2 x ptr addrspace(1)> [[DATA_SLICE_0]], ptr addrspace(8) align 32 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[DATA_SLICE_2:%.*]] = shufflevector <4 x ptr addrspace(1)> [[DATA]], <4 x ptr addrspace(1)> poison, <2 x i32> <i32 2, i32 3>
@@ -1033,7 +1033,7 @@ define void @store_v4p1(<4 x ptr addrspace(1)> %data, ptr addrspace(8) inreg %bu
define <1 x i16> @load_v1i16(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <1 x i16> @load_v1i16(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_LOADABLE:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET:%.*]] = bitcast i16 [[RET_LOADABLE]] to <1 x i16>
; CHECK-NEXT: ret <1 x i16> [[RET]]
@@ -1045,7 +1045,7 @@ define <1 x i16> @load_v1i16(ptr addrspace(8) inreg %buf) {
define void @store_v1i16(<1 x i16> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v1i16(
-; CHECK-SAME: <1 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <1 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_STORABLE:%.*]] = bitcast <1 x i16> [[DATA]] to i16
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_STORABLE]], ptr addrspace(8) align 2 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
@@ -1057,7 +1057,7 @@ define void @store_v1i16(<1 x i16> %data, ptr addrspace(8) inreg %buf) {
define <3 x i16> @load_v3i16(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <3 x i16> @load_v3i16(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_OFF_0:%.*]] = call <2 x i16> @llvm.amdgcn.raw.ptr.buffer.load.v2i16(ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET_EXT_0:%.*]] = shufflevector <2 x i16> [[RET_OFF_0]], <2 x i16> poison, <3 x i32> <i32 0, i32 1, i32 poison>
; CHECK-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <3 x i16> poison, <3 x i16> [[RET_EXT_0]], <3 x i32> <i32 3, i32 4, i32 2>
@@ -1072,7 +1072,7 @@ define <3 x i16> @load_v3i16(ptr addrspace(8) inreg %buf) {
define void @store_v3i16(<3 x i16> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v3i16(
-; CHECK-SAME: <3 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <3 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <3 x i16> [[DATA]], <3 x i16> poison, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i16(<2 x i16> [[DATA_SLICE_0]], ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[DATA_SLICE_2:%.*]] = extractelement <3 x i16> [[DATA]], i64 2
@@ -1086,7 +1086,7 @@ define void @store_v3i16(<3 x i16> %data, ptr addrspace(8) inreg %buf) {
define <5 x i16> @load_v5i16(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <5 x i16> @load_v5i16(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_OFF_0:%.*]] = call <4 x i16> @llvm.amdgcn.raw.ptr.buffer.load.v4i16(ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i16> [[RET_OFF_0]], <4 x i16> poison, <5 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison>
; CHECK-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <5 x i16> poison, <5 x i16> [[RET_EXT_0]], <5 x i32> <i32 5, i32 6, i32 7, i32 8, i32 4>
@@ -1101,7 +1101,7 @@ define <5 x i16> @load_v5i16(ptr addrspace(8) inreg %buf) {
define void @store_v5i16(<5 x i16> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v5i16(
-; CHECK-SAME: <5 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <5 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <5 x i16> [[DATA]], <5 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i16(<4 x i16> [[DATA_SLICE_0]], ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[DATA_SLICE_4:%.*]] = extractelement <5 x i16> [[DATA]], i64 4
@@ -1115,7 +1115,7 @@ define void @store_v5i16(<5 x i16> %data, ptr addrspace(8) inreg %buf) {
define <6 x i16> @load_v6i16(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <6 x i16> @load_v6i16(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_LOADABLE:%.*]] = call <3 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v3i32(ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET:%.*]] = bitcast <3 x i32> [[RET_LOADABLE]] to <6 x i16>
; CHECK-NEXT: ret <6 x i16> [[RET]]
@@ -1127,7 +1127,7 @@ define <6 x i16> @load_v6i16(ptr addrspace(8) inreg %buf) {
define void @store_v6i16(<6 x i16> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v6i16(
-; CHECK-SAME: <6 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <6 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_STORABLE:%.*]] = bitcast <6 x i16> [[DATA]] to <3 x i32>
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> [[DATA_STORABLE]], ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
@@ -1139,7 +1139,7 @@ define void @store_v6i16(<6 x i16> %data, ptr addrspace(8) inreg %buf) {
define <7 x i16> @load_v7i16(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <7 x i16> @load_v7i16(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_OFF_0:%.*]] = call <3 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v3i32(ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET_OFF_0_FROM_LOADABLE:%.*]] = bitcast <3 x i32> [[RET_OFF_0]] to <6 x i16>
; CHECK-NEXT: [[RET_EXT_0:%.*]] = shufflevector <6 x i16> [[RET_OFF_0_FROM_LOADABLE]], <6 x i16> poison, <7 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 poison>
@@ -1155,7 +1155,7 @@ define <7 x i16> @load_v7i16(ptr addrspace(8) inreg %buf) {
define void @store_v7i16(<7 x i16> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v7i16(
-; CHECK-SAME: <7 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <7 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <7 x i16> [[DATA]], <7 x i16> poison, <6 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5>
; CHECK-NEXT: [[DATA_SLICE_0_STORABLE:%.*]] = bitcast <6 x i16> [[DATA_SLICE_0]] to <3 x i32>
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> [[DATA_SLICE_0_STORABLE]], ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
@@ -1170,7 +1170,7 @@ define void @store_v7i16(<7 x i16> %data, ptr addrspace(8) inreg %buf) {
define <9 x i16> @load_v9i16(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <9 x i16> @load_v9i16(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_OFF_0:%.*]] = call <8 x i16> @llvm.amdgcn.raw.ptr.buffer.load.v8i16(ptr addrspace(8) align 32 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET_EXT_0:%.*]] = shufflevector <8 x i16> [[RET_OFF_0]], <8 x i16> poison, <9 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison>
; CHECK-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <9 x i16> poison, <9 x i16> [[RET_EXT_0]], <9 x i32> <i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 8>
@@ -1185,7 +1185,7 @@ define <9 x i16> @load_v9i16(ptr addrspace(8) inreg %buf) {
define void @store_v9i16(<9 x i16> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v9i16(
-; CHECK-SAME: <9 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <9 x i16> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <9 x i16> [[DATA]], <9 x i16> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v8i16(<8 x i16> [[DATA_SLICE_0]], ptr addrspace(8) align 32 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[DATA_SLICE_8:%.*]] = extractelement <9 x i16> [[DATA]], i64 8
@@ -1203,7 +1203,7 @@ define void @store_v9i16(<9 x i16> %data, ptr addrspace(8) inreg %buf) {
define <1 x i8> @load_v1i8(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <1 x i8> @load_v1i8(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_LOADABLE:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET:%.*]] = bitcast i8 [[RET_LOADABLE]] to <1 x i8>
; CHECK-NEXT: ret <1 x i8> [[RET]]
@@ -1215,7 +1215,7 @@ define <1 x i8> @load_v1i8(ptr addrspace(8) inreg %buf) {
define void @store_v1i8(<1 x i8> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v1i8(
-; CHECK-SAME: <1 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <1 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_LEGAL:%.*]] = bitcast <1 x i8> [[DATA]] to i8
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_LEGAL]], ptr addrspace(8) align 1 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
@@ -1227,7 +1227,7 @@ define void @store_v1i8(<1 x i8> %data, ptr addrspace(8) inreg %buf) {
define <2 x i8> @load_v2i8(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <2 x i8> @load_v2i8(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_LOADABLE:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET:%.*]] = bitcast i16 [[RET_LOADABLE]] to <2 x i8>
; CHECK-NEXT: ret <2 x i8> [[RET]]
@@ -1239,7 +1239,7 @@ define <2 x i8> @load_v2i8(ptr addrspace(8) inreg %buf) {
define void @store_v2i8(<2 x i8> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v2i8(
-; CHECK-SAME: <2 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <2 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_LEGAL:%.*]] = bitcast <2 x i8> [[DATA]] to i16
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_LEGAL]], ptr addrspace(8) align 2 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
@@ -1251,7 +1251,7 @@ define void @store_v2i8(<2 x i8> %data, ptr addrspace(8) inreg %buf) {
define <3 x i8> @load_v3i8(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <3 x i8> @load_v3i8(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_OFF_0:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET_OFF_0_FROM_LOADABLE:%.*]] = bitcast i16 [[RET_OFF_0]] to <2 x i8>
; CHECK-NEXT: [[RET_EXT_0:%.*]] = shufflevector <2 x i8> [[RET_OFF_0_FROM_LOADABLE]], <2 x i8> poison, <3 x i32> <i32 0, i32 1, i32 poison>
@@ -1267,7 +1267,7 @@ define <3 x i8> @load_v3i8(ptr addrspace(8) inreg %buf) {
define void @store_v3i8(<3 x i8> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v3i8(
-; CHECK-SAME: <3 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <3 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <3 x i8> [[DATA]], <3 x i8> poison, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: [[DATA_SLICE_0_STORABLE:%.*]] = bitcast <2 x i8> [[DATA_SLICE_0]] to i16
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_SLICE_0_STORABLE]], ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
@@ -1282,7 +1282,7 @@ define void @store_v3i8(<3 x i8> %data, ptr addrspace(8) inreg %buf) {
define <4 x i8> @load_v4i8(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <4 x i8> @load_v4i8(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_LOADABLE:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET:%.*]] = bitcast i32 [[RET_LOADABLE]] to <4 x i8>
; CHECK-NEXT: ret <4 x i8> [[RET]]
@@ -1294,7 +1294,7 @@ define <4 x i8> @load_v4i8(ptr addrspace(8) inreg %buf) {
define void @store_v4i8(<4 x i8> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v4i8(
-; CHECK-SAME: <4 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <4 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_LEGAL:%.*]] = bitcast <4 x i8> [[DATA]] to i32
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_LEGAL]], ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
@@ -1306,7 +1306,7 @@ define void @store_v4i8(<4 x i8> %data, ptr addrspace(8) inreg %buf) {
define <5 x i8> @load_v5i8(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <5 x i8> @load_v5i8(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_OFF_0:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET_OFF_0_FROM_LOADABLE:%.*]] = bitcast i32 [[RET_OFF_0]] to <4 x i8>
; CHECK-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i8> [[RET_OFF_0_FROM_LOADABLE]], <4 x i8> poison, <5 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison>
@@ -1322,7 +1322,7 @@ define <5 x i8> @load_v5i8(ptr addrspace(8) inreg %buf) {
define void @store_v5i8(<5 x i8> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v5i8(
-; CHECK-SAME: <5 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <5 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <5 x i8> [[DATA]], <5 x i8> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[DATA_SLICE_0_STORABLE:%.*]] = bitcast <4 x i8> [[DATA_SLICE_0]] to i32
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_0_STORABLE]], ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
@@ -1337,7 +1337,7 @@ define void @store_v5i8(<5 x i8> %data, ptr addrspace(8) inreg %buf) {
define <6 x i8> @load_v6i8(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <6 x i8> @load_v6i8(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_OFF_0:%.*]] = call <2 x i16> @llvm.amdgcn.raw.ptr.buffer.load.v2i16(ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET_EXT_0:%.*]] = shufflevector <2 x i16> [[RET_OFF_0]], <2 x i16> poison, <3 x i32> <i32 0, i32 1, i32 poison>
; CHECK-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <3 x i16> poison, <3 x i16> [[RET_EXT_0]], <3 x i32> <i32 3, i32 4, i32 2>
@@ -1353,7 +1353,7 @@ define <6 x i8> @load_v6i8(ptr addrspace(8) inreg %buf) {
define void @store_v6i8(<6 x i8> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v6i8(
-; CHECK-SAME: <6 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <6 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_LEGAL:%.*]] = bitcast <6 x i8> [[DATA]] to <3 x i16>
; CHECK-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <3 x i16> [[DATA_LEGAL]], <3 x i16> poison, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i16(<2 x i16> [[DATA_SLICE_0]], ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
@@ -1368,7 +1368,7 @@ define void @store_v6i8(<6 x i8> %data, ptr addrspace(8) inreg %buf) {
define <7 x i8> @load_v7i8(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <7 x i8> @load_v7i8(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_OFF_0:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET_OFF_0_FROM_LOADABLE:%.*]] = bitcast i32 [[RET_OFF_0]] to <4 x i8>
; CHECK-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i8> [[RET_OFF_0_FROM_LOADABLE]], <4 x i8> poison, <7 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison>
@@ -1388,7 +1388,7 @@ define <7 x i8> @load_v7i8(ptr addrspace(8) inreg %buf) {
define void @store_v7i8(<7 x i8> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v7i8(
-; CHECK-SAME: <7 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <7 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <7 x i8> [[DATA]], <7 x i8> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[DATA_SLICE_0_STORABLE:%.*]] = bitcast <4 x i8> [[DATA_SLICE_0]] to i32
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_SLICE_0_STORABLE]], ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
@@ -1406,7 +1406,7 @@ define void @store_v7i8(<7 x i8> %data, ptr addrspace(8) inreg %buf) {
define <8 x i8> @load_v8i8(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <8 x i8> @load_v8i8(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_LOADABLE:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET:%.*]] = bitcast <2 x i32> [[RET_LOADABLE]] to <8 x i8>
; CHECK-NEXT: ret <8 x i8> [[RET]]
@@ -1418,7 +1418,7 @@ define <8 x i8> @load_v8i8(ptr addrspace(8) inreg %buf) {
define void @store_v8i8(<8 x i8> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v8i8(
-; CHECK-SAME: <8 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <8 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_LEGAL:%.*]] = bitcast <8 x i8> [[DATA]] to <2 x i32>
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_LEGAL]], ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
@@ -1430,7 +1430,7 @@ define void @store_v8i8(<8 x i8> %data, ptr addrspace(8) inreg %buf) {
define <8 x i8> @load_v8i8_align1(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <8 x i8> @load_v8i8_align1(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET_SLICE_0:%.*]] = insertelement <8 x i8> poison, i8 [[RET_OFF_0]], i64 0
; CHECK-NEXT: [[RET_OFF_1:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 1, i32 0, i32 0)
@@ -1456,7 +1456,7 @@ define <8 x i8> @load_v8i8_align1(ptr addrspace(8) inreg %buf) {
define void @store_v8i8_align1(<8 x i8> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v8i8_align1(
-; CHECK-SAME: <8 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <8 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_SLICE_0:%.*]] = extractelement <8 x i8> [[DATA]], i64 0
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_SLICE_0]], ptr addrspace(8) align 1 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[DATA_SLICE_1:%.*]] = extractelement <8 x i8> [[DATA]], i64 1
@@ -1482,7 +1482,7 @@ define void @store_v8i8_align1(<8 x i8> %data, ptr addrspace(8) inreg %buf) {
define <12 x i8> @load_v12i8(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <12 x i8> @load_v12i8(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_LOADABLE:%.*]] = call <3 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v3i32(ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET:%.*]] = bitcast <3 x i32> [[RET_LOADABLE]] to <12 x i8>
; CHECK-NEXT: ret <12 x i8> [[RET]]
@@ -1494,7 +1494,7 @@ define <12 x i8> @load_v12i8(ptr addrspace(8) inreg %buf) {
define void @store_v12i8(<12 x i8> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v12i8(
-; CHECK-SAME: <12 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <12 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_LEGAL:%.*]] = bitcast <12 x i8> [[DATA]] to <3 x i32>
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> [[DATA_LEGAL]], ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
@@ -1506,7 +1506,7 @@ define void @store_v12i8(<12 x i8> %data, ptr addrspace(8) inreg %buf) {
define <16 x i8> @load_v16i8(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <16 x i8> @load_v16i8(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_LOADABLE:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET:%.*]] = bitcast <4 x i32> [[RET_LOADABLE]] to <16 x i8>
; CHECK-NEXT: ret <16 x i8> [[RET]]
@@ -1518,7 +1518,7 @@ define <16 x i8> @load_v16i8(ptr addrspace(8) inreg %buf) {
define void @store_v16i8(<16 x i8> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v16i8(
-; CHECK-SAME: <16 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <16 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_LEGAL:%.*]] = bitcast <16 x i8> [[DATA]] to <4 x i32>
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_LEGAL]], ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
@@ -1530,7 +1530,7 @@ define void @store_v16i8(<16 x i8> %data, ptr addrspace(8) inreg %buf) {
define <32 x i8> @load_v32i8(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <32 x i8> @load_v32i8(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_OFF_0:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 32 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i32> [[RET_OFF_0]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <8 x i32> poison, <8 x i32> [[RET_EXT_0]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
@@ -1547,7 +1547,7 @@ define <32 x i8> @load_v32i8(ptr addrspace(8) inreg %buf) {
define void @store_v32i8(<32 x i8> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v32i8(
-; CHECK-SAME: <32 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <32 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_LEGAL:%.*]] = bitcast <32 x i8> [[DATA]] to <8 x i32>
; CHECK-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <8 x i32> [[DATA_LEGAL]], <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 32 [[BUF]], i32 0, i32 0, i32 0)
@@ -1564,7 +1564,7 @@ define void @store_v32i8(<32 x i8> %data, ptr addrspace(8) inreg %buf) {
define [1 x i32] @load_a1i32(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define [1 x i32] @load_a1i32(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_LOADABLE:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET_FROM_LOADABLE:%.*]] = bitcast i32 [[RET_LOADABLE]] to <1 x i32>
; CHECK-NEXT: [[RET_ELEM_0:%.*]] = extractelement <1 x i32> [[RET_FROM_LOADABLE]], i64 0
@@ -1578,7 +1578,7 @@ define [1 x i32] @load_a1i32(ptr addrspace(8) inreg %buf) {
define void @store_a1i32([1 x i32] %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_a1i32(
-; CHECK-SAME: [1 x i32] [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: [1 x i32] [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_ELEM_0:%.*]] = extractvalue [1 x i32] [[DATA]], 0
; CHECK-NEXT: [[DATA_AS_VEC_0:%.*]] = insertelement <1 x i32> poison, i32 [[DATA_ELEM_0]], i64 0
; CHECK-NEXT: [[DATA_STORABLE:%.*]] = bitcast <1 x i32> [[DATA_AS_VEC_0]] to i32
@@ -1592,7 +1592,7 @@ define void @store_a1i32([1 x i32] %data, ptr addrspace(8) inreg %buf) {
define [2 x i32] @load_a2i32(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define [2 x i32] @load_a2i32(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_LOADABLE:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET_OFF_0:%.*]] = extractelement <2 x i32> [[RET_LOADABLE]], i64 0
; CHECK-NEXT: [[RET_AS_ARRAY_0:%.*]] = insertvalue [2 x i32] poison, i32 [[RET_OFF_0]], 0
@@ -1607,7 +1607,7 @@ define [2 x i32] @load_a2i32(ptr addrspace(8) inreg %buf) {
define void @store_a2i32([2 x i32] %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_a2i32(
-; CHECK-SAME: [2 x i32] [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: [2 x i32] [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_ELEM_0:%.*]] = extractvalue [2 x i32] [[DATA]], 0
; CHECK-NEXT: [[DATA_AS_VEC_0:%.*]] = insertelement <2 x i32> poison, i32 [[DATA_ELEM_0]], i64 0
; CHECK-NEXT: [[DATA_ELEM_1:%.*]] = extractvalue [2 x i32] [[DATA]], 1
@@ -1622,7 +1622,7 @@ define void @store_a2i32([2 x i32] %data, ptr addrspace(8) inreg %buf) {
define [2 x half] @load_a2f16(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define [2 x half] @load_a2f16(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_OFF_0:%.*]] = call half @llvm.amdgcn.raw.ptr.buffer.load.f16(ptr addrspace(8) align 2 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET_SLICE_0:%.*]] = insertelement <2 x half> poison, half [[RET_OFF_0]], i64 0
; CHECK-NEXT: [[RET_OFF_2:%.*]] = call half @llvm.amdgcn.raw.ptr.buffer.load.f16(ptr addrspace(8) align 2 [[BUF]], i32 2, i32 0, i32 0)
@@ -1638,7 +1638,7 @@ define [2 x half] @load_a2f16(ptr addrspace(8) inreg %buf) {
define void @store_a2f16([2 x half] %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_a2f16(
-; CHECK-SAME: [2 x half] [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: [2 x half] [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_ELEM_0:%.*]] = extractvalue [2 x half] [[DATA]], 0
; CHECK-NEXT: [[DATA_AS_VEC_0:%.*]] = insertelement <2 x half> poison, half [[DATA_ELEM_0]], i64 0
; CHECK-NEXT: [[DATA_ELEM_1:%.*]] = extractvalue [2 x half] [[DATA]], 1
@@ -1654,7 +1654,7 @@ define void @store_a2f16([2 x half] %data, ptr addrspace(8) inreg %buf) {
define [2 x ptr addrspace(1)] @load_a2p1(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define [2 x ptr addrspace(1)] @load_a2p1(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_LOADABLE:%.*]] = call <2 x ptr addrspace(1)> @llvm.amdgcn.raw.ptr.buffer.load.v2p1(ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET_OFF_0:%.*]] = extractelement <2 x ptr addrspace(1)> [[RET_LOADABLE]], i64 0
; CHECK-NEXT: [[RET_AS_ARRAY_0:%.*]] = insertvalue [2 x ptr addrspace(1)] poison, ptr addrspace(1) [[RET_OFF_0]], 0
@@ -1669,7 +1669,7 @@ define [2 x ptr addrspace(1)] @load_a2p1(ptr addrspace(8) inreg %buf) {
define void @store_a2p1([2 x ptr addrspace(1)] %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_a2p1(
-; CHECK-SAME: [2 x ptr addrspace(1)] [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: [2 x ptr addrspace(1)] [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_ELEM_0:%.*]] = extractvalue [2 x ptr addrspace(1)] [[DATA]], 0
; CHECK-NEXT: [[DATA_AS_VEC_0:%.*]] = insertelement <2 x ptr addrspace(1)> poison, ptr addrspace(1) [[DATA_ELEM_0]], i64 0
; CHECK-NEXT: [[DATA_ELEM_1:%.*]] = extractvalue [2 x ptr addrspace(1)] [[DATA]], 1
@@ -1686,7 +1686,7 @@ define void @store_a2p1([2 x ptr addrspace(1)] %data, ptr addrspace(8) inreg %bu
define i40 @load_i40(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define i40 @load_i40(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_OFF_0:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET_OFF_0_FROM_LOADABLE:%.*]] = bitcast i32 [[RET_OFF_0]] to <4 x i8>
; CHECK-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i8> [[RET_OFF_0_FROM_LOADABLE]], <4 x i8> poison, <5 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison>
@@ -1703,7 +1703,7 @@ define i40 @load_i40(ptr addrspace(8) inreg %buf) {
define void @store_i40(i40 %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_i40(
-; CHECK-SAME: i40 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: i40 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_LEGAL:%.*]] = bitcast i40 [[DATA]] to <5 x i8>
; CHECK-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <5 x i8> [[DATA_LEGAL]], <5 x i8> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[DATA_SLICE_0_STORABLE:%.*]] = bitcast <4 x i8> [[DATA_SLICE_0]] to i32
@@ -1719,7 +1719,7 @@ define void @store_i40(i40 %data, ptr addrspace(8) inreg %buf) {
define i96 @load_i96(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define i96 @load_i96(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_LOADABLE:%.*]] = call <3 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v3i32(ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET:%.*]] = bitcast <3 x i32> [[RET_LOADABLE]] to i96
; CHECK-NEXT: ret i96 [[RET]]
@@ -1731,7 +1731,7 @@ define i96 @load_i96(ptr addrspace(8) inreg %buf) {
define void @store_i96(i96 %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_i96(
-; CHECK-SAME: i96 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: i96 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_LEGAL:%.*]] = bitcast i96 [[DATA]] to <3 x i32>
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> [[DATA_LEGAL]], ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
@@ -1743,7 +1743,7 @@ define void @store_i96(i96 %data, ptr addrspace(8) inreg %buf) {
define i160 @load_i160(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define i160 @load_i160(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_OFF_0:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i32> [[RET_OFF_0]], <4 x i32> poison, <5 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison>
; CHECK-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <5 x i32> poison, <5 x i32> [[RET_EXT_0]], <5 x i32> <i32 5, i32 6, i32 7, i32 8, i32 4>
@@ -1759,7 +1759,7 @@ define i160 @load_i160(ptr addrspace(8) inreg %buf) {
define void @store_i160(i160 %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_i160(
-; CHECK-SAME: i160 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: i160 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_LEGAL:%.*]] = bitcast i160 [[DATA]] to <5 x i32>
; CHECK-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <5 x i32> [[DATA_LEGAL]], <5 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
@@ -1774,7 +1774,7 @@ define void @store_i160(i160 %data, ptr addrspace(8) inreg %buf) {
define i256 @load_i256(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define i256 @load_i256(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_OFF_0:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i32> [[RET_OFF_0]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <8 x i32> poison, <8 x i32> [[RET_EXT_0]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
@@ -1791,7 +1791,7 @@ define i256 @load_i256(ptr addrspace(8) inreg %buf) {
define void @store_i256(i256 %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_i256(
-; CHECK-SAME: i256 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: i256 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_LEGAL:%.*]] = bitcast i256 [[DATA]] to <8 x i32>
; CHECK-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <8 x i32> [[DATA_LEGAL]], <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
@@ -1808,7 +1808,7 @@ define void @store_i256(i256 %data, ptr addrspace(8) inreg %buf) {
define i7 @load_i7(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define i7 @load_i7(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_LOADABLE:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET:%.*]] = trunc i8 [[RET_LOADABLE]] to i7
; CHECK-NEXT: ret i7 [[RET]]
@@ -1820,7 +1820,7 @@ define i7 @load_i7(ptr addrspace(8) inreg %buf) {
define void @store_i7(i7 %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_i7(
-; CHECK-SAME: i7 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: i7 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_ZEXT:%.*]] = zext i7 [[DATA]] to i8
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_ZEXT]], ptr addrspace(8) align 1 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
@@ -1832,7 +1832,7 @@ define void @store_i7(i7 %data, ptr addrspace(8) inreg %buf) {
define i4 @load_i4(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define i4 @load_i4(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_LOADABLE:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET:%.*]] = trunc i8 [[RET_LOADABLE]] to i4
; CHECK-NEXT: ret i4 [[RET]]
@@ -1844,7 +1844,7 @@ define i4 @load_i4(ptr addrspace(8) inreg %buf) {
define void @store_i4(i4 %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_i4(
-; CHECK-SAME: i4 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: i4 [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_ZEXT:%.*]] = zext i4 [[DATA]] to i8
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_ZEXT]], ptr addrspace(8) align 1 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
@@ -1858,7 +1858,7 @@ define void @store_i4(i4 %data, ptr addrspace(8) inreg %buf) {
define <2 x i4> @load_v2i4(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <2 x i4> @load_v2i4(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_LOADABLE:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET:%.*]] = bitcast i8 [[RET_LOADABLE]] to <2 x i4>
; CHECK-NEXT: ret <2 x i4> [[RET]]
@@ -1870,7 +1870,7 @@ define <2 x i4> @load_v2i4(ptr addrspace(8) inreg %buf) {
define void @store_v2i4(<2 x i4> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v2i4(
-; CHECK-SAME: <2 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <2 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_LEGAL:%.*]] = bitcast <2 x i4> [[DATA]] to i8
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA_LEGAL]], ptr addrspace(8) align 1 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
@@ -1882,7 +1882,7 @@ define void @store_v2i4(<2 x i4> %data, ptr addrspace(8) inreg %buf) {
define <4 x i4> @load_v4i4(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <4 x i4> @load_v4i4(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_LOADABLE:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET:%.*]] = bitcast i16 [[RET_LOADABLE]] to <4 x i4>
; CHECK-NEXT: ret <4 x i4> [[RET]]
@@ -1894,7 +1894,7 @@ define <4 x i4> @load_v4i4(ptr addrspace(8) inreg %buf) {
define void @store_v4i4(<4 x i4> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v4i4(
-; CHECK-SAME: <4 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <4 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_LEGAL:%.*]] = bitcast <4 x i4> [[DATA]] to i16
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_LEGAL]], ptr addrspace(8) align 2 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
@@ -1906,7 +1906,7 @@ define void @store_v4i4(<4 x i4> %data, ptr addrspace(8) inreg %buf) {
define <8 x i4> @load_v8i4(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <8 x i4> @load_v8i4(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_LOADABLE:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET:%.*]] = bitcast i32 [[RET_LOADABLE]] to <8 x i4>
; CHECK-NEXT: ret <8 x i4> [[RET]]
@@ -1918,7 +1918,7 @@ define <8 x i4> @load_v8i4(ptr addrspace(8) inreg %buf) {
define void @store_v8i4(<8 x i4> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v8i4(
-; CHECK-SAME: <8 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <8 x i4> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_LEGAL:%.*]] = bitcast <8 x i4> [[DATA]] to i32
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_LEGAL]], ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
@@ -1932,7 +1932,7 @@ define void @store_v8i4(<8 x i4> %data, ptr addrspace(8) inreg %buf) {
define <2 x i6> @load_v2i6(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <2 x i6> @load_v2i6(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_LOADABLE:%.*]] = call i16 @llvm.amdgcn.raw.ptr.buffer.load.i16(ptr addrspace(8) align 2 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET_TRUNC:%.*]] = trunc i16 [[RET_LOADABLE]] to i12
; CHECK-NEXT: [[RET:%.*]] = bitcast i12 [[RET_TRUNC]] to <2 x i6>
@@ -1945,7 +1945,7 @@ define <2 x i6> @load_v2i6(ptr addrspace(8) inreg %buf) {
define void @store_v2i6(<2 x i6> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v2i6(
-; CHECK-SAME: <2 x i6> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <2 x i6> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_AS_SCALAR:%.*]] = bitcast <2 x i6> [[DATA]] to i12
; CHECK-NEXT: [[DATA_ZEXT:%.*]] = zext i12 [[DATA_AS_SCALAR]] to i16
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 [[DATA_ZEXT]], ptr addrspace(8) align 2 [[BUF]], i32 0, i32 0, i32 0)
@@ -1959,7 +1959,7 @@ define void @store_v2i6(<2 x i6> %data, ptr addrspace(8) inreg %buf) {
;; Blocks of fp6 elements
define <6 x i32> @load_v32i6(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <6 x i32> @load_v32i6(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_OFF_0:%.*]] = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v4i32(ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET_EXT_0:%.*]] = shufflevector <4 x i32> [[RET_OFF_0]], <4 x i32> poison, <6 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison>
; CHECK-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <6 x i32> poison, <6 x i32> [[RET_EXT_0]], <6 x i32> <i32 6, i32 7, i32 8, i32 9, i32 4, i32 5>
@@ -1978,7 +1978,7 @@ define <6 x i32> @load_v32i6(ptr addrspace(8) inreg %buf) {
define void @store_v32i6(<6 x i32> %data.abi, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_v32i6(
-; CHECK-SAME: <6 x i32> [[DATA_ABI:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <6 x i32> [[DATA_ABI:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA:%.*]] = bitcast <6 x i32> [[DATA_ABI]] to <32 x i6>
; CHECK-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <6 x i32> [[DATA_ABI]], <6 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[DATA_SLICE_0]], ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
@@ -1996,7 +1996,7 @@ define void @store_v32i6(<6 x i32> %data.abi, ptr addrspace(8) inreg %buf) {
define <4 x i8> @volatile_load_v4i8(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <4 x i8> @volatile_load_v4i8(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_LOADABLE:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 -2147483648)
; CHECK-NEXT: [[RET:%.*]] = bitcast i32 [[RET_LOADABLE]] to <4 x i8>
; CHECK-NEXT: ret <4 x i8> [[RET]]
@@ -2008,7 +2008,7 @@ define <4 x i8> @volatile_load_v4i8(ptr addrspace(8) inreg %buf) {
define void @volatile_store_v4i8(<4 x i8> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @volatile_store_v4i8(
-; CHECK-SAME: <4 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <4 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_LEGAL:%.*]] = bitcast <4 x i8> [[DATA]] to i32
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_LEGAL]], ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 -2147483648)
; CHECK-NEXT: ret void
@@ -2020,7 +2020,7 @@ define void @volatile_store_v4i8(<4 x i8> %data, ptr addrspace(8) inreg %buf) {
define <6 x i8> @volatile_load_v6i8(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <6 x i8> @volatile_load_v6i8(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_OFF_0:%.*]] = call <2 x i16> @llvm.amdgcn.raw.ptr.buffer.load.v2i16(ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 -2147483648)
; CHECK-NEXT: [[RET_EXT_0:%.*]] = shufflevector <2 x i16> [[RET_OFF_0]], <2 x i16> poison, <3 x i32> <i32 0, i32 1, i32 poison>
; CHECK-NEXT: [[RET_PARTS_0:%.*]] = shufflevector <3 x i16> poison, <3 x i16> [[RET_EXT_0]], <3 x i32> <i32 3, i32 4, i32 2>
@@ -2036,7 +2036,7 @@ define <6 x i8> @volatile_load_v6i8(ptr addrspace(8) inreg %buf) {
define void @volatile_store_v6i8(<6 x i8> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @volatile_store_v6i8(
-; CHECK-SAME: <6 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <6 x i8> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_LEGAL:%.*]] = bitcast <6 x i8> [[DATA]] to <3 x i16>
; CHECK-NEXT: [[DATA_SLICE_0:%.*]] = shufflevector <3 x i16> [[DATA_LEGAL]], <3 x i16> poison, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i16(<2 x i16> [[DATA_SLICE_0]], ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 -2147483648)
@@ -2051,7 +2051,7 @@ define void @volatile_store_v6i8(<6 x i8> %data, ptr addrspace(8) inreg %buf) {
define [2 x [2 x i32]] @load_a2a2i32(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define [2 x [2 x i32]] @load_a2a2i32(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET0_OFF_0:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET0_OFF_1:%.*]] = extractelement <2 x i32> [[RET0_OFF_0]], i64 0
; CHECK-NEXT: [[RET0_AS_ARRAY_0:%.*]] = insertvalue [2 x i32] poison, i32 [[RET0_OFF_1]], 0
@@ -2073,7 +2073,7 @@ define [2 x [2 x i32]] @load_a2a2i32(ptr addrspace(8) inreg %buf) {
define void @store_a2a2i32([2 x [2 x i32]] %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_a2a2i32(
-; CHECK-SAME: [2 x [2 x i32]] [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: [2 x [2 x i32]] [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA0:%.*]] = extractvalue [2 x [2 x i32]] [[DATA]], 0
; CHECK-NEXT: [[DATA0_ELEM_0:%.*]] = extractvalue [2 x i32] [[DATA0]], 0
; CHECK-NEXT: [[DATA0_AS_VEC_0:%.*]] = insertelement <2 x i32> poison, i32 [[DATA0_ELEM_0]], i64 0
@@ -2095,7 +2095,7 @@ define void @store_a2a2i32([2 x [2 x i32]] %data, ptr addrspace(8) inreg %buf) {
define [2 x <2 x i32>] @load_a2v2i32(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define [2 x <2 x i32>] @load_a2v2i32(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET0_OFF_0:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET0:%.*]] = insertvalue [2 x <2 x i32>] poison, <2 x i32> [[RET0_OFF_0]], 0
; CHECK-NEXT: [[RET1_OFF_8:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 8, i32 0, i32 0)
@@ -2109,7 +2109,7 @@ define [2 x <2 x i32>] @load_a2v2i32(ptr addrspace(8) inreg %buf) {
define void @store_a2v2i32([2 x <2 x i32>] %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_a2v2i32(
-; CHECK-SAME: [2 x <2 x i32>] [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: [2 x <2 x i32>] [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA0:%.*]] = extractvalue [2 x <2 x i32>] [[DATA]], 0
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA0]], ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[DATA1:%.*]] = extractvalue [2 x <2 x i32>] [[DATA]], 1
@@ -2123,7 +2123,7 @@ define void @store_a2v2i32([2 x <2 x i32>] %data, ptr addrspace(8) inreg %buf) {
define [2 x <3 x i32>] @load_a2v3i32(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define [2 x <3 x i32>] @load_a2v3i32(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET0_OFF_0:%.*]] = call <3 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v3i32(ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET0:%.*]] = insertvalue [2 x <3 x i32>] poison, <3 x i32> [[RET0_OFF_0]], 0
; CHECK-NEXT: [[RET1_OFF_16:%.*]] = call <3 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v3i32(ptr addrspace(8) align 16 [[BUF]], i32 16, i32 0, i32 0)
@@ -2137,7 +2137,7 @@ define [2 x <3 x i32>] @load_a2v3i32(ptr addrspace(8) inreg %buf) {
define void @store_a2v3i32([2 x <3 x i32>] %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_a2v3i32(
-; CHECK-SAME: [2 x <3 x i32>] [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: [2 x <3 x i32>] [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA0:%.*]] = extractvalue [2 x <3 x i32>] [[DATA]], 0
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> [[DATA0]], ptr addrspace(8) align 16 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[DATA1:%.*]] = extractvalue [2 x <3 x i32>] [[DATA]], 1
@@ -2151,7 +2151,7 @@ define void @store_a2v3i32([2 x <3 x i32>] %data, ptr addrspace(8) inreg %buf) {
define { i32 } @load_sl_i32s(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define { i32 } @load_sl_i32s(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_0_OFF_0:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET:%.*]] = insertvalue { i32 } poison, i32 [[RET_0_OFF_0]], 0
; CHECK-NEXT: ret { i32 } [[RET]]
@@ -2163,7 +2163,7 @@ define { i32 } @load_sl_i32s(ptr addrspace(8) inreg %buf) {
define void @store_sl_i32s({ i32 } %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_sl_i32s(
-; CHECK-SAME: { i32 } [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: { i32 } [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_0:%.*]] = extractvalue { i32 } [[DATA]], 0
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[DATA_0]], ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
@@ -2175,7 +2175,7 @@ define void @store_sl_i32s({ i32 } %data, ptr addrspace(8) inreg %buf) {
define { { float } } @load_sl_sl_f32ss(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define { { float } } @load_sl_sl_f32ss(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_0_0_OFF_0:%.*]] = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET:%.*]] = insertvalue { { float } } poison, float [[RET_0_0_OFF_0]], 0, 0
; CHECK-NEXT: ret { { float } } [[RET]]
@@ -2187,7 +2187,7 @@ define { { float } } @load_sl_sl_f32ss(ptr addrspace(8) inreg %buf) {
define void @store_sl_sl_f32ss({ { float } } %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_sl_sl_f32ss(
-; CHECK-SAME: { { float } } [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: { { float } } [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_0_0:%.*]] = extractvalue { { float } } [[DATA]], 0, 0
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float [[DATA_0_0]], ptr addrspace(8) align 4 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
@@ -2199,7 +2199,7 @@ define void @store_sl_sl_f32ss({ { float } } %data, ptr addrspace(8) inreg %buf)
define { <2 x i32> } @load_sl_v2i32s(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define { <2 x i32> } @load_sl_v2i32s(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_0_OFF_0:%.*]] = call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET:%.*]] = insertvalue { <2 x i32> } poison, <2 x i32> [[RET_0_OFF_0]], 0
; CHECK-NEXT: ret { <2 x i32> } [[RET]]
@@ -2211,7 +2211,7 @@ define { <2 x i32> } @load_sl_v2i32s(ptr addrspace(8) inreg %buf) {
define void @store_sl_v2i32s({ <2 x i32> } %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_sl_v2i32s(
-; CHECK-SAME: { <2 x i32> } [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: { <2 x i32> } [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_0:%.*]] = extractvalue { <2 x i32> } [[DATA]], 0
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v2i32(<2 x i32> [[DATA_0]], ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
@@ -2223,7 +2223,7 @@ define void @store_sl_v2i32s({ <2 x i32> } %data, ptr addrspace(8) inreg %buf) {
define { i64, i32 } @load_sl_i64i32s(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define { i64, i32 } @load_sl_i64i32s(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET_0_OFF_0:%.*]] = call i64 @llvm.amdgcn.raw.ptr.buffer.load.i64(ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET_0:%.*]] = insertvalue { i64, i32 } poison, i64 [[RET_0_OFF_0]], 0
; CHECK-NEXT: [[RET_1_OFF_8:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) align 8 [[BUF]], i32 8, i32 0, i32 0)
@@ -2237,7 +2237,7 @@ define { i64, i32 } @load_sl_i64i32s(ptr addrspace(8) inreg %buf) {
define void @store_sl_i64i32s({ i64, i32 } %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_sl_i64i32s(
-; CHECK-SAME: { i64, i32 } [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: { i64, i32 } [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA_0:%.*]] = extractvalue { i64, i32 } [[DATA]], 0
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i64(i64 [[DATA_0]], ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[DATA_1:%.*]] = extractvalue { i64, i32 } [[DATA]], 1
@@ -2251,7 +2251,7 @@ define void @store_sl_i64i32s({ i64, i32 } %data, ptr addrspace(8) inreg %buf) {
define [4 x i7] @load_a4i7(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define [4 x i7] @load_a4i7(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET0_OFF_0:%.*]] = call i8 @llvm.amdgcn.raw.ptr.buffer.load.i8(ptr addrspace(8) align 1 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: [[RET0_TRUNC:%.*]] = trunc i8 [[RET0_OFF_0]] to i7
; CHECK-NEXT: [[RET0:%.*]] = insertvalue [4 x i7] poison, i7 [[RET0_TRUNC]], 0
@@ -2273,7 +2273,7 @@ define [4 x i7] @load_a4i7(ptr addrspace(8) inreg %buf) {
define void @store_a4i7([4 x i7] %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_a4i7(
-; CHECK-SAME: [4 x i7] [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: [4 x i7] [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[DATA0:%.*]] = extractvalue [4 x i7] [[DATA]], 0
; CHECK-NEXT: [[DATA0_ZEXT:%.*]] = zext i7 [[DATA0]] to i8
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 [[DATA0_ZEXT]], ptr addrspace(8) align 1 [[BUF]], i32 0, i32 0, i32 0)
@@ -2297,7 +2297,7 @@ define void @store_a4i7([4 x i7] %data, ptr addrspace(8) inreg %buf) {
define <vscale x 2 x i32> @load_nxv2i32(ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define <vscale x 2 x i32> @load_nxv2i32(
-; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call <vscale x 2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.nxv2i32(ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret <vscale x 2 x i32> [[RET]]
;
@@ -2308,7 +2308,7 @@ define <vscale x 2 x i32> @load_nxv2i32(ptr addrspace(8) inreg %buf) {
define void @store_nxv2i32(<vscale x 2 x i32> %data, ptr addrspace(8) inreg %buf) {
; CHECK-LABEL: define void @store_nxv2i32(
-; CHECK-SAME: <vscale x 2 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: <vscale x 2 x i32> [[DATA:%.*]], ptr addrspace(8) inreg [[BUF:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.nxv2i32(<vscale x 2 x i32> [[DATA]], ptr addrspace(8) align 8 [[BUF]], i32 0, i32 0, i32 0)
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-control-flow.ll b/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-control-flow.ll
index 71005224dd1e5..b7dda33b6646c 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-control-flow.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-control-flow.ll
@@ -1,13 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
-; RUN: opt -S -mcpu=gfx900 -amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
-; RUN: opt -S -mcpu=gfx900 -passes=amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
+; RUN: opt -S -amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
+; RUN: opt -S -passes=amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
-target triple = "amdgcn--"
+target triple = "amdgpu9.00--"
;; This should optimize to just the offset part
define float @sum(ptr addrspace(8) %buf, i32 %len) {
; CHECK-LABEL: define float @sum
-; CHECK-SAME: (ptr addrspace(8) [[BUF:%.*]], i32 [[LEN:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-SAME: (ptr addrspace(8) [[BUF:%.*]], i32 [[LEN:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
@@ -45,7 +45,7 @@ exit:
;; But this should not
define float @sum_integer_ops(ptr addrspace(8) %buf, i32 %len) {
; CHECK-LABEL: define float @sum_integer_ops
-; CHECK-SAME: (ptr addrspace(8) [[BUF:%.*]], i32 [[LEN:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: (ptr addrspace(8) [[BUF:%.*]], i32 [[LEN:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
@@ -94,7 +94,7 @@ exit:
;; Should go to offsets only
define float @sum_2d(ptr addrspace(8) %buf, i32 %ii, i32 %jj) {
; CHECK-LABEL: define float @sum_2d
-; CHECK-SAME: (ptr addrspace(8) [[BUF:%.*]], i32 [[II:%.*]], i32 [[JJ:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: (ptr addrspace(8) [[BUF:%.*]], i32 [[II:%.*]], i32 [[JJ:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP1_ENTRY:%.*]]
; CHECK: loop1.entry:
@@ -155,7 +155,7 @@ exit:
;; select point to the same buffer.
define float @sum_jump_on_negative(ptr addrspace(8) %buf, i32 %len) {
; CHECK-LABEL: define float @sum_jump_on_negative
-; CHECK-SAME: (ptr addrspace(8) [[BUF:%.*]], i32 [[LEN:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: (ptr addrspace(8) [[BUF:%.*]], i32 [[LEN:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
@@ -199,7 +199,7 @@ exit:
define float @sum_jump_on_negative_with_phi(ptr addrspace(8) %buf, i32 %len) {
; CHECK-LABEL: define float @sum_jump_on_negative_with_phi
-; CHECK-SAME: (ptr addrspace(8) [[BUF:%.*]], i32 [[LEN:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: (ptr addrspace(8) [[BUF:%.*]], i32 [[LEN:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
@@ -256,7 +256,7 @@ exit:
;; But this has a shifting resource part.
define float @sum_new_buffer_on_negative(ptr addrspace(8) %buf1, ptr addrspace(8) %buf2, i32 %len) {
; CHECK-LABEL: define float @sum_new_buffer_on_negative
-; CHECK-SAME: (ptr addrspace(8) [[BUF1:%.*]], ptr addrspace(8) [[BUF2:%.*]], i32 [[LEN:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: (ptr addrspace(8) [[BUF1:%.*]], ptr addrspace(8) [[BUF2:%.*]], i32 [[LEN:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
@@ -302,7 +302,7 @@ exit:
;; As does this.
define float @sum_new_buffer_on_negative_with_phi(ptr addrspace(8) %buf1, ptr addrspace(8) %buf2, i32 %len) {
; CHECK-LABEL: define float @sum_new_buffer_on_negative_with_phi
-; CHECK-SAME: (ptr addrspace(8) [[BUF1:%.*]], ptr addrspace(8) [[BUF2:%.*]], i32 [[LEN:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: (ptr addrspace(8) [[BUF1:%.*]], ptr addrspace(8) [[BUF2:%.*]], i32 [[LEN:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
@@ -356,7 +356,7 @@ exit:
;; nodes that repeat the same predecessor multiple times.
define float @sum_duplicate_preds(ptr addrspace(8) %buf, i32 %len) {
; CHECK-LABEL: define float @sum_duplicate_preds
-; CHECK-SAME: (ptr addrspace(8) [[BUF:%.*]], i32 [[LEN:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: (ptr addrspace(8) [[BUF:%.*]], i32 [[LEN:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
@@ -402,7 +402,7 @@ exit:
;; And similirly check the "might not be uniform" case.
define float @sum_integer_ops_duplicate_preds(ptr addrspace(8) %buf, i32 %len) {
; CHECK-LABEL: define float @sum_integer_ops_duplicate_preds
-; CHECK-SAME: (ptr addrspace(8) [[BUF:%.*]], i32 [[LEN:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: (ptr addrspace(8) [[BUF:%.*]], i32 [[LEN:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
@@ -458,7 +458,7 @@ exit:
define void @dominance_not_in_program_order(ptr addrspace(7) inreg %arg) {
; CHECK-LABEL: define void @dominance_not_in_program_order
-; CHECK-SAME: ({ ptr addrspace(8), i32 } inreg [[ARG:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } inreg [[ARG:%.*]]) {
; CHECK-NEXT: .preheader15:
; CHECK-NEXT: [[ARG_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[ARG]], 0
; CHECK-NEXT: [[ARG_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[ARG]], 1
@@ -485,7 +485,7 @@ define void @dominance_not_in_program_order(ptr addrspace(7) inreg %arg) {
;; iree-org/iree#22551 - crash on something that reduces to the below non-canonical select.
define ptr addrspace(7) @noncanonical_const_cond(ptr addrspace(7) %x) {
; CHECK-LABEL: define { ptr addrspace(8), i32 } @noncanonical_const_cond
-; CHECK-SAME: ({ ptr addrspace(8), i32 } [[RET:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } [[RET:%.*]]) {
; CHECK-NEXT: [[X_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[RET]], 0
; CHECK-NEXT: [[X_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[RET]], 1
; CHECK-NEXT: ret { ptr addrspace(8), i32 } [[RET]]
diff --git a/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-mem-transfer.ll b/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-mem-transfer.ll
index 297174f41e75e..ddccc4c4f59cd 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-mem-transfer.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-mem-transfer.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
-; RUN: opt -S -mcpu=gfx900 -mattr=+unaligned-access-mode -amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
-; RUN: opt -S -mcpu=gfx900 -mattr=+unaligned-access-mode -passes=amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
+; RUN: opt -S -mattr=+unaligned-access-mode -amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
+; RUN: opt -S -mattr=+unaligned-access-mode -passes=amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
-target triple = "amdgcn--"
+target triple = "amdgpu9.00--"
;; memcpy
diff --git a/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-memops.ll b/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-memops.ll
index 756a6af4ccbcd..74735529d723d 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-memops.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-memops.ll
@@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
-; RUN: opt -S -mcpu=gfx900 -amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
-; RUN: opt -S -mcpu=gfx900 -passes=amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
+; RUN: opt -S -amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
+; RUN: opt -S -passes=amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
-target triple = "amdgcn--"
+target triple = "amdgpu9.00--"
define void @loads(ptr addrspace(8) %buf) {
; CHECK-LABEL: define void @loads
-; CHECK-SAME: (ptr addrspace(8) [[BUF:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-SAME: (ptr addrspace(8) [[BUF:%.*]]) {
; CHECK-NEXT: [[SCALAR:%.*]] = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) align 4 [[BUF]], i32 16, i32 0, i32 0)
; CHECK-NEXT: [[VEC2:%.*]] = call <2 x float> @llvm.amdgcn.raw.ptr.buffer.load.v2f32(ptr addrspace(8) align 8 [[BUF]], i32 16, i32 0, i32 0)
; CHECK-NEXT: [[VEC4:%.*]] = call <4 x float> @llvm.amdgcn.raw.ptr.buffer.load.v4f32(ptr addrspace(8) align 16 [[BUF]], i32 16, i32 0, i32 0)
@@ -46,7 +46,7 @@ define void @loads(ptr addrspace(8) %buf) {
define void @stores(ptr addrspace(8) %buf, float %f, <4 x float> %f4) {
; CHECK-LABEL: define void @stores
-; CHECK-SAME: (ptr addrspace(8) [[BUF:%.*]], float [[F:%.*]], <4 x float> [[F4:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: (ptr addrspace(8) [[BUF:%.*]], float [[F:%.*]], <4 x float> [[F4:%.*]]) {
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float [[F]], ptr addrspace(8) align 4 [[BUF]], i32 16, i32 0, i32 0)
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4f32(<4 x float> [[F4]], ptr addrspace(8) align 16 [[BUF]], i32 16, i32 0, i32 0)
; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float [[F]], ptr addrspace(8) align 4 [[BUF]], i32 16, i32 0, i32 0), !nontemporal [[META0]]
@@ -80,7 +80,7 @@ define void @stores(ptr addrspace(8) %buf, float %f, <4 x float> %f4) {
define void @atomicrmw(ptr addrspace(8) %buf, float %f, i32 %i) {
; CHECK-LABEL: define void @atomicrmw
-; CHECK-SAME: (ptr addrspace(8) [[BUF:%.*]], float [[F:%.*]], i32 [[I:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: (ptr addrspace(8) [[BUF:%.*]], float [[F:%.*]], i32 [[I:%.*]]) {
; CHECK-NEXT: fence syncscope("wavefront") release
; CHECK-NEXT: [[XCHG:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.swap.i32(i32 [[I]], ptr addrspace(8) align 4 [[BUF]], i32 16, i32 0, i32 0)
; CHECK-NEXT: fence syncscope("wavefront") acquire
@@ -152,7 +152,7 @@ define void @atomicrmw(ptr addrspace(8) %buf, float %f, i32 %i) {
define {i32, i1} @cmpxchg(ptr addrspace(8) %buf, i32 %wanted, i32 %new) {
; CHECK-LABEL: define { i32, i1 } @cmpxchg
-; CHECK-SAME: (ptr addrspace(8) [[BUF:%.*]], i32 [[WANTED:%.*]], i32 [[NEW:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: (ptr addrspace(8) [[BUF:%.*]], i32 [[WANTED:%.*]], i32 [[NEW:%.*]]) {
; CHECK-NEXT: fence syncscope("wavefront") release
; CHECK-NEXT: [[RET:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.i32(i32 [[NEW]], i32 [[WANTED]], ptr addrspace(8) align 4 [[BUF]], i32 16, i32 0, i32 -2147483648)
; CHECK-NEXT: fence syncscope("wavefront") acquire
@@ -170,7 +170,7 @@ define {i32, i1} @cmpxchg(ptr addrspace(8) %buf, i32 %wanted, i32 %new) {
define {i32, i1} @cmpxchg_weak(ptr addrspace(8) %buf, i32 %wanted, i32 %new) {
; CHECK-LABEL: define { i32, i1 } @cmpxchg_weak
-; CHECK-SAME: (ptr addrspace(8) [[BUF:%.*]], i32 [[WANTED:%.*]], i32 [[NEW:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: (ptr addrspace(8) [[BUF:%.*]], i32 [[WANTED:%.*]], i32 [[NEW:%.*]]) {
; CHECK-NEXT: fence syncscope("wavefront") release
; CHECK-NEXT: [[RET:%.*]] = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.i32(i32 [[NEW]], i32 [[WANTED]], ptr addrspace(8) align 4 [[BUF]], i32 16, i32 0, i32 0)
; CHECK-NEXT: fence syncscope("wavefront") acquire
diff --git a/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-p7-in-memory.ll b/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-p7-in-memory.ll
index 0edc563b29ec9..497f99903e266 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-p7-in-memory.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-p7-in-memory.ll
@@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
-; RUN: opt -S -mcpu=gfx900 -amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
-; RUN: opt -S -mcpu=gfx900 -passes=amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
+; RUN: opt -S -amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
+; RUN: opt -S -passes=amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
-target triple = "amdgcn--"
+target triple = "amdgpu9.00--"
define void @scalar_copy(ptr %a, ptr %b) {
; CHECK-LABEL: define void @scalar_copy
-; CHECK-SAME: (ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-SAME: (ptr [[A:%.*]], ptr [[B:%.*]]) {
; CHECK-NEXT: [[X:%.*]] = load i160, ptr [[A]], align 32
; CHECK-NEXT: [[TMP1:%.*]] = lshr i160 [[X]], 32
; CHECK-NEXT: [[TMP2:%.*]] = trunc i160 [[TMP1]] to i128
@@ -24,7 +24,7 @@ define void @scalar_copy(ptr %a, ptr %b) {
define void @vector_copy(ptr %a, ptr %b) {
; CHECK-LABEL: define void @vector_copy
-; CHECK-SAME: (ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: (ptr [[A:%.*]], ptr [[B:%.*]]) {
; CHECK-NEXT: [[X:%.*]] = load <4 x i160>, ptr [[A]], align 128
; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i160> [[X]], splat (i160 32)
; CHECK-NEXT: [[TMP2:%.*]] = trunc <4 x i160> [[TMP1]] to <4 x i128>
@@ -42,7 +42,7 @@ define void @vector_copy(ptr %a, ptr %b) {
define void @alloca(ptr %a, ptr %b) {
; CHECK-LABEL: define void @alloca
-; CHECK-SAME: (ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: (ptr [[A:%.*]], ptr [[B:%.*]]) {
; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [5 x i160], align 32, addrspace(5)
; CHECK-NEXT: [[X:%.*]] = load i160, ptr [[A]], align 32
; CHECK-NEXT: [[TMP1:%.*]] = lshr i160 [[X]], 32
@@ -70,7 +70,7 @@ define void @alloca(ptr %a, ptr %b) {
define void @complex_copy(ptr %a, ptr %b) {
; CHECK-LABEL: define void @complex_copy
-; CHECK-SAME: (ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: (ptr [[A:%.*]], ptr [[B:%.*]]) {
; CHECK-NEXT: [[X:%.*]] = load { [2 x i160], i32, i160 }, ptr [[A]], align 32
; CHECK-NEXT: [[TMP1:%.*]] = extractvalue { [2 x i160], i32, i160 } [[X]], 0
; CHECK-NEXT: [[TMP2:%.*]] = extractvalue [2 x i160] [[TMP1]], 0
diff --git a/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-pointer-ops.ll b/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-pointer-ops.ll
index 01d2c1c356cb5..dca94fd7db941 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-pointer-ops.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-pointer-ops.ll
@@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
-; RUN: opt -S -mcpu=gfx900 -amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
-; RUN: opt -S -mcpu=gfx900 -passes=amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
+; RUN: opt -S -amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
+; RUN: opt -S -passes=amdgpu-lower-buffer-fat-pointers < %s | FileCheck %s
-target triple = "amdgcn--"
+target triple = "amdgpu9.00--"
define ptr addrspace(7) @gep(ptr addrspace(7) %in, i32 %idx) {
; CHECK-LABEL: define { ptr addrspace(8), i32 } @gep
-; CHECK-SAME: ({ ptr addrspace(8), i32 } [[IN:%.*]], i32 [[IDX:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } [[IN:%.*]], i32 [[IDX:%.*]]) {
; CHECK-NEXT: [[IN_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[IN]], 0
; CHECK-NEXT: [[IN_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[IN]], 1
; CHECK-NEXT: [[RET_IDX:%.*]] = mul nsw i32 [[IDX]], 40
@@ -22,7 +22,7 @@ define ptr addrspace(7) @gep(ptr addrspace(7) %in, i32 %idx) {
define <2 x ptr addrspace(7)> @gep_vectors(<2 x ptr addrspace(7)> %in, <2 x i32> %idx) {
; CHECK-LABEL: define { <2 x ptr addrspace(8)>, <2 x i32> } @gep_vectors
-; CHECK-SAME: ({ <2 x ptr addrspace(8)>, <2 x i32> } [[IN:%.*]], <2 x i32> [[IDX:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ <2 x ptr addrspace(8)>, <2 x i32> } [[IN:%.*]], <2 x i32> [[IDX:%.*]]) {
; CHECK-NEXT: [[IN_RSRC:%.*]] = extractvalue { <2 x ptr addrspace(8)>, <2 x i32> } [[IN]], 0
; CHECK-NEXT: [[IN_OFF:%.*]] = extractvalue { <2 x ptr addrspace(8)>, <2 x i32> } [[IN]], 1
; CHECK-NEXT: [[RET_IDX:%.*]] = mul nsw <2 x i32> [[IDX]], splat (i32 40)
@@ -38,7 +38,7 @@ define <2 x ptr addrspace(7)> @gep_vectors(<2 x ptr addrspace(7)> %in, <2 x i32>
define <2 x ptr addrspace(7)> @gep_vector_scalar(<2 x ptr addrspace(7)> %in, i64 %idx) {
; CHECK-LABEL: define { <2 x ptr addrspace(8)>, <2 x i32> } @gep_vector_scalar
-; CHECK-SAME: ({ <2 x ptr addrspace(8)>, <2 x i32> } [[IN:%.*]], i64 [[IDX:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ <2 x ptr addrspace(8)>, <2 x i32> } [[IN:%.*]], i64 [[IDX:%.*]]) {
; CHECK-NEXT: [[IN_RSRC:%.*]] = extractvalue { <2 x ptr addrspace(8)>, <2 x i32> } [[IN]], 0
; CHECK-NEXT: [[IN_OFF:%.*]] = extractvalue { <2 x ptr addrspace(8)>, <2 x i32> } [[IN]], 1
; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <2 x i64> poison, i64 [[IDX]], i64 0
@@ -57,7 +57,7 @@ define <2 x ptr addrspace(7)> @gep_vector_scalar(<2 x ptr addrspace(7)> %in, i64
define <2 x ptr addrspace(7)> @gep_scalar_vector(ptr addrspace(7) %in, <2 x i32> %idxs) {
; CHECK-LABEL: define { <2 x ptr addrspace(8)>, <2 x i32> } @gep_scalar_vector
-; CHECK-SAME: ({ ptr addrspace(8), i32 } [[IN:%.*]], <2 x i32> [[IDXS:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } [[IN:%.*]], <2 x i32> [[IDXS:%.*]]) {
; CHECK-NEXT: [[IN_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[IN]], 0
; CHECK-NEXT: [[IN_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[IN]], 1
; CHECK-NEXT: [[IN_RSRC_SPLATINSERT:%.*]] = insertelement <2 x ptr addrspace(8)> poison, ptr addrspace(8) [[IN_RSRC]], i64 0
@@ -75,7 +75,7 @@ define <2 x ptr addrspace(7)> @gep_scalar_vector(ptr addrspace(7) %in, <2 x i32>
define ptr addrspace(7) @simple_gep(ptr addrspace(7) %ptr, i32 %off) {
; CHECK-LABEL: define { ptr addrspace(8), i32 } @simple_gep
-; CHECK-SAME: ({ ptr addrspace(8), i32 } [[PTR:%.*]], i32 [[OFF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } [[PTR:%.*]], i32 [[OFF:%.*]]) {
; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 0
; CHECK-NEXT: [[PTR_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 1
; CHECK-NEXT: [[RET_IDX:%.*]] = mul i32 [[OFF]], 4
@@ -89,7 +89,7 @@ define ptr addrspace(7) @simple_gep(ptr addrspace(7) %ptr, i32 %off) {
define ptr addrspace(7) @simple_inbounds_gep(ptr addrspace(7) %ptr, i32 %off) {
; CHECK-LABEL: define { ptr addrspace(8), i32 } @simple_inbounds_gep
-; CHECK-SAME: ({ ptr addrspace(8), i32 } [[PTR:%.*]], i32 [[OFF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } [[PTR:%.*]], i32 [[OFF:%.*]]) {
; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 0
; CHECK-NEXT: [[PTR_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 1
; CHECK-NEXT: [[RET_IDX:%.*]] = mul nsw i32 [[OFF]], 4
@@ -103,7 +103,7 @@ define ptr addrspace(7) @simple_inbounds_gep(ptr addrspace(7) %ptr, i32 %off) {
define ptr addrspace(7) @simple_nuw_gep(ptr addrspace(7) %ptr, i32 %off) {
; CHECK-LABEL: define { ptr addrspace(8), i32 } @simple_nuw_gep
-; CHECK-SAME: ({ ptr addrspace(8), i32 } [[PTR:%.*]], i32 [[OFF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } [[PTR:%.*]], i32 [[OFF:%.*]]) {
; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 0
; CHECK-NEXT: [[PTR_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 1
; CHECK-NEXT: [[RET_IDX:%.*]] = mul nuw i32 [[OFF]], 4
@@ -117,7 +117,7 @@ define ptr addrspace(7) @simple_nuw_gep(ptr addrspace(7) %ptr, i32 %off) {
define ptr addrspace(7) @simple_nusw_gep(ptr addrspace(7) %ptr, i32 %off) {
; CHECK-LABEL: define { ptr addrspace(8), i32 } @simple_nusw_gep
-; CHECK-SAME: ({ ptr addrspace(8), i32 } [[PTR:%.*]], i32 [[OFF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } [[PTR:%.*]], i32 [[OFF:%.*]]) {
; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 0
; CHECK-NEXT: [[PTR_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 1
; CHECK-NEXT: [[RET_IDX:%.*]] = mul nsw i32 [[OFF]], 4
@@ -131,7 +131,7 @@ define ptr addrspace(7) @simple_nusw_gep(ptr addrspace(7) %ptr, i32 %off) {
define ptr addrspace(7) @nusw_gep_pair(ptr addrspace(7) %ptr, i32 %off) {
; CHECK-LABEL: define { ptr addrspace(8), i32 } @nusw_gep_pair
-; CHECK-SAME: ({ ptr addrspace(8), i32 } [[PTR:%.*]], i32 [[OFF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } [[PTR:%.*]], i32 [[OFF:%.*]]) {
; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 0
; CHECK-NEXT: [[PTR_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 1
; CHECK-NEXT: [[P1_IDX:%.*]] = mul nsw i32 [[OFF]], 4
@@ -147,7 +147,7 @@ define ptr addrspace(7) @nusw_gep_pair(ptr addrspace(7) %ptr, i32 %off) {
define ptr addrspace(7) @zero_gep(ptr addrspace(7) %ptr) {
; CHECK-LABEL: define { ptr addrspace(8), i32 } @zero_gep
-; CHECK-SAME: ({ ptr addrspace(8), i32 } [[RET:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } [[RET:%.*]]) {
; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[RET]], 0
; CHECK-NEXT: [[PTR_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[RET]], 1
; CHECK-NEXT: ret { ptr addrspace(8), i32 } [[RET]]
@@ -158,7 +158,7 @@ define ptr addrspace(7) @zero_gep(ptr addrspace(7) %ptr) {
define ptr addrspace(7) @zero_gep_goes_second(ptr addrspace(7) %v0, i32 %arg) {
; CHECK-LABEL: define { ptr addrspace(8), i32 } @zero_gep_goes_second
-; CHECK-SAME: ({ ptr addrspace(8), i32 } [[V0:%.*]], i32 [[ARG:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } [[V0:%.*]], i32 [[ARG:%.*]]) {
; CHECK-NEXT: [[V0_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[V0]], 0
; CHECK-NEXT: [[V0_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[V0]], 1
; CHECK-NEXT: [[V1:%.*]] = add i32 [[V0_OFF]], [[ARG]]
@@ -172,7 +172,7 @@ define ptr addrspace(7) @zero_gep_goes_second(ptr addrspace(7) %v0, i32 %arg) {
define ptr addrspace(7) @zero_gep_goes_first(ptr addrspace(7) %v0, i32 %arg) {
; CHECK-LABEL: define { ptr addrspace(8), i32 } @zero_gep_goes_first
-; CHECK-SAME: ({ ptr addrspace(8), i32 } [[V0:%.*]], i32 [[ARG:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } [[V0:%.*]], i32 [[ARG:%.*]]) {
; CHECK-NEXT: [[V0_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[V0]], 0
; CHECK-NEXT: [[V0_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[V0]], 1
; CHECK-NEXT: [[V2:%.*]] = add i32 [[V0_OFF]], [[ARG]]
@@ -186,7 +186,7 @@ define ptr addrspace(7) @zero_gep_goes_first(ptr addrspace(7) %v0, i32 %arg) {
define i160 @ptrtoint(ptr addrspace(7) %ptr) {
; CHECK-LABEL: define i160 @ptrtoint
-; CHECK-SAME: ({ ptr addrspace(8), i32 } [[PTR:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } [[PTR:%.*]]) {
; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 0
; CHECK-NEXT: [[PTR_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 1
; CHECK-NEXT: [[RET_RSRC:%.*]] = ptrtoint ptr addrspace(8) [[PTR_RSRC]] to i160
@@ -201,7 +201,7 @@ define i160 @ptrtoint(ptr addrspace(7) %ptr) {
define <2 x i160> @ptrtoint_vec(<2 x ptr addrspace(7)> %ptr) {
; CHECK-LABEL: define <2 x i160> @ptrtoint_vec
-; CHECK-SAME: ({ <2 x ptr addrspace(8)>, <2 x i32> } [[PTR:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ <2 x ptr addrspace(8)>, <2 x i32> } [[PTR:%.*]]) {
; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { <2 x ptr addrspace(8)>, <2 x i32> } [[PTR]], 0
; CHECK-NEXT: [[PTR_OFF:%.*]] = extractvalue { <2 x ptr addrspace(8)>, <2 x i32> } [[PTR]], 1
; CHECK-NEXT: [[RET_RSRC:%.*]] = ptrtoint <2 x ptr addrspace(8)> [[PTR_RSRC]] to <2 x i160>
@@ -216,7 +216,7 @@ define <2 x i160> @ptrtoint_vec(<2 x ptr addrspace(7)> %ptr) {
define i256 @ptrtoint_long(ptr addrspace(7) %ptr) {
; CHECK-LABEL: define i256 @ptrtoint_long
-; CHECK-SAME: ({ ptr addrspace(8), i32 } [[PTR:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } [[PTR:%.*]]) {
; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 0
; CHECK-NEXT: [[PTR_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 1
; CHECK-NEXT: [[RET_RSRC:%.*]] = ptrtoint ptr addrspace(8) [[PTR_RSRC]] to i256
@@ -231,7 +231,7 @@ define i256 @ptrtoint_long(ptr addrspace(7) %ptr) {
define i64 @ptrtoint_short(ptr addrspace(7) %ptr) {
; CHECK-LABEL: define i64 @ptrtoint_short
-; CHECK-SAME: ({ ptr addrspace(8), i32 } [[PTR:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } [[PTR:%.*]]) {
; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 0
; CHECK-NEXT: [[PTR_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 1
; CHECK-NEXT: [[RET_RSRC:%.*]] = ptrtoint ptr addrspace(8) [[PTR_RSRC]] to i64
@@ -246,7 +246,7 @@ define i64 @ptrtoint_short(ptr addrspace(7) %ptr) {
define i32 @ptrtoint_offset(ptr addrspace(7) %ptr) {
; CHECK-LABEL: define i32 @ptrtoint_offset
-; CHECK-SAME: ({ ptr addrspace(8), i32 } [[PTR:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } [[PTR:%.*]]) {
; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 0
; CHECK-NEXT: [[RET:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 1
; CHECK-NEXT: ret i32 [[RET]]
@@ -257,7 +257,7 @@ define i32 @ptrtoint_offset(ptr addrspace(7) %ptr) {
define i32 @ptrtoaddr(ptr addrspace(7) %ptr) {
; CHECK-LABEL: define i32 @ptrtoaddr
-; CHECK-SAME: ({ ptr addrspace(8), i32 } [[PTR:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } [[PTR:%.*]]) {
; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 0
; CHECK-NEXT: [[RET:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 1
; CHECK-NEXT: ret i32 [[RET]]
@@ -268,7 +268,7 @@ define i32 @ptrtoaddr(ptr addrspace(7) %ptr) {
define <2 x i32> @ptrtoaddr_vec(<2 x ptr addrspace(7)> %ptr) {
; CHECK-LABEL: define <2 x i32> @ptrtoaddr_vec
-; CHECK-SAME: ({ <2 x ptr addrspace(8)>, <2 x i32> } [[PTR:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ <2 x ptr addrspace(8)>, <2 x i32> } [[PTR:%.*]]) {
; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { <2 x ptr addrspace(8)>, <2 x i32> } [[PTR]], 0
; CHECK-NEXT: [[RET:%.*]] = extractvalue { <2 x ptr addrspace(8)>, <2 x i32> } [[PTR]], 1
; CHECK-NEXT: ret <2 x i32> [[RET]]
@@ -280,7 +280,7 @@ define <2 x i32> @ptrtoaddr_vec(<2 x ptr addrspace(7)> %ptr) {
;; Check that we extend the offset to i160.
define i160 @ptrtoaddr_ext(ptr addrspace(7) %ptr) {
; CHECK-LABEL: define i160 @ptrtoaddr_ext
-; CHECK-SAME: ({ ptr addrspace(8), i32 } [[PTR:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } [[PTR:%.*]]) {
; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 0
; CHECK-NEXT: [[ADDR:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 1
; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[ADDR]] to i160
@@ -294,7 +294,7 @@ define i160 @ptrtoaddr_ext(ptr addrspace(7) %ptr) {
;; Check that we truncate the offset to i16.
define i16 @ptrtoaddr_trunc(ptr addrspace(7) %ptr) {
; CHECK-LABEL: define i16 @ptrtoaddr_trunc
-; CHECK-SAME: ({ ptr addrspace(8), i32 } [[PTR:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } [[PTR:%.*]]) {
; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 0
; CHECK-NEXT: [[ADDR:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 1
; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[ADDR]] to i16
@@ -307,7 +307,7 @@ define i16 @ptrtoaddr_trunc(ptr addrspace(7) %ptr) {
define ptr addrspace(7) @inttoptr(i160 %v) {
; CHECK-LABEL: define { ptr addrspace(8), i32 } @inttoptr
-; CHECK-SAME: (i160 [[V:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: (i160 [[V:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = lshr i160 [[V]], 32
; CHECK-NEXT: [[TMP2:%.*]] = trunc i160 [[TMP1]] to i128
; CHECK-NEXT: [[RET_RSRC:%.*]] = inttoptr i128 [[TMP2]] to ptr addrspace(8)
@@ -322,7 +322,7 @@ define ptr addrspace(7) @inttoptr(i160 %v) {
define <2 x ptr addrspace(7)> @inttoptr_vec(<2 x i160> %v) {
; CHECK-LABEL: define { <2 x ptr addrspace(8)>, <2 x i32> } @inttoptr_vec
-; CHECK-SAME: (<2 x i160> [[V:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: (<2 x i160> [[V:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i160> [[V]], splat (i160 32)
; CHECK-NEXT: [[TMP2:%.*]] = trunc <2 x i160> [[TMP1]] to <2 x i128>
; CHECK-NEXT: [[RET_RSRC:%.*]] = inttoptr <2 x i128> [[TMP2]] to <2 x ptr addrspace(8)>
@@ -337,7 +337,7 @@ define <2 x ptr addrspace(7)> @inttoptr_vec(<2 x i160> %v) {
define ptr addrspace(7) @inttoptr_long(i256 %v) {
; CHECK-LABEL: define { ptr addrspace(8), i32 } @inttoptr_long
-; CHECK-SAME: (i256 [[V:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: (i256 [[V:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = lshr i256 [[V]], 32
; CHECK-NEXT: [[TMP2:%.*]] = trunc i256 [[TMP1]] to i128
; CHECK-NEXT: [[RET_RSRC:%.*]] = inttoptr i128 [[TMP2]] to ptr addrspace(8)
@@ -352,7 +352,7 @@ define ptr addrspace(7) @inttoptr_long(i256 %v) {
define ptr addrspace(7) @inttoptr_offset(i32 %v) {
; CHECK-LABEL: define { ptr addrspace(8), i32 } @inttoptr_offset
-; CHECK-SAME: (i32 [[V:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: (i32 [[V:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = insertvalue { ptr addrspace(8), i32 } poison, i32 [[V]], 1
; CHECK-NEXT: ret { ptr addrspace(8), i32 } [[RET]]
;
@@ -362,7 +362,7 @@ define ptr addrspace(7) @inttoptr_offset(i32 %v) {
define ptr addrspace(7) @addrspacecast(ptr addrspace(8) %buf) {
; CHECK-LABEL: define { ptr addrspace(8), i32 } @addrspacecast
-; CHECK-SAME: (ptr addrspace(8) [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: (ptr addrspace(8) [[BUF:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = insertvalue { ptr addrspace(8), i32 } poison, ptr addrspace(8) [[BUF]], 0
; CHECK-NEXT: [[RET:%.*]] = insertvalue { ptr addrspace(8), i32 } [[TMP1]], i32 0, 1
; CHECK-NEXT: ret { ptr addrspace(8), i32 } [[RET]]
@@ -373,7 +373,7 @@ define ptr addrspace(7) @addrspacecast(ptr addrspace(8) %buf) {
define <2 x ptr addrspace(7)> @addrspacecast_vec(<2 x ptr addrspace(8)> %buf) {
; CHECK-LABEL: define { <2 x ptr addrspace(8)>, <2 x i32> } @addrspacecast_vec
-; CHECK-SAME: (<2 x ptr addrspace(8)> [[BUF:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: (<2 x ptr addrspace(8)> [[BUF:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = insertvalue { <2 x ptr addrspace(8)>, <2 x i32> } poison, <2 x ptr addrspace(8)> [[BUF]], 0
; CHECK-NEXT: [[RET:%.*]] = insertvalue { <2 x ptr addrspace(8)>, <2 x i32> } [[TMP1]], <2 x i32> zeroinitializer, 1
; CHECK-NEXT: ret { <2 x ptr addrspace(8)>, <2 x i32> } [[RET]]
@@ -383,8 +383,7 @@ define <2 x ptr addrspace(7)> @addrspacecast_vec(<2 x ptr addrspace(8)> %buf) {
}
define ptr addrspace(7) @addrspacecast_null() {
-; CHECK-LABEL: define { ptr addrspace(8), i32 } @addrspacecast_null
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define { ptr addrspace(8), i32 } @addrspacecast_null() {
; CHECK-NEXT: ret { ptr addrspace(8), i32 } zeroinitializer
;
%ret = addrspacecast ptr null to ptr addrspace(7)
@@ -392,8 +391,7 @@ define ptr addrspace(7) @addrspacecast_null() {
}
define <2 x ptr addrspace(7)> @addrspacecast_null_vec() {
-; CHECK-LABEL: define { <2 x ptr addrspace(8)>, <2 x i32> } @addrspacecast_null_vec
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define { <2 x ptr addrspace(8)>, <2 x i32> } @addrspacecast_null_vec() {
; CHECK-NEXT: ret { <2 x ptr addrspace(8)>, <2 x i32> } zeroinitializer
;
%ret = addrspacecast <2 x ptr> zeroinitializer to <2 x ptr addrspace(7)>
@@ -402,7 +400,7 @@ define <2 x ptr addrspace(7)> @addrspacecast_null_vec() {
define i1 @test_null(ptr addrspace(7) %p) {
; CHECK-LABEL: define i1 @test_null
-; CHECK-SAME: ({ ptr addrspace(8), i32 } [[P:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } [[P:%.*]]) {
; CHECK-NEXT: [[P_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[P]], 0
; CHECK-NEXT: [[P_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[P]], 1
; CHECK-NEXT: [[IS_NULL:%.*]] = icmp eq i32 [[P_OFF]], 0
@@ -413,8 +411,7 @@ define i1 @test_null(ptr addrspace(7) %p) {
}
define ptr addrspace(7) @addrspacecast_undef() {
-; CHECK-LABEL: define { ptr addrspace(8), i32 } @addrspacecast_undef
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define { ptr addrspace(8), i32 } @addrspacecast_undef() {
; CHECK-NEXT: ret { ptr addrspace(8), i32 } undef
;
%ret = addrspacecast ptr undef to ptr addrspace(7)
@@ -422,8 +419,7 @@ define ptr addrspace(7) @addrspacecast_undef() {
}
define <2 x ptr addrspace(7)> @addrspacecast_undef_vec() {
-; CHECK-LABEL: define { <2 x ptr addrspace(8)>, <2 x i32> } @addrspacecast_undef_vec
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define { <2 x ptr addrspace(8)>, <2 x i32> } @addrspacecast_undef_vec() {
; CHECK-NEXT: ret { <2 x ptr addrspace(8)>, <2 x i32> } undef
;
%ret = addrspacecast <2 x ptr> undef to <2 x ptr addrspace(7)>
@@ -431,8 +427,7 @@ define <2 x ptr addrspace(7)> @addrspacecast_undef_vec() {
}
define ptr addrspace(7) @addrspacecast_poison() {
-; CHECK-LABEL: define { ptr addrspace(8), i32 } @addrspacecast_poison
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define { ptr addrspace(8), i32 } @addrspacecast_poison() {
; CHECK-NEXT: ret { ptr addrspace(8), i32 } poison
;
%ret = addrspacecast ptr poison to ptr addrspace(7)
@@ -440,8 +435,7 @@ define ptr addrspace(7) @addrspacecast_poison() {
}
define <2 x ptr addrspace(7)> @addrspacecast_poison_vec() {
-; CHECK-LABEL: define { <2 x ptr addrspace(8)>, <2 x i32> } @addrspacecast_poison_vec
-; CHECK-SAME: () #[[ATTR0]] {
+; CHECK-LABEL: define { <2 x ptr addrspace(8)>, <2 x i32> } @addrspacecast_poison_vec() {
; CHECK-NEXT: ret { <2 x ptr addrspace(8)>, <2 x i32> } poison
;
%ret = addrspacecast <2 x ptr> poison to <2 x ptr addrspace(7)>
@@ -452,7 +446,7 @@ declare ptr addrspace(7) @llvm.amdgcn.make.buffer.rsrc.p7.p1(ptr addrspace(1), i
define ptr addrspace(7) @make_buffer_rsrc(ptr addrspace(1) %buf, i16 %stride, i64 %numRecords, i32 %flags) {
; CHECK-LABEL: define { ptr addrspace(8), i32 } @make_buffer_rsrc
-; CHECK-SAME: (ptr addrspace(1) [[BUF:%.*]], i16 [[STRIDE:%.*]], i64 [[NUMRECORDS:%.*]], i32 [[FLAGS:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: (ptr addrspace(1) [[BUF:%.*]], i16 [[STRIDE:%.*]], i64 [[NUMRECORDS:%.*]], i32 [[FLAGS:%.*]]) {
; CHECK-NEXT: [[RET:%.*]] = call ptr addrspace(8) @llvm.amdgcn.make.buffer.rsrc.p8.p1(ptr addrspace(1) [[BUF]], i16 [[STRIDE]], i64 [[NUMRECORDS]], i32 [[FLAGS]])
; CHECK-NEXT: [[TMP1:%.*]] = insertvalue { ptr addrspace(8), i32 } poison, ptr addrspace(8) [[RET]], 0
; CHECK-NEXT: [[TMP2:%.*]] = insertvalue { ptr addrspace(8), i32 } [[TMP1]], i32 0, 1
@@ -464,7 +458,7 @@ define ptr addrspace(7) @make_buffer_rsrc(ptr addrspace(1) %buf, i16 %stride, i6
define i1 @icmp_eq(ptr addrspace(7) %a, ptr addrspace(7) %b) {
; CHECK-LABEL: define i1 @icmp_eq
-; CHECK-SAME: ({ ptr addrspace(8), i32 } [[A:%.*]], { ptr addrspace(8), i32 } [[B:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } [[A:%.*]], { ptr addrspace(8), i32 } [[B:%.*]]) {
; CHECK-NEXT: [[B_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[B]], 0
; CHECK-NEXT: [[B_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[B]], 1
; CHECK-NEXT: [[A_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[A]], 0
@@ -478,7 +472,7 @@ define i1 @icmp_eq(ptr addrspace(7) %a, ptr addrspace(7) %b) {
define i1 @icmp_ne(ptr addrspace(7) %a, ptr addrspace(7) %b) {
; CHECK-LABEL: define i1 @icmp_ne
-; CHECK-SAME: ({ ptr addrspace(8), i32 } [[A:%.*]], { ptr addrspace(8), i32 } [[B:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } [[A:%.*]], { ptr addrspace(8), i32 } [[B:%.*]]) {
; CHECK-NEXT: [[B_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[B]], 0
; CHECK-NEXT: [[B_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[B]], 1
; CHECK-NEXT: [[A_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[A]], 0
@@ -492,7 +486,7 @@ define i1 @icmp_ne(ptr addrspace(7) %a, ptr addrspace(7) %b) {
define <2 x i1> @icmp_eq_vec(<2 x ptr addrspace(7)> %a, <2 x ptr addrspace(7)> %b) {
; CHECK-LABEL: define <2 x i1> @icmp_eq_vec
-; CHECK-SAME: ({ <2 x ptr addrspace(8)>, <2 x i32> } [[A:%.*]], { <2 x ptr addrspace(8)>, <2 x i32> } [[B:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ <2 x ptr addrspace(8)>, <2 x i32> } [[A:%.*]], { <2 x ptr addrspace(8)>, <2 x i32> } [[B:%.*]]) {
; CHECK-NEXT: [[B_RSRC:%.*]] = extractvalue { <2 x ptr addrspace(8)>, <2 x i32> } [[B]], 0
; CHECK-NEXT: [[B_OFF:%.*]] = extractvalue { <2 x ptr addrspace(8)>, <2 x i32> } [[B]], 1
; CHECK-NEXT: [[A_RSRC:%.*]] = extractvalue { <2 x ptr addrspace(8)>, <2 x i32> } [[A]], 0
@@ -506,7 +500,7 @@ define <2 x i1> @icmp_eq_vec(<2 x ptr addrspace(7)> %a, <2 x ptr addrspace(7)> %
define <2 x i1> @icmp_ne_vec(<2 x ptr addrspace(7)> %a, <2 x ptr addrspace(7)> %b) {
; CHECK-LABEL: define <2 x i1> @icmp_ne_vec
-; CHECK-SAME: ({ <2 x ptr addrspace(8)>, <2 x i32> } [[A:%.*]], { <2 x ptr addrspace(8)>, <2 x i32> } [[B:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ <2 x ptr addrspace(8)>, <2 x i32> } [[A:%.*]], { <2 x ptr addrspace(8)>, <2 x i32> } [[B:%.*]]) {
; CHECK-NEXT: [[B_RSRC:%.*]] = extractvalue { <2 x ptr addrspace(8)>, <2 x i32> } [[B]], 0
; CHECK-NEXT: [[B_OFF:%.*]] = extractvalue { <2 x ptr addrspace(8)>, <2 x i32> } [[B]], 1
; CHECK-NEXT: [[A_RSRC:%.*]] = extractvalue { <2 x ptr addrspace(8)>, <2 x i32> } [[A]], 0
@@ -520,7 +514,7 @@ define <2 x i1> @icmp_ne_vec(<2 x ptr addrspace(7)> %a, <2 x ptr addrspace(7)> %
define ptr addrspace(7) @freeze(ptr addrspace(7) %p) {
; CHECK-LABEL: define { ptr addrspace(8), i32 } @freeze
-; CHECK-SAME: ({ ptr addrspace(8), i32 } [[P:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } [[P:%.*]]) {
; CHECK-NEXT: [[P_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[P]], 0
; CHECK-NEXT: [[P_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[P]], 1
; CHECK-NEXT: [[RET_RSRC:%.*]] = freeze ptr addrspace(8) [[P_RSRC]]
@@ -535,7 +529,7 @@ define ptr addrspace(7) @freeze(ptr addrspace(7) %p) {
define <2 x ptr addrspace(7)> @freeze_vec(<2 x ptr addrspace(7)> %p) {
; CHECK-LABEL: define { <2 x ptr addrspace(8)>, <2 x i32> } @freeze_vec
-; CHECK-SAME: ({ <2 x ptr addrspace(8)>, <2 x i32> } [[P:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ <2 x ptr addrspace(8)>, <2 x i32> } [[P:%.*]]) {
; CHECK-NEXT: [[P_RSRC:%.*]] = extractvalue { <2 x ptr addrspace(8)>, <2 x i32> } [[P]], 0
; CHECK-NEXT: [[P_OFF:%.*]] = extractvalue { <2 x ptr addrspace(8)>, <2 x i32> } [[P]], 1
; CHECK-NEXT: [[RET_RSRC:%.*]] = freeze <2 x ptr addrspace(8)> [[P_RSRC]]
@@ -550,7 +544,7 @@ define <2 x ptr addrspace(7)> @freeze_vec(<2 x ptr addrspace(7)> %p) {
define ptr addrspace(7) @extractelement(<2 x ptr addrspace(7)> %v, i32 %i) {
; CHECK-LABEL: define { ptr addrspace(8), i32 } @extractelement
-; CHECK-SAME: ({ <2 x ptr addrspace(8)>, <2 x i32> } [[V:%.*]], i32 [[I:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ <2 x ptr addrspace(8)>, <2 x i32> } [[V:%.*]], i32 [[I:%.*]]) {
; CHECK-NEXT: [[V_RSRC:%.*]] = extractvalue { <2 x ptr addrspace(8)>, <2 x i32> } [[V]], 0
; CHECK-NEXT: [[V_OFF:%.*]] = extractvalue { <2 x ptr addrspace(8)>, <2 x i32> } [[V]], 1
; CHECK-NEXT: [[RET_RSRC:%.*]] = extractelement <2 x ptr addrspace(8)> [[V_RSRC]], i32 [[I]]
@@ -565,7 +559,7 @@ define ptr addrspace(7) @extractelement(<2 x ptr addrspace(7)> %v, i32 %i) {
define <2 x ptr addrspace(7)> @insertelement(<2 x ptr addrspace(7)> %v, ptr addrspace(7) %s, i32 %i) {
; CHECK-LABEL: define { <2 x ptr addrspace(8)>, <2 x i32> } @insertelement
-; CHECK-SAME: ({ <2 x ptr addrspace(8)>, <2 x i32> } [[V:%.*]], { ptr addrspace(8), i32 } [[S:%.*]], i32 [[I:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ <2 x ptr addrspace(8)>, <2 x i32> } [[V:%.*]], { ptr addrspace(8), i32 } [[S:%.*]], i32 [[I:%.*]]) {
; CHECK-NEXT: [[S_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[S]], 0
; CHECK-NEXT: [[S_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[S]], 1
; CHECK-NEXT: [[V_RSRC:%.*]] = extractvalue { <2 x ptr addrspace(8)>, <2 x i32> } [[V]], 0
@@ -582,7 +576,7 @@ define <2 x ptr addrspace(7)> @insertelement(<2 x ptr addrspace(7)> %v, ptr addr
define <4 x ptr addrspace(7)> @shufflenvector(<2 x ptr addrspace(7)> %a, <2 x ptr addrspace(7)> %b) {
; CHECK-LABEL: define { <4 x ptr addrspace(8)>, <4 x i32> } @shufflenvector
-; CHECK-SAME: ({ <2 x ptr addrspace(8)>, <2 x i32> } [[A:%.*]], { <2 x ptr addrspace(8)>, <2 x i32> } [[B:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ <2 x ptr addrspace(8)>, <2 x i32> } [[A:%.*]], { <2 x ptr addrspace(8)>, <2 x i32> } [[B:%.*]]) {
; CHECK-NEXT: [[B_RSRC:%.*]] = extractvalue { <2 x ptr addrspace(8)>, <2 x i32> } [[B]], 0
; CHECK-NEXT: [[B_OFF:%.*]] = extractvalue { <2 x ptr addrspace(8)>, <2 x i32> } [[B]], 1
; CHECK-NEXT: [[A_RSRC:%.*]] = extractvalue { <2 x ptr addrspace(8)>, <2 x i32> } [[A]], 0
@@ -601,7 +595,7 @@ declare ptr addrspace(7) @llvm.ptrmask.p7.i32(ptr addrspace(7), i32)
define ptr addrspace(7) @ptrmask(ptr addrspace(7) %p, i32 %mask) {
; CHECK-LABEL: define { ptr addrspace(8), i32 } @ptrmask
-; CHECK-SAME: ({ ptr addrspace(8), i32 } [[P:%.*]], i32 [[MASK:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } [[P:%.*]], i32 [[MASK:%.*]]) {
; CHECK-NEXT: [[P_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[P]], 0
; CHECK-NEXT: [[P_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[P]], 1
; CHECK-NEXT: [[RET_OFF:%.*]] = and i32 [[P_OFF]], [[MASK]]
@@ -617,7 +611,7 @@ declare void @llvm.invariant.end.p7(ptr, i64, ptr addrspace(7) nocapture)
define i32 @invariant_start_end(ptr addrspace(7) %p) {
; CHECK-LABEL: define i32 @invariant_start_end
-; CHECK-SAME: ({ ptr addrspace(8), i32 } [[P:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } [[P:%.*]]) {
; CHECK-NEXT: [[P_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[P]], 0
; CHECK-NEXT: [[P_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[P]], 1
; CHECK-NEXT: [[INV:%.*]] = call ptr @llvm.invariant.start.p8(i64 256, ptr addrspace(8) [[P_RSRC]])
@@ -636,7 +630,7 @@ declare ptr addrspace(7) @llvm.strip.invariant.group.p7(ptr addrspace(7) nocaptu
define ptr addrspace(7) @invariant_group(ptr addrspace(7) %p) {
; CHECK-LABEL: define { ptr addrspace(8), i32 } @invariant_group
-; CHECK-SAME: ({ ptr addrspace(8), i32 } [[P:%.*]]) #[[ATTR0]] {
+; CHECK-SAME: ({ ptr addrspace(8), i32 } [[P:%.*]]) {
; CHECK-NEXT: [[P_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[P]], 0
; CHECK-NEXT: [[P_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[P]], 1
; CHECK-NEXT: [[LAUNDERED:%.*]] = call ptr addrspace(8) @llvm.launder.invariant.group.p8(ptr addrspace(8) [[P_RSRC]])
diff --git a/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-unoptimized-debug-data.ll b/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-unoptimized-debug-data.ll
index 1ab2a145f6b73..21d0caa40ea3e 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-unoptimized-debug-data.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-unoptimized-debug-data.ll
@@ -1,66 +1,66 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
-; RUN: opt -S -mcpu=gfx900 -mattr=+unaligned-access-mode -amdgpu-lower-buffer-fat-pointers -check-debugify < %s | FileCheck %s
-; RUN: opt -S -mcpu=gfx900 -mattr=+unaligned-access-mode -passes=amdgpu-lower-buffer-fat-pointers,check-debugify < %s | FileCheck %s
+; RUN: opt -S -mattr=+unaligned-access-mode -amdgpu-lower-buffer-fat-pointers -check-debugify < %s | FileCheck %s
+; RUN: opt -S -mattr=+unaligned-access-mode -passes=amdgpu-lower-buffer-fat-pointers,check-debugify < %s | FileCheck %s
-target triple = "amdgcn--"
+target triple = "amdgpu9.00--"
define float @debug_stash_pointer(ptr addrspace(8) %buf, i32 %idx, ptr addrspace(8) %aux) !dbg !5 {
; CHECK-LABEL: define float @debug_stash_pointer
-; CHECK-SAME: (ptr addrspace(8) [[BUF:%.*]], i32 [[IDX:%.*]], ptr addrspace(8) [[AUX:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG5:![0-9]+]] {
-; CHECK-NEXT: [[BUF_PTR_VAR:%.*]] = alloca i160, align 32, addrspace(5), !dbg [[DBG21:![0-9]+]]
-; CHECK-NEXT: #dbg_value(ptr addrspace(5) [[BUF_PTR_VAR]], [[META10:![0-9]+]], !DIExpression(), [[DBG21]])
-; CHECK-NEXT: [[AUX_PTR_VAR:%.*]] = alloca i160, align 32, addrspace(5), !dbg [[DBG22:![0-9]+]]
-; CHECK-NEXT: #dbg_value(ptr addrspace(5) [[AUX_PTR_VAR]], [[META12:![0-9]+]], !DIExpression(), [[DBG22]])
-; CHECK-NEXT: #dbg_value(i32 0, [[META13:![0-9]+]], !DIExpression(DW_OP_LLVM_fragment, 128, 32), [[META23:![0-9]+]])
-; CHECK-NEXT: #dbg_value(ptr addrspace(8) [[BUF]], [[META13]], !DIExpression(DW_OP_LLVM_fragment, 0, 128), [[META23]])
-; CHECK-NEXT: [[BUF_PTR_INT_RSRC:%.*]] = ptrtoint ptr addrspace(8) [[BUF]] to i160, !dbg [[DBG24:![0-9]+]]
-; CHECK-NEXT: [[BUF_PTR_INT:%.*]] = shl nuw i160 [[BUF_PTR_INT_RSRC]], 32, !dbg [[DBG24]]
-; CHECK-NEXT: store i160 [[BUF_PTR_INT]], ptr addrspace(5) [[BUF_PTR_VAR]], align 32, !dbg [[DBG24]], !DIAssignID [[DIASSIGNID25:![0-9]+]]
-; CHECK-NEXT: #dbg_assign(i160 [[BUF_PTR_INT]], [[META13]], !DIExpression(), [[DIASSIGNID25]], ptr addrspace(5) [[BUF_PTR_VAR]], !DIExpression(), [[DBG21]])
-; CHECK-NEXT: #dbg_value(i32 0, [[META15:![0-9]+]], !DIExpression(DW_OP_LLVM_fragment, 128, 32), [[META26:![0-9]+]])
-; CHECK-NEXT: #dbg_value(ptr addrspace(8) [[AUX]], [[META15]], !DIExpression(DW_OP_LLVM_fragment, 0, 128), [[META26]])
-; CHECK-NEXT: [[AUX_PTR_INT_RSRC:%.*]] = ptrtoint ptr addrspace(8) [[AUX]] to i160, !dbg [[DBG27:![0-9]+]]
-; CHECK-NEXT: [[AUX_PTR_INT:%.*]] = shl nuw i160 [[AUX_PTR_INT_RSRC]], 32, !dbg [[DBG27]]
-; CHECK-NEXT: store i160 [[AUX_PTR_INT]], ptr addrspace(5) [[AUX_PTR_VAR]], align 32, !dbg [[DBG27]]
-; CHECK-NEXT: [[BUF_PTR_2:%.*]] = load i160, ptr addrspace(5) [[BUF_PTR_VAR]], align 32, !dbg [[DBG28:![0-9]+]]
-; CHECK-NEXT: [[TMP1:%.*]] = lshr i160 [[BUF_PTR_2]], 32, !dbg [[DBG28]]
-; CHECK-NEXT: [[TMP2:%.*]] = trunc i160 [[TMP1]] to i128, !dbg [[DBG28]]
-; CHECK-NEXT: [[BUF_PTR_2_PTR_RSRC:%.*]] = inttoptr i128 [[TMP2]] to ptr addrspace(8), !dbg [[DBG28]]
-; CHECK-NEXT: [[BUF_PTR_2_PTR_OFF:%.*]] = trunc i160 [[BUF_PTR_2]] to i32, !dbg [[DBG28]]
-; CHECK-NEXT: #dbg_value(i32 [[BUF_PTR_2_PTR_OFF]], [[META16:![0-9]+]], !DIExpression(DW_OP_LLVM_fragment, 128, 32), [[DBG28]])
-; CHECK-NEXT: #dbg_value(ptr addrspace(8) [[BUF_PTR_2_PTR_RSRC]], [[META16]], !DIExpression(DW_OP_LLVM_fragment, 0, 128), [[DBG28]])
-; CHECK-NEXT: [[BUF_PTR_3_IDX:%.*]] = mul i32 [[IDX]], 4, !dbg [[DBG29:![0-9]+]]
-; CHECK-NEXT: [[BUF_PTR_3:%.*]] = add i32 [[BUF_PTR_2_PTR_OFF]], [[BUF_PTR_3_IDX]], !dbg [[DBG29]]
-; CHECK-NEXT: #dbg_value(i32 [[BUF_PTR_3]], [[META17:![0-9]+]], !DIExpression(DW_OP_LLVM_fragment, 128, 32), [[DBG29]])
+; CHECK-SAME: (ptr addrspace(8) [[BUF:%.*]], i32 [[IDX:%.*]], ptr addrspace(8) [[AUX:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] {
+; CHECK-NEXT: [[BUF_PTR_VAR:%.*]] = alloca i160, align 32, addrspace(5), !dbg [[DBG22:![0-9]+]]
+; CHECK-NEXT: #dbg_value(ptr addrspace(5) [[BUF_PTR_VAR]], [[META11:![0-9]+]], !DIExpression(), [[DBG22]])
+; CHECK-NEXT: [[AUX_PTR_VAR:%.*]] = alloca i160, align 32, addrspace(5), !dbg [[DBG23:![0-9]+]]
+; CHECK-NEXT: #dbg_value(ptr addrspace(5) [[AUX_PTR_VAR]], [[META13:![0-9]+]], !DIExpression(), [[DBG23]])
+; CHECK-NEXT: #dbg_value(i32 0, [[META14:![0-9]+]], !DIExpression(DW_OP_LLVM_fragment, 128, 32), [[META24:![0-9]+]])
+; CHECK-NEXT: #dbg_value(ptr addrspace(8) [[BUF]], [[META14]], !DIExpression(DW_OP_LLVM_fragment, 0, 128), [[META24]])
+; CHECK-NEXT: [[BUF_PTR_INT_RSRC:%.*]] = ptrtoint ptr addrspace(8) [[BUF]] to i160, !dbg [[DBG25:![0-9]+]]
+; CHECK-NEXT: [[BUF_PTR_INT:%.*]] = shl nuw i160 [[BUF_PTR_INT_RSRC]], 32, !dbg [[DBG25]]
+; CHECK-NEXT: store i160 [[BUF_PTR_INT]], ptr addrspace(5) [[BUF_PTR_VAR]], align 32, !dbg [[DBG25]], !DIAssignID [[DIASSIGNID26:![0-9]+]]
+; CHECK-NEXT: #dbg_assign(i160 [[BUF_PTR_INT]], [[META14]], !DIExpression(), [[DIASSIGNID26]], ptr addrspace(5) [[BUF_PTR_VAR]], !DIExpression(), [[DBG22]])
+; CHECK-NEXT: #dbg_value(i32 0, [[META16:![0-9]+]], !DIExpression(DW_OP_LLVM_fragment, 128, 32), [[META27:![0-9]+]])
+; CHECK-NEXT: #dbg_value(ptr addrspace(8) [[AUX]], [[META16]], !DIExpression(DW_OP_LLVM_fragment, 0, 128), [[META27]])
+; CHECK-NEXT: [[AUX_PTR_INT_RSRC:%.*]] = ptrtoint ptr addrspace(8) [[AUX]] to i160, !dbg [[DBG28:![0-9]+]]
+; CHECK-NEXT: [[AUX_PTR_INT:%.*]] = shl nuw i160 [[AUX_PTR_INT_RSRC]], 32, !dbg [[DBG28]]
+; CHECK-NEXT: store i160 [[AUX_PTR_INT]], ptr addrspace(5) [[AUX_PTR_VAR]], align 32, !dbg [[DBG28]]
+; CHECK-NEXT: [[BUF_PTR_2:%.*]] = load i160, ptr addrspace(5) [[BUF_PTR_VAR]], align 32, !dbg [[DBG29:![0-9]+]]
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i160 [[BUF_PTR_2]], 32, !dbg [[DBG29]]
+; CHECK-NEXT: [[TMP2:%.*]] = trunc i160 [[TMP1]] to i128, !dbg [[DBG29]]
+; CHECK-NEXT: [[BUF_PTR_2_PTR_RSRC:%.*]] = inttoptr i128 [[TMP2]] to ptr addrspace(8), !dbg [[DBG29]]
+; CHECK-NEXT: [[BUF_PTR_2_PTR_OFF:%.*]] = trunc i160 [[BUF_PTR_2]] to i32, !dbg [[DBG29]]
+; CHECK-NEXT: #dbg_value(i32 [[BUF_PTR_2_PTR_OFF]], [[META17:![0-9]+]], !DIExpression(DW_OP_LLVM_fragment, 128, 32), [[DBG29]])
; CHECK-NEXT: #dbg_value(ptr addrspace(8) [[BUF_PTR_2_PTR_RSRC]], [[META17]], !DIExpression(DW_OP_LLVM_fragment, 0, 128), [[DBG29]])
-; CHECK-NEXT: [[BUF_PTR_3_INT_RSRC:%.*]] = ptrtoint ptr addrspace(8) [[BUF_PTR_2_PTR_RSRC]] to i160, !dbg [[DBG30:![0-9]+]]
-; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i160 [[BUF_PTR_3_INT_RSRC]], 32, !dbg [[DBG30]]
-; CHECK-NEXT: [[BUF_PTR_3_INT_OFF:%.*]] = zext i32 [[BUF_PTR_3]] to i160, !dbg [[DBG30]]
-; CHECK-NEXT: [[BUF_PTR_3_INT:%.*]] = or i160 [[TMP3]], [[BUF_PTR_3_INT_OFF]], !dbg [[DBG30]]
-; CHECK-NEXT: store i160 [[BUF_PTR_3_INT]], ptr addrspace(5) [[BUF_PTR_VAR]], align 32, !dbg [[DBG30]]
-; CHECK-NEXT: [[BUF_PTR_4:%.*]] = load i160, ptr addrspace(5) [[BUF_PTR_VAR]], align 32, !dbg [[DBG31:![0-9]+]]
-; CHECK-NEXT: [[TMP4:%.*]] = lshr i160 [[BUF_PTR_4]], 32, !dbg [[DBG31]]
-; CHECK-NEXT: [[TMP5:%.*]] = trunc i160 [[TMP4]] to i128, !dbg [[DBG31]]
-; CHECK-NEXT: [[BUF_PTR_4_PTR_RSRC:%.*]] = inttoptr i128 [[TMP5]] to ptr addrspace(8), !dbg [[DBG31]]
-; CHECK-NEXT: [[BUF_PTR_4_PTR_OFF:%.*]] = trunc i160 [[BUF_PTR_4]] to i32, !dbg [[DBG31]]
-; CHECK-NEXT: #dbg_value(i32 [[BUF_PTR_4_PTR_OFF]], [[META18:![0-9]+]], !DIExpression(DW_OP_LLVM_fragment, 128, 32), [[DBG31]])
-; CHECK-NEXT: #dbg_value(ptr addrspace(8) [[BUF_PTR_4_PTR_RSRC]], [[META18]], !DIExpression(DW_OP_LLVM_fragment, 0, 128), [[DBG31]])
-; CHECK-NEXT: [[RET:%.*]] = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) align 4 [[BUF_PTR_4_PTR_RSRC]], i32 [[BUF_PTR_4_PTR_OFF]], i32 0, i32 0), !dbg [[DBG32:![0-9]+]]
-; CHECK-NEXT: #dbg_value(float [[RET]], [[META19:![0-9]+]], !DIExpression(), [[DBG32]])
-; CHECK-NEXT: [[AUX_PTR_2:%.*]] = load i160, ptr addrspace(5) [[AUX_PTR_VAR]], align 32, !dbg [[DBG33:![0-9]+]]
-; CHECK-NEXT: [[TMP6:%.*]] = lshr i160 [[AUX_PTR_2]], 32, !dbg [[DBG33]]
-; CHECK-NEXT: [[TMP7:%.*]] = trunc i160 [[TMP6]] to i128, !dbg [[DBG33]]
-; CHECK-NEXT: [[AUX_PTR_2_PTR_RSRC:%.*]] = inttoptr i128 [[TMP7]] to ptr addrspace(8), !dbg [[DBG33]]
-; CHECK-NEXT: [[AUX_PTR_2_PTR_OFF:%.*]] = trunc i160 [[AUX_PTR_2]] to i32, !dbg [[DBG33]]
-; CHECK-NEXT: #dbg_value(i32 [[AUX_PTR_2_PTR_OFF]], [[META20:![0-9]+]], !DIExpression(DW_OP_LLVM_fragment, 128, 32), [[DBG33]])
-; CHECK-NEXT: #dbg_value(ptr addrspace(8) [[AUX_PTR_2_PTR_RSRC]], [[META20]], !DIExpression(DW_OP_LLVM_fragment, 0, 128), [[DBG33]])
-; CHECK-NEXT: [[BUF_PTR_4_LEGAL:%.*]] = bitcast i160 [[BUF_PTR_4]] to <5 x i32>, !dbg [[DBG34:![0-9]+]]
-; CHECK-NEXT: [[BUF_PTR_4_SLICE_0:%.*]] = shufflevector <5 x i32> [[BUF_PTR_4_LEGAL]], <5 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>, !dbg [[DBG34]]
-; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[BUF_PTR_4_SLICE_0]], ptr addrspace(8) align 32 [[AUX_PTR_2_PTR_RSRC]], i32 [[AUX_PTR_2_PTR_OFF]], i32 0, i32 0), !dbg [[DBG34]]
-; CHECK-NEXT: [[AUX_PTR_2_PTR_PART_4:%.*]] = add nuw i32 [[AUX_PTR_2_PTR_OFF]], 16, !dbg [[DBG34]]
-; CHECK-NEXT: [[BUF_PTR_4_SLICE_4:%.*]] = extractelement <5 x i32> [[BUF_PTR_4_LEGAL]], i64 4, !dbg [[DBG34]]
-; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[BUF_PTR_4_SLICE_4]], ptr addrspace(8) align 16 [[AUX_PTR_2_PTR_RSRC]], i32 [[AUX_PTR_2_PTR_PART_4]], i32 0, i32 0), !dbg [[DBG34]]
-; CHECK-NEXT: ret float [[RET]], !dbg [[DBG35:![0-9]+]]
+; CHECK-NEXT: [[BUF_PTR_3_IDX:%.*]] = mul i32 [[IDX]], 4, !dbg [[DBG30:![0-9]+]]
+; CHECK-NEXT: [[BUF_PTR_3:%.*]] = add i32 [[BUF_PTR_2_PTR_OFF]], [[BUF_PTR_3_IDX]], !dbg [[DBG30]]
+; CHECK-NEXT: #dbg_value(i32 [[BUF_PTR_3]], [[META18:![0-9]+]], !DIExpression(DW_OP_LLVM_fragment, 128, 32), [[DBG30]])
+; CHECK-NEXT: #dbg_value(ptr addrspace(8) [[BUF_PTR_2_PTR_RSRC]], [[META18]], !DIExpression(DW_OP_LLVM_fragment, 0, 128), [[DBG30]])
+; CHECK-NEXT: [[BUF_PTR_3_INT_RSRC:%.*]] = ptrtoint ptr addrspace(8) [[BUF_PTR_2_PTR_RSRC]] to i160, !dbg [[DBG31:![0-9]+]]
+; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i160 [[BUF_PTR_3_INT_RSRC]], 32, !dbg [[DBG31]]
+; CHECK-NEXT: [[BUF_PTR_3_INT_OFF:%.*]] = zext i32 [[BUF_PTR_3]] to i160, !dbg [[DBG31]]
+; CHECK-NEXT: [[BUF_PTR_3_INT:%.*]] = or i160 [[TMP3]], [[BUF_PTR_3_INT_OFF]], !dbg [[DBG31]]
+; CHECK-NEXT: store i160 [[BUF_PTR_3_INT]], ptr addrspace(5) [[BUF_PTR_VAR]], align 32, !dbg [[DBG31]]
+; CHECK-NEXT: [[BUF_PTR_4:%.*]] = load i160, ptr addrspace(5) [[BUF_PTR_VAR]], align 32, !dbg [[DBG32:![0-9]+]]
+; CHECK-NEXT: [[TMP4:%.*]] = lshr i160 [[BUF_PTR_4]], 32, !dbg [[DBG32]]
+; CHECK-NEXT: [[TMP5:%.*]] = trunc i160 [[TMP4]] to i128, !dbg [[DBG32]]
+; CHECK-NEXT: [[BUF_PTR_4_PTR_RSRC:%.*]] = inttoptr i128 [[TMP5]] to ptr addrspace(8), !dbg [[DBG32]]
+; CHECK-NEXT: [[BUF_PTR_4_PTR_OFF:%.*]] = trunc i160 [[BUF_PTR_4]] to i32, !dbg [[DBG32]]
+; CHECK-NEXT: #dbg_value(i32 [[BUF_PTR_4_PTR_OFF]], [[META19:![0-9]+]], !DIExpression(DW_OP_LLVM_fragment, 128, 32), [[DBG32]])
+; CHECK-NEXT: #dbg_value(ptr addrspace(8) [[BUF_PTR_4_PTR_RSRC]], [[META19]], !DIExpression(DW_OP_LLVM_fragment, 0, 128), [[DBG32]])
+; CHECK-NEXT: [[RET:%.*]] = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) align 4 [[BUF_PTR_4_PTR_RSRC]], i32 [[BUF_PTR_4_PTR_OFF]], i32 0, i32 0), !dbg [[DBG33:![0-9]+]]
+; CHECK-NEXT: #dbg_value(float [[RET]], [[META20:![0-9]+]], !DIExpression(), [[DBG33]])
+; CHECK-NEXT: [[AUX_PTR_2:%.*]] = load i160, ptr addrspace(5) [[AUX_PTR_VAR]], align 32, !dbg [[DBG34:![0-9]+]]
+; CHECK-NEXT: [[TMP6:%.*]] = lshr i160 [[AUX_PTR_2]], 32, !dbg [[DBG34]]
+; CHECK-NEXT: [[TMP7:%.*]] = trunc i160 [[TMP6]] to i128, !dbg [[DBG34]]
+; CHECK-NEXT: [[AUX_PTR_2_PTR_RSRC:%.*]] = inttoptr i128 [[TMP7]] to ptr addrspace(8), !dbg [[DBG34]]
+; CHECK-NEXT: [[AUX_PTR_2_PTR_OFF:%.*]] = trunc i160 [[AUX_PTR_2]] to i32, !dbg [[DBG34]]
+; CHECK-NEXT: #dbg_value(i32 [[AUX_PTR_2_PTR_OFF]], [[META21:![0-9]+]], !DIExpression(DW_OP_LLVM_fragment, 128, 32), [[DBG34]])
+; CHECK-NEXT: #dbg_value(ptr addrspace(8) [[AUX_PTR_2_PTR_RSRC]], [[META21]], !DIExpression(DW_OP_LLVM_fragment, 0, 128), [[DBG34]])
+; CHECK-NEXT: [[BUF_PTR_4_LEGAL:%.*]] = bitcast i160 [[BUF_PTR_4]] to <5 x i32>, !dbg [[DBG35:![0-9]+]]
+; CHECK-NEXT: [[BUF_PTR_4_SLICE_0:%.*]] = shufflevector <5 x i32> [[BUF_PTR_4_LEGAL]], <5 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>, !dbg [[DBG35]]
+; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> [[BUF_PTR_4_SLICE_0]], ptr addrspace(8) align 32 [[AUX_PTR_2_PTR_RSRC]], i32 [[AUX_PTR_2_PTR_OFF]], i32 0, i32 0), !dbg [[DBG35]]
+; CHECK-NEXT: [[AUX_PTR_2_PTR_PART_4:%.*]] = add nuw i32 [[AUX_PTR_2_PTR_OFF]], 16, !dbg [[DBG35]]
+; CHECK-NEXT: [[BUF_PTR_4_SLICE_4:%.*]] = extractelement <5 x i32> [[BUF_PTR_4_LEGAL]], i64 4, !dbg [[DBG35]]
+; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 [[BUF_PTR_4_SLICE_4]], ptr addrspace(8) align 16 [[AUX_PTR_2_PTR_RSRC]], i32 [[AUX_PTR_2_PTR_PART_4]], i32 0, i32 0), !dbg [[DBG35]]
+; CHECK-NEXT: ret float [[RET]], !dbg [[DBG36:![0-9]+]]
;
%buf.ptr.var = alloca ptr addrspace(7), align 32, addrspace(5), !dbg !20
call void @llvm.dbg.value(metadata ptr addrspace(5) %buf.ptr.var, metadata !9, metadata !DIExpression()), !dbg !20
diff --git a/llvm/test/CodeGen/AMDGPU/mcinstlower-external-symbol-reloc.mir b/llvm/test/CodeGen/AMDGPU/mcinstlower-external-symbol-reloc.mir
index d0104ca1f7639..5cec0ee7a18ba 100644
--- a/llvm/test/CodeGen/AMDGPU/mcinstlower-external-symbol-reloc.mir
+++ b/llvm/test/CodeGen/AMDGPU/mcinstlower-external-symbol-reloc.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -start-after=prolog-epilog %s -o - | FileCheck --check-prefix=ASM %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -start-after=prolog-epilog -filetype=obj %s -o %t.o && llvm-readobj -r %t.o | FileCheck --check-prefix=ELF %s
+# RUN: llc -mtriple=amdgpu9.00 -start-after=prolog-epilog %s -o - | FileCheck --check-prefix=ASM %s
+# RUN: llc -mtriple=amdgpu9.00 -start-after=prolog-epilog -filetype=obj %s -o %t.o && llvm-readobj -r %t.o | FileCheck --check-prefix=ELF %s
# AMDGPUMCInstLower must apply the operand's target flag specifier when
# lowering an MO_ExternalSymbol operand, just like it does for
diff --git a/llvm/test/CodeGen/AMDGPU/noop-shader-O0.ll b/llvm/test/CodeGen/AMDGPU/noop-shader-O0.ll
index c02b3fbb21715..35637c5433fc4 100644
--- a/llvm/test/CodeGen/AMDGPU/noop-shader-O0.ll
+++ b/llvm/test/CodeGen/AMDGPU/noop-shader-O0.ll
@@ -6,8 +6,6 @@
; Confirm registers reserved in SIMachineFunctionInfo are those expected during
; lowering, even when e.g. spilling is required due to being at OptNone.
-target triple = "amdgcn-amd-amdpal"
-
define amdgpu_vs void @noop_vs() {
; GCN-LABEL: noop_vs:
; GCN: ; %bb.0: ; %entry
diff --git a/llvm/test/CodeGen/AMDGPU/pack-half-to-lshl-or.ll b/llvm/test/CodeGen/AMDGPU/pack-half-to-lshl-or.ll
index 67c502547b975..446c598d746c8 100644
--- a/llvm/test/CodeGen/AMDGPU/pack-half-to-lshl-or.ll
+++ b/llvm/test/CodeGen/AMDGPU/pack-half-to-lshl-or.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=amdgcn -mcpu=gfx803 < %s | FileCheck -check-prefixes=GFX8 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-FAKE16 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-TRUE16 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12-FAKE16 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12-TRUE16 %s
+; RUN: llc -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=GFX8 %s
+; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX9 %s
+; RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-FAKE16 %s
+; RUN: llc -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgpu12.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12-FAKE16 %s
+; RUN: llc -mtriple=amdgpu12.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12-TRUE16 %s
define i32 @pack_high_half(i16 %hi, i32 %lo) {
; GFX8-LABEL: pack_high_half:
diff --git a/llvm/test/CodeGen/AMDGPU/packed_shl64_combine.ll b/llvm/test/CodeGen/AMDGPU/packed_shl64_combine.ll
index 7532c431427cd..76d7bdf7a55e0 100644
--- a/llvm/test/CodeGen/AMDGPU/packed_shl64_combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/packed_shl64_combine.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1251 < %s | FileCheck %s
+; RUN: llc -mtriple=amdgpu12.51-- < %s | FileCheck %s
define <2 x i64> @func_v2i64_vector(<2 x i64> %arg) {
; CHECK-LABEL: func_v2i64_vector:
diff --git a/llvm/test/CodeGen/AMDGPU/phi-elimination-assertion.mir b/llvm/test/CodeGen/AMDGPU/phi-elimination-assertion.mir
index c53f81eae52ce..474eb3f80840d 100644
--- a/llvm/test/CodeGen/AMDGPU/phi-elimination-assertion.mir
+++ b/llvm/test/CodeGen/AMDGPU/phi-elimination-assertion.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn -run-pass livevars -run-pass phi-node-elimination -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn --passes='require<live-vars>,phi-node-elimination' -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -run-pass livevars -run-pass phi-node-elimination -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 --passes='require<live-vars>,phi-node-elimination' -o - %s | FileCheck %s
################################################################################
# This test used to hit an assert in PHIElimination:
diff --git a/llvm/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir b/llvm/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir
index 79919d92804b9..c2b9f34ea78b0 100644
--- a/llvm/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir
+++ b/llvm/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn -run-pass livevars -run-pass phi-node-elimination -verify-machineinstrs -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn --passes='require<live-vars>,phi-node-elimination' -verify-each -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00 -run-pass livevars -run-pass phi-node-elimination -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00 --passes='require<live-vars>,phi-node-elimination' -verify-each -o - %s | FileCheck %s
# CHECK-LABEL: phi-cf-test
# CHECK: bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/rewrite-out-arguments-2.ll b/llvm/test/CodeGen/AMDGPU/rewrite-out-arguments-2.ll
index 5a35d603e9703..f836bd61ff864 100644
--- a/llvm/test/CodeGen/AMDGPU/rewrite-out-arguments-2.ll
+++ b/llvm/test/CodeGen/AMDGPU/rewrite-out-arguments-2.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
-; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -amdgpu-rewrite-out-arguments < %s | FileCheck %s
+; RUN: opt -S -mtriple=amdgpu7.00-amd-amdhsa -amdgpu-rewrite-out-arguments < %s | FileCheck %s
define i32 @load_out_ptr_after_store(ptr addrspace(5) %out) {
; CHECK-LABEL: define i32 @load_out_ptr_after_store(
diff --git a/llvm/test/CodeGen/AMDGPU/s-barrier-signal-var-gep.ll b/llvm/test/CodeGen/AMDGPU/s-barrier-signal-var-gep.ll
index 15194df6aa09e..65a6f150ab79a 100644
--- a/llvm/test/CodeGen/AMDGPU/s-barrier-signal-var-gep.ll
+++ b/llvm/test/CodeGen/AMDGPU/s-barrier-signal-var-gep.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefixes=CHECK,CHECK-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefixes=CHECK,CHECK-GISEL %s
-; RUN: llc -global-isel=0 -amdgpu-enable-object-linking -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefixes=CHECK-OBJ,CHECK-OBJ-SDAG %s
-; RUN: llc -global-isel=1 -amdgpu-enable-object-linking -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefixes=CHECK-OBJ,CHECK-OBJ-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgpu12.50-amd-amdhsa < %s | FileCheck -check-prefixes=CHECK,CHECK-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu12.50-amd-amdhsa < %s | FileCheck -check-prefixes=CHECK,CHECK-GISEL %s
+; RUN: llc -global-isel=0 -amdgpu-enable-object-linking -mtriple=amdgpu12.50-amd-amdhsa < %s | FileCheck -check-prefixes=CHECK-OBJ,CHECK-OBJ-SDAG %s
+; RUN: llc -global-isel=1 -amdgpu-enable-object-linking -mtriple=amdgpu12.50-amd-amdhsa < %s | FileCheck -check-prefixes=CHECK-OBJ,CHECK-OBJ-GISEL %s
@bars = internal addrspace(3) global [2 x target("amdgcn.named.barrier", 0)] poison
diff --git a/llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-dead-def-join.mir b/llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-dead-def-join.mir
index c27a5e9ef24b1..19400a782fd63 100644
--- a/llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-dead-def-join.mir
+++ b/llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-dead-def-join.mir
@@ -8,7 +8,6 @@
# the problematic move.
--- |
- target triple = "amdgcn-unknown-amdhsa"
define amdgpu_kernel void @rock_attention(ptr addrspace(1) inreg %0, ptr addrspace(1) inreg %1, ptr addrspace(1) inreg %2, ptr addrspace(1) inreg %3, ptr addrspace(1) inreg %4, ptr addrspace(1) inreg %5) #0 {
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwwmregs-dbg-noreg.mir b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwwmregs-dbg-noreg.mir
index cb515f880d0a0..d42a87dabdfbc 100644
--- a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwwmregs-dbg-noreg.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwwmregs-dbg-noreg.mir
@@ -1,4 +1,4 @@
-# RUN: llc %s -o - -mcpu=gfx1030 -O0 -run-pass=si-pre-allocate-wwm-regs | FileCheck %s
+# RUN: llc %s -o - -mtriple=amdgpu10.30-amd-amdpal -O0 -run-pass=si-pre-allocate-wwm-regs | FileCheck %s
# Simple regression test to make sure DBG_VALUE $noreg does not assert in the pass
@@ -6,20 +6,19 @@
# CHECK: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr3, 0, $vgpr0
--- |
- target triple = "amdgcn-amd-amdpal"
%dx.types.ResRet.f32 = type { float, float, float, float, i32 }
-
+
define dllexport amdgpu_cs void @_amdgpu_cs_main(i32 inreg noundef %globalTable, i32 inreg noundef %userdata4, <3 x i32> inreg noundef %WorkgroupId, i32 inreg noundef %MultiDispatchInfo, <3 x i32> noundef %LocalInvocationId) #0 !dbg !5 {
#dbg_value(i32 poison, !19, !DIExpression(DW_OP_LLVM_fragment, 0, 32), !20)
#dbg_value(%dx.types.ResRet.f32 poison, !21, !DIExpression(), !23)
ret void, !dbg !24
}
-
+
attributes #0 = { memory(readwrite) "amdgpu-prealloc-sgpr-spill-vgprs" }
-
+
!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!3, !4}
-
+
!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "dxcoob 1.7.2308.16 (52da17e29)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, globals: !2)
!1 = !DIFile(filename: "tests\\basic_var.hlsl", directory: "")
!2 = !{}
@@ -58,7 +57,7 @@ machineFunctionInfo:
body: |
bb.0 (%ir-block.0):
liveins: $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2
-
+
%0:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr3, 0, %2
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fptrunc_bf16.ll b/llvm/test/CodeGen/AMDGPU/strict_fptrunc_bf16.ll
index dacd5502463b6..8ac7aa84b31e8 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fptrunc_bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fptrunc_bf16.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck --check-prefixes=GFX950 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck --check-prefixes=GFX1250 %s
+; RUN: llc -mtriple=amdgpu9.50 < %s | FileCheck --check-prefixes=GFX950 %s
+; RUN: llc -mtriple=amdgpu12.50 -mattr=-real-true16 < %s | FileCheck --check-prefixes=GFX1250 %s
define amdgpu_ps void @strict_fptrunc_f32_to_bf16(float %a, ptr %out) #0 {
; GFX950-LABEL: strict_fptrunc_f32_to_bf16:
diff --git a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
index 5037508772fb1..0fb518348562c 100644
--- a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
+++ b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
@@ -2,7 +2,6 @@
; RUN: llc -mtriple=amdgpu6.00 -amdgpu-codegenprepare-break-large-phis=0 -amdgpu-dce-in-ra=0 -o - %s | FileCheck %s
; Don't crash when the use of an undefined value is only detected by the
; register coalescer because it is hidden with subregister insert/extract.
-target triple="amdgcn--"
; NOTE: breaking large PHIs is disabled here else this example is completely optimized out
; before reaching codegen.
diff --git a/llvm/test/CodeGen/AMDGPU/v_mov_b64-isel.ll b/llvm/test/CodeGen/AMDGPU/v_mov_b64-isel.ll
index d8e09d7c31714..9e0ecd64b8355 100644
--- a/llvm/test/CodeGen/AMDGPU/v_mov_b64-isel.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_mov_b64-isel.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --filter "S_MOV_B32|REG_SEQUENCE|V_MOV_B32_e32|V_MOV_B64|COPY|DS_WRITE_B64" --version 6
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=NOVMOV %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx942 -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX942 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX1250 %s
+; RUN: llc -mtriple=amdgpu9.00 -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=NOVMOV %s
+; RUN: llc -mtriple=amdgpu9.42 -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX942 %s
+; RUN: llc -mtriple=amdgpu12.50 -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GFX1250 %s
define void @store_i64_inline(ptr addrspace(3) %ptr) {
; NOVMOV-LABEL: name: store_i64_inline
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-setreg-pred-block.mir b/llvm/test/CodeGen/AMDGPU/vgpr-setreg-pred-block.mir
index 1ae20fe073798..47e1fe0c4ed1f 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-setreg-pred-block.mir
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-setreg-pred-block.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=amdgpu-lower-vgpr-encoding -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.50 -run-pass=amdgpu-lower-vgpr-encoding -o - %s | FileCheck %s
# All S_SETREG_IMM32_B32(MODE) in the file have size=4(<12) and imm32[12:19]=0.
# This ensures they do not cause the insertion of a S_NOP by default. All
diff --git a/llvm/test/CodeGen/Generic/GlobalISel/irtranslator-byte-type.ll b/llvm/test/CodeGen/Generic/GlobalISel/irtranslator-byte-type.ll
index 5a6b28a839d09..9d91ff55d6916 100644
--- a/llvm/test/CodeGen/Generic/GlobalISel/irtranslator-byte-type.ll
+++ b/llvm/test/CodeGen/Generic/GlobalISel/irtranslator-byte-type.ll
@@ -4,7 +4,7 @@
; REQUIRES: x86-registered-target
; RUN: llc -mtriple=aarch64-linux-gnu -O0 -stop-after=irtranslator -global-isel %s -o - 2>&1 | FileCheck %s --check-prefix=AARCH64
-; RUN: llc -mtriple=amdgcn--mesa-mesa3d -O0 -stop-after=irtranslator -global-isel %s -o - 2>&1 | FileCheck %s --check-prefix=AMDGPU
+; RUN: llc -mtriple=amdgpu6.00--mesa-mesa3d -O0 -stop-after=irtranslator -global-isel %s -o - 2>&1 | FileCheck %s --check-prefix=AMDGPU
; RUN: llc -mtriple=x86_64-linux-gnu -O0 -stop-after=irtranslator -global-isel %s -o - 2>&1 | FileCheck %s --check-prefix=X86
; IRTranslator handling of LLVM IR's byte type (bN), constants and loads /
diff --git a/llvm/test/CodeGen/Generic/bfloat-op.ll b/llvm/test/CodeGen/Generic/bfloat-op.ll
index 6eec5eef81cd8..c02eae16bc7fe 100644
--- a/llvm/test/CodeGen/Generic/bfloat-op.ll
+++ b/llvm/test/CodeGen/Generic/bfloat-op.ll
@@ -6,7 +6,7 @@
; RUN: %if aarch64-registered-target %{ llc %s -o - -mtriple=aarch64-pc-windows-msvc | FileCheck %s --check-prefixes=ALL,CHECK-COPYSIGN,CHECK-FMA %}
; RUN: %if aarch64-registered-target %{ llc %s -o - -mtriple=aarch64-unknown-linux-gnu | FileCheck %s --check-prefixes=ALL,CHECK-COPYSIGN,CHECK-FMA %}
; RUN: %if aarch64-registered-target %{ llc %s -o - -mtriple=arm64ec-pc-windows-msvc | FileCheck %s --check-prefixes=ALL,CHECK-COPYSIGN,CHECK-FMA %}
-; RUN: %if amdgpu-registered-target %{ llc %s -o - -mtriple=amdgcn-amd-amdhsa | FileCheck %s --check-prefixes=ALL,CHECK-COPYSIGN,CHECK-FMA %}
+; RUN: %if amdgpu-registered-target %{ llc %s -o - -mtriple=amdgpu7.00-amd-amdhsa | FileCheck %s --check-prefixes=ALL,CHECK-COPYSIGN,CHECK-FMA %}
; RUN: %if arc-registered-target %{ llc %s -o - -mtriple=arc-elf | FileCheck %s --check-prefixes=ALL,CHECK-COPYSIGN,BAD-FMA %}
; RUN: %if arm-registered-target %{ llc %s -o - -mtriple=arm-unknown-linux-gnueabi | FileCheck %s --check-prefixes=ALL,CHECK-COPYSIGN,BAD-FMA %}
; RUN: %if arm-registered-target %{ llc %s -o - -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefixes=ALL,CHECK-COPYSIGN,BAD-FMA %}
diff --git a/llvm/test/CodeGen/Generic/bfloat.ll b/llvm/test/CodeGen/Generic/bfloat.ll
index 83c6711de89cd..5f67dcca669fd 100644
--- a/llvm/test/CodeGen/Generic/bfloat.ll
+++ b/llvm/test/CodeGen/Generic/bfloat.ll
@@ -8,7 +8,7 @@
; RUN: %if aarch64-registered-target %{ llc %s -o - -mtriple=aarch64-pc-windows-msvc | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if aarch64-registered-target %{ llc %s -o - -mtriple=aarch64-unknown-linux-gnu | FileCheck %s --check-prefixes=ALL,CHECK %}
; FIXME: arm64ec crashes when passing/returning bfloat
-; RUN: %if amdgpu-registered-target %{ llc %s -o - -mtriple=amdgcn-amd-amdhsa | FileCheck %s --check-prefixes=ALL,CHECK %}
+; RUN: %if amdgpu-registered-target %{ llc %s -o - -mtriple=amdgpu7.00-amd-amdhsa | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if arc-registered-target %{ llc %s -o - -mtriple=arc-elf | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if arm-registered-target %{ llc %s -o - -mtriple=arm-unknown-linux-gnueabi | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if arm-registered-target %{ llc %s -o - -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefixes=ALL,CHECK %}
diff --git a/llvm/test/CodeGen/Generic/half-op.ll b/llvm/test/CodeGen/Generic/half-op.ll
index ddc85ea66c0b5..139cf9e265793 100644
--- a/llvm/test/CodeGen/Generic/half-op.ll
+++ b/llvm/test/CodeGen/Generic/half-op.ll
@@ -5,7 +5,7 @@
; RUN: %if aarch64-registered-target %{ llc %s -o - -mtriple=aarch64-pc-windows-msvc | FileCheck %s --check-prefixes=ALL %}
; RUN: %if aarch64-registered-target %{ llc %s -o - -mtriple=aarch64-unknown-linux-gnu | FileCheck %s --check-prefixes=ALL %}
; RUN: %if aarch64-registered-target %{ llc %s -o - -mtriple=arm64ec-pc-windows-msvc | FileCheck %s --check-prefixes=ALL %}
-; RUN: %if amdgpu-registered-target %{ llc %s -o - -mtriple=amdgcn-amd-amdhsa | FileCheck %s --check-prefixes=ALL %}
+; RUN: %if amdgpu-registered-target %{ llc %s -o - -mtriple=amdgpu7.00-amd-amdhsa | FileCheck %s --check-prefixes=ALL %}
; RUN: %if arc-registered-target %{ llc %s -o - -mtriple=arc-elf | FileCheck %s --check-prefixes=ALL %}
; RUN: %if arm-registered-target %{ llc %s -o - -mtriple=arm-unknown-linux-gnueabi | FileCheck %s --check-prefixes=ALL %}
; RUN: %if arm-registered-target %{ llc %s -o - -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefixes=ALL %}
diff --git a/llvm/test/CodeGen/Generic/half.ll b/llvm/test/CodeGen/Generic/half.ll
index 4949a1628a77a..20c50643d85e1 100644
--- a/llvm/test/CodeGen/Generic/half.ll
+++ b/llvm/test/CodeGen/Generic/half.ll
@@ -8,7 +8,7 @@
; RUN: %if aarch64-registered-target %{ llc %s -o - -mtriple=aarch64-pc-windows-msvc | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if aarch64-registered-target %{ llc %s -o - -mtriple=aarch64-unknown-linux-gnu | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if aarch64-registered-target %{ llc %s -o - -mtriple=arm64ec-pc-windows-msvc | FileCheck %s --check-prefixes=ALL,CHECK %}
-; RUN: %if amdgpu-registered-target %{ llc %s -o - -mtriple=amdgcn-amd-amdhsa | FileCheck %s --check-prefixes=ALL,CHECK %}
+; RUN: %if amdgpu-registered-target %{ llc %s -o - -mtriple=amdgpu7.00-amd-amdhsa | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if arc-registered-target %{ llc %s -o - -mtriple=arc-elf | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if arm-registered-target %{ llc %s -o - -mtriple=arm-unknown-linux-gnueabi | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if arm-registered-target %{ llc %s -o - -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefixes=ALL,CHECK %}
diff --git a/llvm/test/CodeGen/Generic/live-debug-label.ll b/llvm/test/CodeGen/Generic/live-debug-label.ll
index 3121b8700ed11..dc96e59f237bd 100644
--- a/llvm/test/CodeGen/Generic/live-debug-label.ll
+++ b/llvm/test/CodeGen/Generic/live-debug-label.ll
@@ -8,7 +8,7 @@
; this by teaching `-stop-after` how to stop at the last instance of a Pass,
; but we're just marking XFAIL for these two targets for now.
; XFAIL: target=riscv{{.*}}
-; XFAIL: target=amdgcn-{{.*}}
+; XFAIL: target=amdgpu-{{.*}}
; Generated with "clang++ -g -O1 -S -emit-llvm"
;
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/empty-custom-regmask.mir b/llvm/test/CodeGen/MIR/AMDGPU/empty-custom-regmask.mir
index 63e77bd69203d..746d0bec409da 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/empty-custom-regmask.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/empty-custom-regmask.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -run-pass=none -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00 -run-pass=none -o - %s | FileCheck %s
# Make sure there's no parse error on empty CustomRegMask or trailing comma
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir b/llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
index 7db8d53f11cc1..ef15542ed6ee4 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn -run-pass none -filetype=null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgpu6.00 -run-pass none -filetype=null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/intrinsics.mir b/llvm/test/CodeGen/MIR/AMDGPU/intrinsics.mir
index 0650f9cfae2e8..13f155582da40 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/intrinsics.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/intrinsics.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00 -run-pass=none -o - %s | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-fixed-stack.mir b/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-fixed-stack.mir
index 22842a3e68256..fe26a6ca18cc5 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-fixed-stack.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-fixed-stack.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -filetype=null 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=none -verify-machineinstrs %s -filetype=null 2>&1 | FileCheck %s
---
name: invalid_scavenge_fi
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-stack.mir b/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-stack.mir
index 700c2b6f14f04..bbc6678522635 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-stack.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-stack.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -filetype=null 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=none -verify-machineinstrs %s -filetype=null 2>&1 | FileCheck %s
---
name: invalid_scavenge_fi
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-no-stack.mir b/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-no-stack.mir
index 61a78c61b9750..ca31560875b78 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-no-stack.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-no-stack.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -filetype=null 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=none -verify-machineinstrs %s -filetype=null 2>&1 | FileCheck %s
---
name: invalid_scavenge_fi
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index.mir b/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index.mir
index e217acf962a25..53ff552d0baa4 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -filetype=null 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgpu6.00-amd-amdhsa -run-pass=none -verify-machineinstrs %s -filetype=null 2>&1 | FileCheck %s
---
name: invalid_scavenge_fi
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index2.mir b/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index2.mir
index ad23abcda16dd..738eceb625fcc 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index2.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index2.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -filetype=null 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=none -verify-machineinstrs %s -filetype=null 2>&1 | FileCheck %s
---
name: invalid_scavenge_fi
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir b/llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
index 4d3a502b27031..75b8edbcc1055 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn -run-pass none -filetype=null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgpu6.00 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/llc-target-cpu-attr-from-cmdline-ir.mir b/llvm/test/CodeGen/MIR/AMDGPU/llc-target-cpu-attr-from-cmdline-ir.mir
index 418873def82b8..c1c58f38aa4be 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/llc-target-cpu-attr-from-cmdline-ir.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/llc-target-cpu-attr-from-cmdline-ir.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn -mcpu=hawaii -run-pass=none -o - %s | FileCheck -check-prefix=MCPU %s
-# RUN: llc -mtriple=amdgcn -mattr=+unaligned-access-mode -run-pass=none -o - %s | FileCheck -check-prefix=MATTR %s
+# RUN: llc -mtriple=amdgpu7 -mcpu=hawaii -run-pass=none -o - %s | FileCheck -check-prefix=MCPU %s
+# RUN: llc -mtriple=amdgpu7 -mattr=+unaligned-access-mode -run-pass=none -o - %s | FileCheck -check-prefix=MATTR %s
# FIXME: This overrides attributes that already are present. It should probably
# only touch functions without an existing attribute.
@@ -7,10 +7,10 @@
# MCPU: @with_cpu_attr() #0 {
# MCPU: @no_cpu_attr() #1 {
-# MCPU: attributes #0 = { "target-cpu"="fiji" }
+# MCPU: attributes #0 = { "target-cpu"="gfx700" }
# MCPU: attributes #1 = { "target-cpu"="hawaii" }
-# MATTR: attributes #0 = { "target-cpu"="fiji" "target-features"="+unaligned-access-mode" }
+# MATTR: attributes #0 = { "target-cpu"="gfx700" "target-features"="+unaligned-access-mode" }
# MATTR: attributes #1 = { "target-features"="+unaligned-access-mode" }
--- |
@@ -22,7 +22,7 @@
ret void
}
- attributes #0 = { "target-cpu"="fiji" }
+ attributes #0 = { "target-cpu"="gfx700" }
...
---
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/llc-target-cpu-attr-from-cmdline.mir b/llvm/test/CodeGen/MIR/AMDGPU/llc-target-cpu-attr-from-cmdline.mir
index fb12b2a312615..d76a63407862b 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/llc-target-cpu-attr-from-cmdline.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/llc-target-cpu-attr-from-cmdline.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn -mcpu=hawaii -run-pass=none -o - %s | FileCheck -check-prefix=MCPU %s
-# RUN: llc -mtriple=amdgcn -mattr=+unaligned-access-mode -run-pass=none -o - %s | FileCheck -check-prefix=MATTR %s
+# RUN: llc -mtriple=amdgpu7 -mcpu=hawaii -run-pass=none -o - %s | FileCheck -check-prefix=MCPU %s
+# RUN: llc -mtriple=amdgpu7 -mattr=+unaligned-access-mode -run-pass=none -o - %s | FileCheck -check-prefix=MATTR %s
# The command line arguments for -mcpu and -mattr should manifest themselves by adding the corresponding attributes to the stub IR function.
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll b/llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll
index d608fa63bd668..d8c8ea1a87895 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll
+++ b/llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn -verify-machineinstrs -amdgpu-s-branch-bits=5 -stop-after=branch-relaxation %s -o - | FileCheck %s
+; RUN: llc -mtriple=amdgpu6.00 -verify-machineinstrs -amdgpu-s-branch-bits=5 -stop-after=branch-relaxation %s -o - | FileCheck %s
; Test long branch reserved register pass when all
; SGPRs are used
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/lr-split-flag.mir b/llvm/test/CodeGen/MIR/AMDGPU/lr-split-flag.mir
index ed1680e3545c2..6a517b7101c6e 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/lr-split-flag.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/lr-split-flag.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx950 -run-pass=none -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.50 -run-pass=none -o - %s | FileCheck %s
#
# Round-trip test for the 'lr-split' MIR text spelling of
# MachineInstr::LRSplit. The flag is set by SplitKit on copies inserted for
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-dynlds-align-invalid-case.mir b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-dynlds-align-invalid-case.mir
index be12301b1431a..ea7d3135e79fa 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-dynlds-align-invalid-case.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-dynlds-align-invalid-case.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
---
# CHECK: error: YAML:8:16: must be a power of two
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg-debug.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg-debug.ll
index bb1706402ea6f..796814baa195d 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg-debug.ll
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg-debug.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -amdgpu-s-branch-bits=4 -stop-after=branch-relaxation -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -amdgpu-s-branch-bits=4 -stop-after=branch-relaxation -verify-machineinstrs %s -o - | FileCheck %s
; Test that debug instructions do not change long branch reserved serialized through
; MIR.
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll
index e408458d65f1a..13a958c4b1ed5 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -amdgpu-s-branch-bits=4 -stop-after=branch-relaxation -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -amdgpu-s-branch-bits=4 -stop-after=branch-relaxation -verify-machineinstrs %s -o - | FileCheck %s
; Test that long branch reserved register is serialized through
; MIR.
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
index 60a9dd449da71..22e74925f8139 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mattr=+dx10-clamp-and-ieee-mode -run-pass=none -verify-machineinstrs %s -o - | FileCheck -check-prefixes=FULL,ALL %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mattr=+dx10-clamp-and-ieee-mode -run-pass=none -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefixes=SIMPLE,ALL %s
+# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -mattr=+dx10-clamp-and-ieee-mode -run-pass=none -verify-machineinstrs %s -o - | FileCheck -check-prefixes=FULL,ALL %s
+# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -mattr=+dx10-clamp-and-ieee-mode -run-pass=none -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefixes=SIMPLE,ALL %s
---
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir
index f6b313f031fd4..5899cdf4eb61c 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn -run-pass none -filetype=null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgpu6.00 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
---
name: noreg_rsrc_reg
machineFunctionInfo:
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir
index 7e14755c6e5ce..9fe98dcbe9747 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn -run-pass none -filetype=null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgpu7.00 -run-pass none -filetype=null %s 2>&1 | FileCheck %s
---
name: invalid_rsrc_reg
machineFunctionInfo:
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir b/llvm/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir
index 21a8f285e3557..7f246f42c04b0 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn -run-pass none -filetype=null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgpu6.00 -run-pass none -filetype=null %s 2>&1 | FileCheck %s
---
name: wrong_reg_class_frame_offset_reg
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir b/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir
index e189e4dcb2f4f..e138bae2a47d8 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn -run-pass none -filetype=null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgpu6.00 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
---
name: empty_frame_offset_reg
machineFunctionInfo:
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir b/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir
index af96283047b94..9455003a1e7d5 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn -run-pass none -filetype=null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgpu6.00 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
---
name: empty_scratch_rsrc_reg
machineFunctionInfo:
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir b/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir
index f5940bf2933ab..389c9c81ac938 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn -run-pass none -filetype=null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgpu6.00 -run-pass none -filetype=null %s 2>&1 | FileCheck %s
---
name: empty_stack_ptr_offset_reg
machineFunctionInfo:
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir b/llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir
index 09ff3977dbcb4..c7f2211e985f2 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn -run-pass none -filetype=null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgpu7.00 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
---
name: wrong_reg_class_scratch_rsrc_reg
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir b/llvm/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir
index dddcb8693d7bd..cb6072fffec1e 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn -run-pass none -filetype=null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgpu6.00 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
---
name: wrong_reg_class_stack_ptr_offset_reg
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi-def.mir b/llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi-def.mir
index efeb34603782c..2b5e61a413b14 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi-def.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi-def.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs %s -o - | FileCheck %s
---
name: multi_def_renaming
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir b/llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
index c67f7e662ef02..1f18f23413598 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
@@ -1,5 +1,5 @@
-# RUN: llc -o - -mtriple=amdgcn -run-pass mir-canonicalizer -verify-machineinstrs %s | FileCheck %s
-# RUN: llc -o - -mtriple=amdgcn -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -o - -mtriple=amdgpu6.00 -run-pass mir-canonicalizer -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -o - -mtriple=amdgpu6.00 -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs %s | FileCheck %s
# This tests for the itereator invalidation fix (reviews.llvm.org/D62713)
...
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/noconvergent-invalid.mir b/llvm/test/CodeGen/MIR/AMDGPU/noconvergent-invalid.mir
index bf6180c29f764..cfb8bbe301b4d 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/noconvergent-invalid.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/noconvergent-invalid.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -filetype=null 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=none -verify-machineinstrs %s -filetype=null 2>&1 | FileCheck %s
---
name: noconvergent_invalid
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/noconvergent.mir b/llvm/test/CodeGen/MIR/AMDGPU/noconvergent.mir
index f1a4454868290..53065215c659c 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/noconvergent.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/noconvergent.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00 -run-pass=none -o - %s | FileCheck %s
---
# Completely invalid code, but it checks that noconvergent round-trips properly.
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-empty-lanemask.mir b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-empty-lanemask.mir
index 68324f1b2f90e..9caa8ca4dc173 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-empty-lanemask.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-empty-lanemask.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
---
name: test_empty_lanemask_type
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-lanemask.mir b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-lanemask.mir
index 647f6116f18f7..6d9bf7d94f0e8 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-lanemask.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-lanemask.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
---
name: test_wrong_lanemask_type
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-missing-lparen.mir b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-missing-lparen.mir
index 3382572f67213..5935f9b6b9e18 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-missing-lparen.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-missing-lparen.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
---
name: test_missing_lparen
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-missing-rparen.mir b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-missing-rparen.mir
index 052305d9f9c36..06f01a53d80f4 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-missing-rparen.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-missing-rparen.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
---
name: test_missing_rparen
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand.mir b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand.mir
index 066bc8e79a56e..ea22ff8a11e78 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=none -verify-machineinstrs -o - %s | FileCheck %s
# This test checks for the correctness of the MIR parser for lanemask
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir b/llvm/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir
index ff66323826ac1..7d2210bb18b5c 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir
@@ -1,6 +1,6 @@
-# RUN: llc -mtriple=amdgcn -run-pass=none -verify-machineinstrs -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn -run-pass mir-canonicalizer -verify-machineinstrs -o - %s
-# RUN: llc -mtriple=amdgcn -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs -o - %s
+# RUN: llc -mtriple=amdgpu6.00 -run-pass=none -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00 -run-pass mir-canonicalizer -verify-machineinstrs -o - %s
+# RUN: llc -mtriple=amdgpu6.00 -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs -o - %s
# Previously getReservedRegs was called before parsing
# machineFunctionInfo, but the AMDGPU implementation depends on
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/s_wait_alu_missing_operand_crash.mir b/llvm/test/CodeGen/MIR/AMDGPU/s_wait_alu_missing_operand_crash.mir
index aba02459889c4..0d710a076d6b3 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/s_wait_alu_missing_operand_crash.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/s_wait_alu_missing_operand_crash.mir
@@ -1,4 +1,4 @@
-# RUN: ! llc -mtriple=amdgcn -run-pass=none %s -filetype=null 2>&1 | FileCheck %s
+# RUN: ! llc -mtriple=amdgpu12.00 -run-pass=none %s -filetype=null 2>&1 | FileCheck %s
---
# CHECK: Bad machine code: Too few operands
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/s_waitcnt_missing_operand_crash.mir b/llvm/test/CodeGen/MIR/AMDGPU/s_waitcnt_missing_operand_crash.mir
index f3c595fd186f4..3b86ee655ce37 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/s_waitcnt_missing_operand_crash.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/s_waitcnt_missing_operand_crash.mir
@@ -1,4 +1,4 @@
-# RUN: ! llc -mtriple=amdgcn -run-pass=none %s -filetype=null 2>&1 | FileCheck %s
+# RUN: ! llc -mtriple=amdgpu6.00 -run-pass=none %s -filetype=null 2>&1 | FileCheck %s
---
# CHECK: Bad machine code: Too few operands
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/sgpr-for-exec-copy-invalid-reg.mir b/llvm/test/CodeGen/MIR/AMDGPU/sgpr-for-exec-copy-invalid-reg.mir
index 15ffcf5f02b96..ff9841e536628 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/sgpr-for-exec-copy-invalid-reg.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/sgpr-for-exec-copy-invalid-reg.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none %s -filetype=null 2>&1 | FileCheck -check-prefix=ERR %s
+# RUN: not llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=none %s -filetype=null 2>&1 | FileCheck -check-prefix=ERR %s
---
name: invalid_reg
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-invalid.mir b/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-invalid.mir
index 6a20a370c8580..366051321fe71 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-invalid.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-invalid.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -filetype=null %s 2>&1 | FileCheck %s --check-prefix=ERR
+# RUN: not llc -mtriple=amdgpu6.00-amd-amdhsa -run-pass=none -filetype=null %s 2>&1 | FileCheck %s --check-prefix=ERR
---
name: invalid_reg_spill_phys_vgprs
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-not-a-reg.mir b/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-not-a-reg.mir
index 1f532781ee8f8..ccdc1e9b724e9 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-not-a-reg.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-not-a-reg.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -filetype=null %s 2>&1 | FileCheck %s --check-prefix=ERR
+# RUN: not llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=none -filetype=null %s 2>&1 | FileCheck %s --check-prefix=ERR
---
name: invalid_reg_spill_phys_vgprs
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir b/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir
index 0872ddb3745a8..13dc1f7f964d9 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn-amd-amdhsa --start-before=si-lower-sgpr-spills --stop-after=prolog-epilog -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa --start-before=si-lower-sgpr-spills --stop-after=prolog-epilog -o - %s | FileCheck %s
# CHECK: csr_sgpr_spill
# CHECK-NOT: spillPhysVGPRs
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir b/llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir
index 3d9a53a78118c..4a0290e7feab5 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir
@@ -3,7 +3,7 @@
# contains not dead objects only. So using objects IDs as offset in the storage
# caused out of bounds access.
-# RUN: llc -mtriple=amdgcn -start-before=si-lower-sgpr-spills -stop-after=prolog-epilog -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -start-before=si-lower-sgpr-spills -stop-after=prolog-epilog -o - %s | FileCheck %s
# CHECK-LABEL: name: foo
# CHECK: {{^}}fixedStack: []
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/stack-id.mir b/llvm/test/CodeGen/MIR/AMDGPU/stack-id.mir
index 6d122c0b087ff..9f9137cf3c63a 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/stack-id.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/stack-id.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu7.00 -run-pass none -o - %s | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/target-flags.mir b/llvm/test/CodeGen/MIR/AMDGPU/target-flags.mir
index 0de6114cd7d14..3bce5400e576b 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/target-flags.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/target-flags.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00 -run-pass none -o - %s | FileCheck %s
--- |
define amdgpu_kernel void @flags() {
ret void
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir b/llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
index 651cfe01dc2d2..4edfacd2dee12 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu7.00 -run-pass none -o - %s | FileCheck %s
# This test verifies that the MIR parser can parse target index operands.
--- |
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/target-memoperands.mir b/llvm/test/CodeGen/MIR/AMDGPU/target-memoperands.mir
index 82140c8156848..d674227dbd14d 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/target-memoperands.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/target-memoperands.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00 -run-pass=none -o - %s | FileCheck %s
---
name: target_memoperands_noclobber
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/vgpr-for-agpr-copy-invalid-reg.mir b/llvm/test/CodeGen/MIR/AMDGPU/vgpr-for-agpr-copy-invalid-reg.mir
index 1c16a0d085929..38545df392789 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/vgpr-for-agpr-copy-invalid-reg.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/vgpr-for-agpr-copy-invalid-reg.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -filetype=null 2>&1 | FileCheck -check-prefix=ERR %s
+# RUN: not llc -mtriple=amdgpu9.08-amd-amdhsa -run-pass=none -verify-machineinstrs %s -filetype=null 2>&1 | FileCheck -check-prefix=ERR %s
---
name: invalid_reg
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-invalid-reg.mir b/llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-invalid-reg.mir
index 2d317e518bbfa..ab832c1bb2e71 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-invalid-reg.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-invalid-reg.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -filetype=null 2>&1 | FileCheck -check-prefix=ERR %s
+# RUN: not llc -mtriple=amdgpu9.00-amd-amdhsa -run-pass=none -verify-machineinstrs %s -filetype=null 2>&1 | FileCheck -check-prefix=ERR %s
---
name: invalid_reg
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-not-a-reg.mir b/llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-not-a-reg.mir
index 6e3f4cf841628..3616881eee7fd 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-not-a-reg.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-not-a-reg.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -filetype=null 2>&1 | FileCheck -check-prefix=ERR %s
+# RUN: not llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=none %s -filetype=null 2>&1 | FileCheck -check-prefix=ERR %s
---
name: invalid_reg
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs.mir b/llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs.mir
index 128e73f2f44e9..ca253b39014c2 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o - | FileCheck %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -run-pass=none -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
# CHECK-LABEL: name: empty_wwm_regs{{$}}
# CHECK: machineFunctionInfo:
diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_do_not_internalize.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_do_not_internalize.ll
index a15f0024cfd05..30ace4cfaf758 100644
--- a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_do_not_internalize.ll
+++ b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_do_not_internalize.ll
@@ -1,7 +1,7 @@
-; RUN: opt -O0 -S -mtriple=amdgcn-unknown-amdhsa -amdgpu-internalize-symbols < %s | FileCheck -check-prefix=OPTNONE %s
-; RUN: opt -passes='default<O0>' -S -mtriple=amdgcn-unknown-amdhsa -amdgpu-internalize-symbols < %s | FileCheck -check-prefix=OPTNONE %s
-; RUN: opt -O1 -S -mtriple=amdgcn-unknown-amdhsa -amdgpu-internalize-symbols < %s | FileCheck -check-prefix=ASAN_NO_INTERNALIZE %s
-; RUN: opt -passes='default<O1>' -S -mtriple=amdgcn-unknown-amdhsa -amdgpu-internalize-symbols < %s | FileCheck -check-prefix=ASAN_NO_INTERNALIZE %s
+; RUN: opt -O0 -S -mtriple=amdgpu-unknown-amdhsa -amdgpu-internalize-symbols < %s | FileCheck -check-prefix=OPTNONE %s
+; RUN: opt -passes='default<O0>' -S -mtriple=amdgpu-unknown-amdhsa -amdgpu-internalize-symbols < %s | FileCheck -check-prefix=OPTNONE %s
+; RUN: opt -O1 -S -mtriple=amdgpu-unknown-amdhsa -amdgpu-internalize-symbols < %s | FileCheck -check-prefix=ASAN_NO_INTERNALIZE %s
+; RUN: opt -passes='default<O1>' -S -mtriple=amdgpu-unknown-amdhsa -amdgpu-internalize-symbols < %s | FileCheck -check-prefix=ASAN_NO_INTERNALIZE %s
; OPTNONE: define void @__asan_no_explicit_linkage(
; ASAN_NO_INTERNALIZE: define void @__asan_no_explicit_linkage(
diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_mem_intrinsics.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_mem_intrinsics.ll
index 2139ae0de0c9a..75a6e01d57d75 100644
--- a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_mem_intrinsics.ll
+++ b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_mem_intrinsics.ll
@@ -1,4 +1,4 @@
-;RUN: opt < %s -mtriple=amdgcn-amd-amdhsa -passes=asan -S | FileCheck %s
+;RUN: opt < %s -mtriple=amdgpu-amd-amdhsa -passes=asan -S | FileCheck %s
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg)
declare void @llvm.memcpy.p0.p1.i64(ptr noalias nocapture writeonly, ptr addrspace(1) noalias nocapture readonly, i64, i1 immarg)
diff --git a/llvm/test/Instrumentation/InstrProfiling/amdgpu-3d-grid.ll b/llvm/test/Instrumentation/InstrProfiling/amdgpu-3d-grid.ll
index f775b9756e878..11f6c39ba3a3d 100644
--- a/llvm/test/Instrumentation/InstrProfiling/amdgpu-3d-grid.ll
+++ b/llvm/test/Instrumentation/InstrProfiling/amdgpu-3d-grid.ll
@@ -2,7 +2,7 @@
;; and profile section symbols with CUID-based naming. The __llvm_profile_sampling_gpu
;; library function handles 3D block linearization internally.
-; RUN: opt %s -mtriple=amdgcn-amd-amdhsa -passes=instrprof -S | FileCheck %s
+; RUN: opt %s -mtriple=amdgpu-amd-amdhsa -passes=instrprof -S | FileCheck %s
@__hip_cuid_abcdef789 = addrspace(1) global i8 0
@__profn_kernel_3d = private constant [9 x i8] c"kernel_3d"
diff --git a/llvm/test/Instrumentation/InstrProfiling/amdgpu-contiguous-counters.ll b/llvm/test/Instrumentation/InstrProfiling/amdgpu-contiguous-counters.ll
index 8d48372a12de6..67865f666832e 100644
--- a/llvm/test/Instrumentation/InstrProfiling/amdgpu-contiguous-counters.ll
+++ b/llvm/test/Instrumentation/InstrProfiling/amdgpu-contiguous-counters.ll
@@ -5,7 +5,7 @@
;; array and whose second is a GEP into the matching uniform-counter array.
;; Sampling is disabled so the increment lowers to a direct call.
-; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -offload-pgo-sampling=0 -passes=instrprof < %s | FileCheck %s
+; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -offload-pgo-sampling=0 -passes=instrprof < %s | FileCheck %s
@__profn_kernel1 = private constant [7 x i8] c"kernel1"
@__profn_kernel2 = private constant [7 x i8] c"kernel2"
diff --git a/llvm/test/Instrumentation/InstrProfiling/amdgpu-instrumentation.ll b/llvm/test/Instrumentation/InstrProfiling/amdgpu-instrumentation.ll
index 963e141934df1..e9585ecbfebfb 100644
--- a/llvm/test/Instrumentation/InstrProfiling/amdgpu-instrumentation.ll
+++ b/llvm/test/Instrumentation/InstrProfiling/amdgpu-instrumentation.ll
@@ -5,10 +5,10 @@
;; sampling guard branch.
;; 3. No-sampling mode (sampling=0) calls __llvm_profile_instrument_gpu unconditionally.
-; RUN: opt %s -mtriple=amdgcn-amd-amdhsa -passes=instrprof \
+; RUN: opt %s -mtriple=amdgpu-amd-amdhsa -passes=instrprof \
; RUN: -offload-pgo-sampling=3 -S \
; RUN: | FileCheck %s --check-prefix=SAMPLED
-; RUN: opt %s -mtriple=amdgcn-amd-amdhsa -passes=instrprof \
+; RUN: opt %s -mtriple=amdgpu-amd-amdhsa -passes=instrprof \
; RUN: -offload-pgo-sampling=0 -S \
; RUN: | FileCheck %s --check-prefix=NOSAMPLE
diff --git a/llvm/test/Instrumentation/InstrProfiling/amdgpu-uniform-counters.ll b/llvm/test/Instrumentation/InstrProfiling/amdgpu-uniform-counters.ll
index ffdd41043bdbe..ae1164157c271 100644
--- a/llvm/test/Instrumentation/InstrProfiling/amdgpu-uniform-counters.ll
+++ b/llvm/test/Instrumentation/InstrProfiling/amdgpu-uniform-counters.ll
@@ -2,7 +2,7 @@
;; counters. The uniform counter is passed to __llvm_profile_instrument_gpu which
;; updates it when all lanes in the wave are active.
-; RUN: opt %s -mtriple=amdgcn-amd-amdhsa -passes=instrprof -S | FileCheck %s
+; RUN: opt %s -mtriple=amdgpu-amd-amdhsa -passes=instrprof -S | FileCheck %s
@__hip_cuid_test123 = addrspace(1) global i8 0
@__profn_test_kernel = private constant [11 x i8] c"test_kernel"
diff --git a/llvm/test/Instrumentation/InstrProfiling/amdgpu-wave32.ll b/llvm/test/Instrumentation/InstrProfiling/amdgpu-wave32.ll
index 9cdf733da1c6f..3a1653ff46c48 100644
--- a/llvm/test/Instrumentation/InstrProfiling/amdgpu-wave32.ll
+++ b/llvm/test/Instrumentation/InstrProfiling/amdgpu-wave32.ll
@@ -2,7 +2,7 @@
;; Verifies sampling guard and __llvm_profile_instrument_gpu call with correct
;; addrspace(1) counter pointers.
-; RUN: opt %s -mtriple=amdgcn-amd-amdhsa -passes=instrprof -S | FileCheck %s
+; RUN: opt %s -mtriple=amdgpu-amd-amdhsa -passes=instrprof -S | FileCheck %s
@__hip_cuid_abcdef456 = addrspace(1) global i8 0
@__profn_kernel_w32 = private constant [10 x i8] c"kernel_w32"
diff --git a/llvm/test/Instrumentation/InstrProfiling/amdgpu-wave64.ll b/llvm/test/Instrumentation/InstrProfiling/amdgpu-wave64.ll
index 0a776ba5da687..3979653df1f40 100644
--- a/llvm/test/Instrumentation/InstrProfiling/amdgpu-wave64.ll
+++ b/llvm/test/Instrumentation/InstrProfiling/amdgpu-wave64.ll
@@ -1,7 +1,7 @@
;; Test that AMDGPU PGO instrumentation generates library calls for Wave64.
;; Wave64 targets (e.g., gfx908) should embed wave size 64 in profile data.
-; RUN: opt %s -mtriple=amdgcn-amd-amdhsa -passes=instrprof -S | FileCheck %s
+; RUN: opt %s -mtriple=amdgpu-amd-amdhsa -passes=instrprof -S | FileCheck %s
@__hip_cuid_abcdef123 = addrspace(1) global i8 0
@__profn_kernel_w64 = private constant [10 x i8] c"kernel_w64"
diff --git a/llvm/test/Instrumentation/InstrProfiling/platform.ll b/llvm/test/Instrumentation/InstrProfiling/platform.ll
index 5f7eb47d2b611..c698f8f129599 100644
--- a/llvm/test/Instrumentation/InstrProfiling/platform.ll
+++ b/llvm/test/Instrumentation/InstrProfiling/platform.ll
@@ -9,7 +9,7 @@
; RUN: opt < %s -mtriple=x86_64-pc-windows -passes=instrprof -S | FileCheck %s -check-prefix=WINDOWS
; RUN: opt < %s -mtriple=powerpc64-ibm-aix-xcoff -passes=instrprof -S | FileCheck %s -check-prefix=AIX
; RUN: opt < %s -mtriple=arm-elf -passes=instrprof -S | FileCheck %s -check-prefix=BAREMETAL
-; RUN: opt < %s -mtriple=amdgcn-amd-amdhsa -passes=instrprof -S | FileCheck %s -check-prefix=AMDGPU
+; RUN: opt < %s -mtriple=amdgpu-amd-amdhsa -passes=instrprof -S | FileCheck %s -check-prefix=AMDGPU
@__profn_foo = private constant [3 x i8] c"foo"
; MACHO-NOT: __profn_foo
diff --git a/llvm/test/LTO/AMDGPU/closed-world-assumption.ll b/llvm/test/LTO/AMDGPU/closed-world-assumption.ll
index de1e614944d6b..0f1f153ad2304 100644
--- a/llvm/test/LTO/AMDGPU/closed-world-assumption.ll
+++ b/llvm/test/LTO/AMDGPU/closed-world-assumption.ll
@@ -1,6 +1,6 @@
-; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -O3 -debug-only=amdgpu-attributor -o - %s 2>&1 | FileCheck %s --check-prefixes=NO-CW,NO-LTO
-; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes="lto<O3>" -debug-only=amdgpu-attributor -o - %s 2>&1 | FileCheck %s --check-prefixes=NO-CW,LTO
-; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes="lto<O3>" -debug-only=amdgpu-attributor -amdgpu-link-time-closed-world=1 -o - %s 2>&1 | FileCheck %s --check-prefixes=CW,LTO
+; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -O3 -debug-only=amdgpu-attributor -o - %s 2>&1 | FileCheck %s --check-prefixes=NO-CW,NO-LTO
+; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes="lto<O3>" -debug-only=amdgpu-attributor -o - %s 2>&1 | FileCheck %s --check-prefixes=NO-CW,LTO
+; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes="lto<O3>" -debug-only=amdgpu-attributor -amdgpu-link-time-closed-world=1 -o - %s 2>&1 | FileCheck %s --check-prefixes=CW,LTO
; REQUIRES: amdgpu-registered-target
; REQUIRES: asserts
diff --git a/llvm/test/MachineVerifier/AMDGPU/undef-virt-reg-entry-block.mir b/llvm/test/MachineVerifier/AMDGPU/undef-virt-reg-entry-block.mir
index 5a1dedde1e8a2..9a9f684fda533 100644
--- a/llvm/test/MachineVerifier/AMDGPU/undef-virt-reg-entry-block.mir
+++ b/llvm/test/MachineVerifier/AMDGPU/undef-virt-reg-entry-block.mir
@@ -1,5 +1,5 @@
# XFAIL: *
-# RUN: not --crash llc -o - -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s
+# RUN: not --crash llc -o - -mtriple=amdgpu7.00-amd-amdhsa -run-pass=none -verify-machineinstrs %s
# FIXME: This should catch the undefined use of %0
diff --git a/llvm/test/MachineVerifier/AMDGPU/verifier-implicit-virtreg-invalid-physreg-liveness.mir b/llvm/test/MachineVerifier/AMDGPU/verifier-implicit-virtreg-invalid-physreg-liveness.mir
index c0f222407b266..1f56141cbc1ce 100644
--- a/llvm/test/MachineVerifier/AMDGPU/verifier-implicit-virtreg-invalid-physreg-liveness.mir
+++ b/llvm/test/MachineVerifier/AMDGPU/verifier-implicit-virtreg-invalid-physreg-liveness.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -filetype=null %s 2>&1 | FileCheck -check-prefix=ERROR %s
+# RUN: not --crash llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -filetype=null %s 2>&1 | FileCheck -check-prefix=ERROR %s
# When the verifier was detecting the invalid liveness for vcc, it would assert when trying to iterate the subregisters of the implicit virtual register use.
diff --git a/llvm/test/MachineVerifier/AMDGPU/verify-implicit-def.mir b/llvm/test/MachineVerifier/AMDGPU/verify-implicit-def.mir
index 04609ac989b38..b2696a1ab3c19 100644
--- a/llvm/test/MachineVerifier/AMDGPU/verify-implicit-def.mir
+++ b/llvm/test/MachineVerifier/AMDGPU/verify-implicit-def.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=amdgpu9.00-amd-amdhsa -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
---
name: invalid_reg_sequence
diff --git a/llvm/test/MachineVerifier/AMDGPU/writelane_m0.mir b/llvm/test/MachineVerifier/AMDGPU/writelane_m0.mir
index e3f7a144a88f6..906e4162cc574 100644
--- a/llvm/test/MachineVerifier/AMDGPU/writelane_m0.mir
+++ b/llvm/test/MachineVerifier/AMDGPU/writelane_m0.mir
@@ -1,11 +1,11 @@
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 -verify-machineinstrs -run-pass=none -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=none -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx904 -verify-machineinstrs -run-pass=none -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -verify-machineinstrs -run-pass=none -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs -run-pass=none -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -verify-machineinstrs -run-pass=none -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs -run-pass=none -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -verify-machineinstrs -run-pass=none -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu6.00-amd-amdhsa -verify-machineinstrs -run-pass=none -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -run-pass=none -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.04-amd-amdhsa -verify-machineinstrs -run-pass=none -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.42-amd-amdhsa -verify-machineinstrs -run-pass=none -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu10.10-amd-amdhsa -verify-machineinstrs -run-pass=none -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu10.30-amd-amdhsa -verify-machineinstrs -run-pass=none -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu11.00-amd-amdhsa -verify-machineinstrs -run-pass=none -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.00-amd-amdhsa -verify-machineinstrs -run-pass=none -o - %s | FileCheck %s
---
diff --git a/llvm/test/MachineVerifier/convergencectrl/AMDGPU/cycles.mir b/llvm/test/MachineVerifier/convergencectrl/AMDGPU/cycles.mir
index c3b26afc3d2a4..22bda8bf8c2e9 100644
--- a/llvm/test/MachineVerifier/convergencectrl/AMDGPU/cycles.mir
+++ b/llvm/test/MachineVerifier/convergencectrl/AMDGPU/cycles.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -mtriple=amdgcn -run-pass=none -verify-machineinstrs -filetype=null %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=amdgpu6.00 -run-pass=none -verify-machineinstrs -filetype=null %s 2>&1 | FileCheck %s
---
name: cycles
body: |
diff --git a/llvm/test/MachineVerifier/convergencectrl/AMDGPU/mixed2.mir b/llvm/test/MachineVerifier/convergencectrl/AMDGPU/mixed2.mir
index 3fb04e97240d2..e237be05bf4c4 100644
--- a/llvm/test/MachineVerifier/convergencectrl/AMDGPU/mixed2.mir
+++ b/llvm/test/MachineVerifier/convergencectrl/AMDGPU/mixed2.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -mtriple=amdgcn -run-pass=none -verify-machineinstrs -filetype=null %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=amdgpu6.00 -run-pass=none -verify-machineinstrs -filetype=null %s 2>&1 | FileCheck %s
---
name: mixed2
body: |
diff --git a/llvm/test/MachineVerifier/convergencectrl/AMDGPU/region-nesting.mir b/llvm/test/MachineVerifier/convergencectrl/AMDGPU/region-nesting.mir
index 7042e4a847fb0..1c8676b601588 100644
--- a/llvm/test/MachineVerifier/convergencectrl/AMDGPU/region-nesting.mir
+++ b/llvm/test/MachineVerifier/convergencectrl/AMDGPU/region-nesting.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -mtriple=amdgcn -run-pass=none -verify-machineinstrs -filetype=null %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=amdgpu6.00 -run-pass=none -verify-machineinstrs -filetype=null %s 2>&1 | FileCheck %s
---
name: region_nesting
body: |
diff --git a/llvm/test/MachineVerifier/stack-protector-offset.mir b/llvm/test/MachineVerifier/stack-protector-offset.mir
index 16ee3c8da8979..d786506281df5 100644
--- a/llvm/test/MachineVerifier/stack-protector-offset.mir
+++ b/llvm/test/MachineVerifier/stack-protector-offset.mir
@@ -5,7 +5,7 @@
# RUN: llc -mtriple=aarch64 -run-pass=none -o - %t/valid.mir
# RUN: not --crash llc -mtriple=aarch64 -run-pass=none -o - %t/lower.mir 2>&1 | FileCheck %t/lower.mir
# RUN: not --crash llc -mtriple=aarch64 -run-pass=none -o - %t/overlap.mir 2>&1 | FileCheck %t/overlap.mir
-# RUN: not --crash llc -mtriple=amdgcn -run-pass=none -o - %t/higher.mir 2>&1 | FileCheck %t/higher.mir
+# RUN: not --crash llc -mtriple=amdgpu7.00 -run-pass=none -o - %t/higher.mir 2>&1 | FileCheck %t/higher.mir
;--- valid.mir
---
diff --git a/llvm/test/ThinLTO/AMDGPU/force-import-all.ll b/llvm/test/ThinLTO/AMDGPU/force-import-all.ll
index 829fc515ee306..b185d74946d39 100644
--- a/llvm/test/ThinLTO/AMDGPU/force-import-all.ll
+++ b/llvm/test/ThinLTO/AMDGPU/force-import-all.ll
@@ -1,5 +1,5 @@
-; RUN: opt -mtriple=amdgcn-amd-amdhsa -module-summary %s -o %t.main.bc
-; RUN: opt -mtriple=amdgcn-amd-amdhsa -module-summary %p/Inputs/in-f1.ll -o %t.in.bc
+; RUN: opt -mtriple=amdgpu7.00-amd-amdhsa -module-summary %s -o %t.main.bc
+; RUN: opt -mtriple=amdgpu7.00-amd-amdhsa -module-summary %p/Inputs/in-f1.ll -o %t.in.bc
; RUN: llvm-lto -thinlto-action=run -force-import-all %t.main.bc %t.in.bc --thinlto-save-temps=%t.2.
; RUN: llvm-dis %t.2.0.3.imported.bc -o - | FileCheck --check-prefix=MOD1 %s
; RUN: llvm-dis %t.2.1.3.imported.bc -o - | FileCheck --check-prefix=MOD2 %s
diff --git a/llvm/test/Transforms/Attributor/heap_to_stack_gpu.ll b/llvm/test/Transforms/Attributor/heap_to_stack_gpu.ll
index b10910b3de2ef..c85e496c497f6 100644
--- a/llvm/test/Transforms/Attributor/heap_to_stack_gpu.ll
+++ b/llvm/test/Transforms/Attributor/heap_to_stack_gpu.ll
@@ -6,7 +6,7 @@
; useless except the __kmpc_alloc_shared part which now also covers the important
; part this test was initially designed for, make sure the "is freed" check is
; not sufficient on a GPU.
-target triple = "amdgcn-amd-amdhsa"
+target triple = "amdgpu7.00-amd-amdhsa"
declare noalias ptr @malloc(i64)
diff --git a/llvm/test/Transforms/Attributor/memory_locations_gpu.ll b/llvm/test/Transforms/Attributor/memory_locations_gpu.ll
index 49a2e69fe8f9a..91f0c8c0da61c 100644
--- a/llvm/test/Transforms/Attributor/memory_locations_gpu.ll
+++ b/llvm/test/Transforms/Attributor/memory_locations_gpu.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals
; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,TUNIT
; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,CGSCC
-target triple = "amdgcn-amd-amdhsa"
+target triple = "amdgpu7.00-amd-amdhsa"
@G = external dso_local addrspace(4) global i32, align 4
diff --git a/llvm/test/Transforms/Attributor/reduced/openmp_opt_constant_type_crash.ll b/llvm/test/Transforms/Attributor/reduced/openmp_opt_constant_type_crash.ll
index 6b78d3daa3551..5e86697fd89b2 100644
--- a/llvm/test/Transforms/Attributor/reduced/openmp_opt_constant_type_crash.ll
+++ b/llvm/test/Transforms/Attributor/reduced/openmp_opt_constant_type_crash.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes --check-attributes --check-globals --include-generated-funcs
; RUN: opt -passes=openmp-opt -S < %s | FileCheck %s
-target triple = "amdgcn-amd-amdhsa"
+target triple = "amdgpu9.00-amd-amdhsa"
%"struct.Kokkos::Impl::SubviewExtents.448" = type <{ [2 x i64], [1 x i64], [1 x i32], [4 x i8] }>
diff --git a/llvm/test/Transforms/Attributor/value-simplify-gpu.ll b/llvm/test/Transforms/Attributor/value-simplify-gpu.ll
index 31df85a0a75dd..e45e77a8ada21 100644
--- a/llvm/test/Transforms/Attributor/value-simplify-gpu.ll
+++ b/llvm/test/Transforms/Attributor/value-simplify-gpu.ll
@@ -2,7 +2,7 @@
; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,TUNIT
; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,CGSCC
-target triple = "amdgcn-amd-amdhsa"
+target triple = "amdgpu7.00-amd-amdhsa"
%struct.ident_t = type { i32, i32, i32, i32, ptr }
@ReachableKernel = internal addrspace(3) global i32 3, align 4
diff --git a/llvm/test/Transforms/FunctionAttrs/make-buffer-rsrc.ll b/llvm/test/Transforms/FunctionAttrs/make-buffer-rsrc.ll
index 4b2f8567a6fb8..0113437240236 100644
--- a/llvm/test/Transforms/FunctionAttrs/make-buffer-rsrc.ll
+++ b/llvm/test/Transforms/FunctionAttrs/make-buffer-rsrc.ll
@@ -2,8 +2,6 @@
; RUN: opt -passes=function-attrs -S < %s | FileCheck --check-prefixes=COMMON,FNATTRS %s
; RUN: opt -passes=attributor-light -S < %s | FileCheck --check-prefixes=COMMON,ATTRIBUTOR %s
-;; target triple = "amdgcn-amd-amdhsa"
-
define amdgpu_kernel void @test_make_buffer_rsrc(ptr %p, ptr %q) {
; FNATTRS: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite)
; FNATTRS-LABEL: define {{[^@]+}}@test_make_buffer_rsrc
diff --git a/llvm/test/Transforms/IndVarSimplify/AMDGPU/addrspace-7-doesnt-crash.ll b/llvm/test/Transforms/IndVarSimplify/AMDGPU/addrspace-7-doesnt-crash.ll
index 08dcf1d7a0091..9e4539c1279e7 100644
--- a/llvm/test/Transforms/IndVarSimplify/AMDGPU/addrspace-7-doesnt-crash.ll
+++ b/llvm/test/Transforms/IndVarSimplify/AMDGPU/addrspace-7-doesnt-crash.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt -passes=indvars -S < %s | FileCheck %s
-target triple = "amdgcn--amdpal"
+target triple = "amdgpu6.00--amdpal"
define void @f(ptr addrspace(7) %arg) {
; CHECK-LABEL: define void @f
diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/phi-with-incoming-from-load.ll b/llvm/test/Transforms/InstCombine/AMDGPU/phi-with-incoming-from-load.ll
index 481b89b2b3338..fe014cad824ee 100644
--- a/llvm/test/Transforms/InstCombine/AMDGPU/phi-with-incoming-from-load.ll
+++ b/llvm/test/Transforms/InstCombine/AMDGPU/phi-with-incoming-from-load.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -passes=instcombine -S -o - %s | FileCheck %s
-target triple = "amdgcn-amd-amdhsa"
+target triple = "amdgpu6.00-amd-amdhsa"
%double_double = type { double, double }
diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/select-from-load.ll b/llvm/test/Transforms/InstCombine/AMDGPU/select-from-load.ll
index e22fd040bdc2c..5fed9e82170c3 100644
--- a/llvm/test/Transforms/InstCombine/AMDGPU/select-from-load.ll
+++ b/llvm/test/Transforms/InstCombine/AMDGPU/select-from-load.ll
@@ -2,7 +2,7 @@
; RUN: opt -passes=instcombine -S -o - %s | FileCheck %s
; REQUIRES: amdgpu-registered-target
-target triple = "amdgcn-amd-amdhsa"
+target triple = "amdgpu7.00-amd-amdhsa"
%anon = type { i32, [8 x ptr], ptr }
diff --git a/llvm/test/Transforms/LICM/AMDGPU/buffer-rsrc-ptrs.ll b/llvm/test/Transforms/LICM/AMDGPU/buffer-rsrc-ptrs.ll
index 1d3a13bede799..51e2fb003d41b 100644
--- a/llvm/test/Transforms/LICM/AMDGPU/buffer-rsrc-ptrs.ll
+++ b/llvm/test/Transforms/LICM/AMDGPU/buffer-rsrc-ptrs.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt < %s -aa-pipeline=basic-aa,scoped-noalias-aa -passes=licm -S | FileCheck %s
-target triple = "amdgcn-amd-amdhsa"
+target triple = "amdgpu7.00-amd-amdhsa"
define void @hoistable_noalias(ptr addrspace(8) noalias %p, ptr addrspace(8) noalias %q, i32 %bound) {
; CHECK-LABEL: define void @hoistable_noalias
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/adjust-alloca-alignment.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/adjust-alloca-alignment.ll
index 69385c5e801f1..2014b81ba33fc 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/adjust-alloca-alignment.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/adjust-alloca-alignment.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -passes=load-store-vectorizer --mcpu=hawaii -mattr=-unaligned-access-mode,+max-private-element-size-16 < %s | FileCheck -check-prefixes=CHECK,ALIGNED %s
-; RUN: opt -S -passes=load-store-vectorizer --mcpu=hawaii -mattr=+unaligned-access-mode,+unaligned-scratch-access,+max-private-element-size-16 < %s | FileCheck -check-prefixes=CHECK,UNALIGNED %s
-; RUN: opt -S -passes='function(load-store-vectorizer)' --mcpu=hawaii -mattr=-unaligned-access-mode,+max-private-element-size-16 < %s | FileCheck -check-prefixes=CHECK,ALIGNED %s
-; RUN: opt -S -passes='function(load-store-vectorizer)' --mcpu=hawaii -mattr=+unaligned-access-mode,+unaligned-scratch-access,+max-private-element-size-16 < %s | FileCheck -check-prefixes=CHECK,UNALIGNED %s
+; RUN: opt -S -passes=load-store-vectorizer -mattr=-unaligned-access-mode,+max-private-element-size-16 < %s | FileCheck -check-prefixes=CHECK,ALIGNED %s
+; RUN: opt -S -passes=load-store-vectorizer -mattr=+unaligned-access-mode,+unaligned-scratch-access,+max-private-element-size-16 < %s | FileCheck -check-prefixes=CHECK,UNALIGNED %s
+; RUN: opt -S -passes='function(load-store-vectorizer)' -mattr=-unaligned-access-mode,+max-private-element-size-16 < %s | FileCheck -check-prefixes=CHECK,ALIGNED %s
+; RUN: opt -S -passes='function(load-store-vectorizer)' -mattr=+unaligned-access-mode,+unaligned-scratch-access,+max-private-element-size-16 < %s | FileCheck -check-prefixes=CHECK,UNALIGNED %s
-target triple = "amdgcn--"
+target triple = "amdgpu7.01--"
define amdgpu_kernel void @load_unknown_offset_align1_i8(ptr addrspace(1) noalias %out, i32 %offset) #0 {
; ALIGNED-LABEL: @load_unknown_offset_align1_i8(
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/dont-adjust-globalobj-alignment.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/dont-adjust-globalobj-alignment.ll
index 4486368290eaf..87e1c03e70038 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/dont-adjust-globalobj-alignment.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/dont-adjust-globalobj-alignment.ll
@@ -1,6 +1,6 @@
-; RUN: opt -S -passes=load-store-vectorizer --mcpu=hawaii -mattr=+unaligned-access-mode,+unaligned-scratch-access,+max-private-element-size-16 < %s | FileCheck --match-full-lines %s
+; RUN: opt -S -passes=load-store-vectorizer -mattr=+unaligned-access-mode,+unaligned-scratch-access,+max-private-element-size-16 < %s | FileCheck --match-full-lines %s
-target triple = "amdgcn--"
+target triple = "amdgpu7.01--"
@G = internal addrspace(5) global [8 x i16] undef, align 1
diff --git a/llvm/test/Transforms/LoopLoadElim/pr46854-adress-spaces.ll b/llvm/test/Transforms/LoopLoadElim/pr46854-adress-spaces.ll
index 6d4b031c930df..b03b4772b482a 100644
--- a/llvm/test/Transforms/LoopLoadElim/pr46854-adress-spaces.ll
+++ b/llvm/test/Transforms/LoopLoadElim/pr46854-adress-spaces.ll
@@ -3,7 +3,7 @@
; RUN: opt -passes='require<globals-aa>,loop-simplify,loop-load-elim' -S %s | FileCheck %s
-target triple = "amdgcn-amd-amdhsa"
+target triple = "amdgpu6.00-amd-amdhsa"
%struct.foo = type { %struct.pluto, i8, ptr, i32 }
%struct.pluto = type { i32, i32, i32, ptr, i32, i32, i32 }
diff --git a/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-icmpzero-mixed-ptr-width.ll b/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-icmpzero-mixed-ptr-width.ll
index 5418b6d10c5cb..6cb7700f3533d 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-icmpzero-mixed-ptr-width.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-icmpzero-mixed-ptr-width.ll
@@ -1,15 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
-; RUN: opt -passes=loop-reduce -S -mcpu=gfx942 %s | FileCheck %s
+; RUN: opt -passes=loop-reduce -S %s | FileCheck %s
;
; Verify that LSR produces well-typed icmp operands when ICmpZero uses a
; pointer-typed operand from a narrow address space (addrspace(5), 32-bit)
; but the chosen IV is wider (i64, from flat-pointer address uses).
-target triple = "amdgcn-amd-amdhsa"
+target triple = "amdgpu9.42-amd-amdhsa"
define amdgpu_kernel void @icmpzero_mixed_ptr_width(ptr addrspace(5) %scratch) {
; CHECK-LABEL: define amdgpu_kernel void @icmpzero_mixed_ptr_width(
-; CHECK-SAME: ptr addrspace(5) [[SCRATCH:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-SAME: ptr addrspace(5) [[SCRATCH:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
diff --git a/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-void-inseltpoison.ll b/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-void-inseltpoison.ll
index bd3e38c6c1060..de7e8d08079f3 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-void-inseltpoison.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-void-inseltpoison.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s
@array = external addrspace(4) constant [32 x [800 x i32]], align 4
diff --git a/llvm/test/Transforms/LoopUnroll/AMDGPU/scev-mul-expansion-cost.ll b/llvm/test/Transforms/LoopUnroll/AMDGPU/scev-mul-expansion-cost.ll
index c2bb5ef5e67a3..6abd5d37b1bfc 100644
--- a/llvm/test/Transforms/LoopUnroll/AMDGPU/scev-mul-expansion-cost.ll
+++ b/llvm/test/Transforms/LoopUnroll/AMDGPU/scev-mul-expansion-cost.ll
@@ -10,7 +10,7 @@
; AMDGPU is used because its i32 mul has a cost of 4,
; making the over-counting observable against the default budget of 4.
-target triple = "amdgcn-amd-amdhsa"
+target triple = "amdgpu7.00-amd-amdhsa"
; CHECK-LABEL: @offset_start_loop
; The loop should be runtime-unrolled 8x (prologue + main unrolled body).
diff --git a/llvm/test/Transforms/OpenMP/add_attributes_amdgcn.ll b/llvm/test/Transforms/OpenMP/add_attributes_amdgcn.ll
index db4cb4ecb4c4c..394dd5bf3c8da 100644
--- a/llvm/test/Transforms/OpenMP/add_attributes_amdgcn.ll
+++ b/llvm/test/Transforms/OpenMP/add_attributes_amdgcn.ll
@@ -1,7 +1,7 @@
; RUN: opt < %s -S -passes=openmp-opt-cgscc | FileCheck %s
; RUN: opt < %s -S -passes=openmp-opt-cgscc -openmp-ir-builder-optimistic-attributes | FileCheck %s --check-prefix=OPTIMISTIC
-target triple = "amdgcn-amd-amdhsa"
+target triple = "amdgpu7.00-amd-amdhsa"
define void @call_all(i64 %arg) {
call void @__kmpc_syncwarp(i64 %arg)
diff --git a/llvm/test/Transforms/OpenMP/barrier_removal.ll b/llvm/test/Transforms/OpenMP/barrier_removal.ll
index 56f730ccb4189..dbe2c2e8fe3cb 100644
--- a/llvm/test/Transforms/OpenMP/barrier_removal.ll
+++ b/llvm/test/Transforms/OpenMP/barrier_removal.ll
@@ -3,7 +3,7 @@
; RUN: opt < %s -S -passes=openmp-opt-cgscc | FileCheck %s --check-prefixes=CHECK,CGSCC
; REQUIRES: amdgpu-registered-target
-target triple = "amdgcn-amd-amdhsa"
+target triple = "amdgpu7.00-amd-amdhsa"
declare void @useI32(i32)
declare void @unknown()
diff --git a/llvm/test/Transforms/OpenMP/indirect_call_kernel_info_crash.ll b/llvm/test/Transforms/OpenMP/indirect_call_kernel_info_crash.ll
index cff8a0d978573..49f72f766e37b 100644
--- a/llvm/test/Transforms/OpenMP/indirect_call_kernel_info_crash.ll
+++ b/llvm/test/Transforms/OpenMP/indirect_call_kernel_info_crash.ll
@@ -1,5 +1,5 @@
; RUN: opt -S -passes=openmp-opt < %s
-target triple = "amdgcn-amd-amdhsa"
+target triple = "amdgpu7.00-amd-amdhsa"
%"struct.ompx::state::TeamStateTy" = type { %"struct.ompx::state::ICVStateTy", i32, i32, ptr }
%"struct.ompx::state::ICVStateTy" = type { i32, i32, i32, i32, i32, i32, i32 }
diff --git a/llvm/test/Transforms/OpenMP/spmdization_constant_prop.ll b/llvm/test/Transforms/OpenMP/spmdization_constant_prop.ll
index 3f996f1145b05..583f6a4bc18a0 100644
--- a/llvm/test/Transforms/OpenMP/spmdization_constant_prop.ll
+++ b/llvm/test/Transforms/OpenMP/spmdization_constant_prop.ll
@@ -8,7 +8,7 @@
; CHECK: store i32 1, ptr addrspace(3) @IsSPMDMode
; CHECK-NOT: store i32 0, ptr addrspace(3) @IsSPMDMode
;
-target triple = "amdgcn-amd-amdhsa"
+target triple = "amdgpu9.08-amd-amdhsa"
%struct.ident_t = type { i32, i32, i32, i32, ptr }
%struct.DeviceEnvironmentTy = type { i32, i32, i32, i32 }
@@ -277,16 +277,16 @@ declare void @__kmpc_parallel_60(ptr noundef readnone captures(none), i32 nounde
; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #10
-attributes #0 = { alwaysinline convergent norecurse nounwind "frame-pointer"="none" "kernel" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx908" "target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot2-insts,+dot3-insts,+dot4-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+flat-address-space,+gfx8-insts,+gfx9-insts,+mai-insts,+s-memrealtime,+s-memtime-inst" }
+attributes #0 = { alwaysinline convergent norecurse nounwind "frame-pointer"="none" "kernel" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot2-insts,+dot3-insts,+dot4-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+flat-address-space,+gfx8-insts,+gfx9-insts,+mai-insts,+s-memrealtime,+s-memtime-inst" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
-attributes #2 = { alwaysinline mustprogress nofree norecurse nosync nounwind willreturn memory(none) "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx908" "target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot2-insts,+dot3-insts,+dot4-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+flat-address-space,+gfx8-insts,+gfx9-insts,+mai-insts,+s-memrealtime,+s-memtime-inst" }
-attributes #3 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx908" "target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot2-insts,+dot3-insts,+dot4-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+flat-address-space,+gfx8-insts,+gfx9-insts,+mai-insts,+s-memrealtime,+s-memtime-inst" }
+attributes #2 = { alwaysinline mustprogress nofree norecurse nosync nounwind willreturn memory(none) "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot2-insts,+dot3-insts,+dot4-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+flat-address-space,+gfx8-insts,+gfx9-insts,+mai-insts,+s-memrealtime,+s-memtime-inst" }
+attributes #3 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot2-insts,+dot3-insts,+dot4-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+flat-address-space,+gfx8-insts,+gfx9-insts,+mai-insts,+s-memrealtime,+s-memtime-inst" }
attributes #4 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #5 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
attributes #6 = { convergent nocallback nofree nounwind willreturn }
-attributes #7 = { convergent mustprogress noinline nounwind willreturn "frame-pointer"="none" "llvm.assume"="ompx_aligned_barrier,ompx_no_call_asm,ompx_no_call_asm" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx908" "target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot2-insts,+dot3-insts,+dot4-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+flat-address-space,+gfx8-insts,+gfx9-insts,+mai-insts,+s-memrealtime,+s-memtime-inst" }
-attributes #8 = { convergent nounwind "frame-pointer"="none" "llvm.assume"="ompx_no_call_asm,ompx_no_call_asm" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx908" "target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot2-insts,+dot3-insts,+dot4-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+flat-address-space,+gfx8-insts,+gfx9-insts,+mai-insts,+s-memrealtime,+s-memtime-inst" }
-attributes #9 = { nounwind "frame-pointer"="none" "llvm.assume"="ompx_no_call_asm,ompx_no_call_asm" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx908" "target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot2-insts,+dot3-insts,+dot4-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+flat-address-space,+gfx8-insts,+gfx9-insts,+mai-insts,+s-memrealtime,+s-memtime-inst" }
+attributes #7 = { convergent mustprogress noinline nounwind willreturn "frame-pointer"="none" "llvm.assume"="ompx_aligned_barrier,ompx_no_call_asm,ompx_no_call_asm" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot2-insts,+dot3-insts,+dot4-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+flat-address-space,+gfx8-insts,+gfx9-insts,+mai-insts,+s-memrealtime,+s-memtime-inst" }
+attributes #8 = { convergent nounwind "frame-pointer"="none" "llvm.assume"="ompx_no_call_asm,ompx_no_call_asm" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot2-insts,+dot3-insts,+dot4-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+flat-address-space,+gfx8-insts,+gfx9-insts,+mai-insts,+s-memrealtime,+s-memtime-inst" }
+attributes #9 = { nounwind "frame-pointer"="none" "llvm.assume"="ompx_no_call_asm,ompx_no_call_asm" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dot1-insts,+dot2-insts,+dot3-insts,+dot4-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+flat-address-space,+gfx8-insts,+gfx9-insts,+mai-insts,+s-memrealtime,+s-memtime-inst" }
attributes #10 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
attributes #11 = { nounwind }
attributes #12 = { convergent nounwind "llvm.assume"="ompx_aligned_barrier,ompx_no_call_asm" }
diff --git a/llvm/test/Transforms/OpenMP/spmdization_kernel_env_dep.ll b/llvm/test/Transforms/OpenMP/spmdization_kernel_env_dep.ll
index de994a02bf747..ff43d69675ef8 100644
--- a/llvm/test/Transforms/OpenMP/spmdization_kernel_env_dep.ll
+++ b/llvm/test/Transforms/OpenMP/spmdization_kernel_env_dep.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals
-; RUN: opt --mtriple=amdgpu-amd-amdhsa -S -passes=openmp-opt < %s | FileCheck %s --check-prefixes=AMDGPU
+; RUN: opt -S -passes=openmp-opt < %s | FileCheck %s --check-prefixes=AMDGPU
-target triple = "amdgcn-amd-amdhsa"
+target triple = "amdgpu7.00-amd-amdhsa"
%struct.KernelEnvironmentTy = type { %struct.ConfigurationEnvironmentTy.8, ptr, ptr }
%struct.ConfigurationEnvironmentTy.8 = type { i8, i8, i8, i32, i32, i32, i32, i32, i32 }
diff --git a/llvm/test/Transforms/OpenMP/value-simplify-openmp-opt.ll b/llvm/test/Transforms/OpenMP/value-simplify-openmp-opt.ll
index 2842dfd030b11..752385bfa3e89 100644
--- a/llvm/test/Transforms/OpenMP/value-simplify-openmp-opt.ll
+++ b/llvm/test/Transforms/OpenMP/value-simplify-openmp-opt.ll
@@ -2,7 +2,7 @@
; RUN: opt -aa-pipeline=basic-aa -passes=openmp-opt -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,TUNIT
; RUN: opt -aa-pipeline=basic-aa -passes=openmp-opt-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,CGSCC
-target triple = "amdgcn-amd-amdhsa"
+target triple = "amdgpu7.00-amd-amdhsa"
%struct.ConfigurationEnvironmentTy = type { i8, i8, i8, i32, i32, i32, i32, i32, i32 }
%struct.KernelEnvironmentTy = type { %struct.ConfigurationEnvironmentTy, ptr, ptr }
diff --git a/llvm/test/Transforms/PGOProfile/amdgpu-disable-value-profiling.ll b/llvm/test/Transforms/PGOProfile/amdgpu-disable-value-profiling.ll
index 21b1d68004b13..9cb0fd47210e0 100644
--- a/llvm/test/Transforms/PGOProfile/amdgpu-disable-value-profiling.ll
+++ b/llvm/test/Transforms/PGOProfile/amdgpu-disable-value-profiling.ll
@@ -4,7 +4,7 @@
; RUN: opt < %s -passes=pgo-instr-gen -S | FileCheck %s
-target triple = "amdgcn-amd-amdhsa"
+target triple = "amdgpu7.00-amd-amdhsa"
@fptr = addrspace(1) global ptr null, align 8
diff --git a/llvm/test/Transforms/PhaseOrdering/varargs.ll b/llvm/test/Transforms/PhaseOrdering/varargs.ll
index 2a5ee4746e484..de286755f07b1 100644
--- a/llvm/test/Transforms/PhaseOrdering/varargs.ll
+++ b/llvm/test/Transforms/PhaseOrdering/varargs.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
-; RUN: opt -mtriple=amdgpu-- -S -passes='lto<O2>' < %s | FileCheck %s
-target triple = "amdgcn-amd-amdhsa"
+; RUN: opt -S -passes='lto<O2>' < %s | FileCheck %s
+target triple = "amdgpu7.00-amd-amdhsa"
; REQUIRES: amdgpu-registered-target
diff --git a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/lower-gep.ll b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/lower-gep.ll
index 78c889c5bd127..dd30caf8eca11 100644
--- a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/lower-gep.ll
+++ b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/lower-gep.ll
@@ -2,7 +2,7 @@
; RUN: opt < %s -passes='separate-const-offset-from-gep<lower-gep>' \
; RUN: -reassociate-geps-verify-no-dead-code -S | FileCheck %s
-target triple = "amdgcn-amd-amdhsa"
+target triple = "amdgpu7.00-amd-amdhsa"
%struct.Packed = type <{ [3 x i32], [8 x i64] }> ; <> means packed
diff --git a/llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/pr23975.ll b/llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/pr23975.ll
index 420c22219446c..1b90ead288fe6 100644
--- a/llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/pr23975.ll
+++ b/llvm/test/Transforms/StraightLineStrengthReduce/AMDGPU/pr23975.ll
@@ -1,7 +1,7 @@
; RUN: opt < %s -passes=slsr -S | FileCheck %s
; RUN: opt < %s -passes='slsr' -S | FileCheck %s
-target triple = "amdgcn--"
+target triple = "amdgpu6.00--"
%struct.Matrix4x4 = type { [4 x [4 x float]] }
diff --git a/llvm/test/Transforms/StructurizeCFG/hoist-zerocost-nested.ll b/llvm/test/Transforms/StructurizeCFG/hoist-zerocost-nested.ll
index c349709ea0f05..70d835a8aaecb 100644
--- a/llvm/test/Transforms/StructurizeCFG/hoist-zerocost-nested.ll
+++ b/llvm/test/Transforms/StructurizeCFG/hoist-zerocost-nested.ll
@@ -1,6 +1,6 @@
; RUN: opt -passes=fix-irreducible,unify-loop-exits,structurizecfg -S %s | FileCheck %s
;
-target triple = "amdgcn-amd-amdhsa"
+target triple = "amdgpu7.00-amd-amdhsa"
;
; Reduced from rocPRIM block_sort_kernel compiled with code coverage.
; The sort comparator `operator<` for custom_type uses nested short-circuit:
diff --git a/llvm/test/Transforms/StructurizeCFG/rebuild-ssa-infinite-loop-inseltpoison.ll b/llvm/test/Transforms/StructurizeCFG/rebuild-ssa-infinite-loop-inseltpoison.ll
index e7203bb3139bd..3020df74c9fe9 100644
--- a/llvm/test/Transforms/StructurizeCFG/rebuild-ssa-infinite-loop-inseltpoison.ll
+++ b/llvm/test/Transforms/StructurizeCFG/rebuild-ssa-infinite-loop-inseltpoison.ll
@@ -4,7 +4,7 @@
; rebuildSSA routine, where we were iterating over an instruction's uses while
; modifying the use list, without taking care to do this safely.
-target triple = "amdgcn--"
+target triple = "amdgpu6.00--"
define amdgpu_vs void @wrapper(i32 inreg %arg, i32 %arg1) {
main_body:
diff --git a/llvm/test/Transforms/StructurizeCFG/rebuild-ssa-infinite-loop.ll b/llvm/test/Transforms/StructurizeCFG/rebuild-ssa-infinite-loop.ll
index 6bc60614ecd17..7986374f9a78d 100644
--- a/llvm/test/Transforms/StructurizeCFG/rebuild-ssa-infinite-loop.ll
+++ b/llvm/test/Transforms/StructurizeCFG/rebuild-ssa-infinite-loop.ll
@@ -4,7 +4,7 @@
; rebuildSSA routine, where we were iterating over an instruction's uses while
; modifying the use list, without taking care to do this safely.
-target triple = "amdgcn--"
+target triple = "amdgpu6.00--"
define amdgpu_vs void @wrapper(i32 inreg %arg, i32 %arg1) {
main_body:
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_no_merge_comments.ll b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_no_merge_comments.ll
index fa6e521ae653b..14c1cb3002556 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_no_merge_comments.ll
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_no_merge_comments.ll
@@ -2,7 +2,7 @@
; RUN: llc %S/amdgpu_no_merge_comments-O0.s | FileCheck -check-prefixes=GCN,GFX9-O0 %s
; RUN: llc %S/amdgpu_no_merge_comments-O3.s | FileCheck -check-prefixes=GCN,GFX9-O3 %s
-target triple = "amdgcn--"
+target triple = "amdgpu9.00--"
define hidden i32 @main(i32 %a) {
%add = add i32 %a, %a
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_no_merge_comments.ll.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_no_merge_comments.ll.expected
index 6cc7cb84dfc19..dfa2d391bffd0 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_no_merge_comments.ll.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_no_merge_comments.ll.expected
@@ -3,7 +3,7 @@
; RUN: llc %S/amdgpu_no_merge_comments-O0.s | FileCheck -check-prefixes=GCN,GFX9-O0 %s
; RUN: llc %S/amdgpu_no_merge_comments-O3.s | FileCheck -check-prefixes=GCN,GFX9-O3 %s
-target triple = "amdgcn--"
+target triple = "amdgpu9.00--"
define hidden i32 @main(i32 %a) {
; GFX9-O0-LABEL: main:
diff --git a/llvm/test/tools/llvm-objdump/ELF/AMDGPU/source-lines.ll b/llvm/test/tools/llvm-objdump/ELF/AMDGPU/source-lines.ll
index cf61f20225bfe..65e3b3218ffbd 100644
--- a/llvm/test/tools/llvm-objdump/ELF/AMDGPU/source-lines.ll
+++ b/llvm/test/tools/llvm-objdump/ELF/AMDGPU/source-lines.ll
@@ -36,9 +36,7 @@
; SOURCE: ; }
; SOURCE-NEXT: s_endpgm
-; ModuleID = 'source-lines.cl'
source_filename = "source-lines.cl"
-target triple = "amdgcn-amd-amdhsa"
; Function Attrs: noinline nounwind
define amdgpu_kernel void @source_lines_test(ptr addrspace(1) %Out) #0 !dbg !7 !kernel_arg_addr_space !12 !kernel_arg_access_qual !13 !kernel_arg_type !14 !kernel_arg_base_type !14 !kernel_arg_type_qual !15 {
diff --git a/llvm/test/tools/llvm-objdump/Offloading/Inputs/binary.yaml b/llvm/test/tools/llvm-objdump/Offloading/Inputs/binary.yaml
index 703c93b24dcc0..95e24d2c593b2 100644
--- a/llvm/test/tools/llvm-objdump/Offloading/Inputs/binary.yaml
+++ b/llvm/test/tools/llvm-objdump/Offloading/Inputs/binary.yaml
@@ -4,14 +4,14 @@ Members:
OffloadKind: OFK_OpenMP
String:
- Key: "triple"
- Value: "amdgcn-amd-amdhsa"
+ Value: "amdgpu9.08-amd-amdhsa"
- Key: "arch"
Value: "gfx908"
- ImageKind: IMG_Bitcode
OffloadKind: OFK_OpenMP
String:
- Key: "triple"
- Value: "amdgcn-amd-amdhsa"
+ Value: "amdgpu9.0a-amd-amdhsa"
- Key: "arch"
Value: "gfx90a"
- ImageKind: IMG_Cubin
diff --git a/llvm/test/tools/llvm-objdump/Offloading/coff.test b/llvm/test/tools/llvm-objdump/Offloading/coff.test
index 5bec7d60cb83e..86ba900b7a6ee 100644
--- a/llvm/test/tools/llvm-objdump/Offloading/coff.test
+++ b/llvm/test/tools/llvm-objdump/Offloading/coff.test
@@ -20,14 +20,14 @@ symbols:
# CHECK-NEXT:OFFLOADING IMAGE [0]:
# CHECK-NEXT:kind llvm ir
# CHECK-NEXT:arch gfx908
-# CHECK-NEXT:triple amdgcn-amd-amdhsa
+# CHECK-NEXT:triple amdgpu9.08-amd-amdhsa
# CHECK-NEXT:producer openmp
# CHECK-NEXT:image size 0 bytes
# CHECK-EMPTY:
# CHECK-NEXT:OFFLOADING IMAGE [1]:
# CHECK-NEXT:kind llvm ir
# CHECK-NEXT:arch gfx90a
-# CHECK-NEXT:triple amdgcn-amd-amdhsa
+# CHECK-NEXT:triple amdgpu9.0a-amd-amdhsa
# CHECK-NEXT:producer openmp
# CHECK-NEXT:image size 0 bytes
# CHECK-EMPTY:
diff --git a/llvm/test/tools/llvm-objdump/Offloading/elf.test b/llvm/test/tools/llvm-objdump/Offloading/elf.test
index 3064286b9fea1..9b8fed306c869 100644
--- a/llvm/test/tools/llvm-objdump/Offloading/elf.test
+++ b/llvm/test/tools/llvm-objdump/Offloading/elf.test
@@ -29,14 +29,14 @@ Sections:
# CHECK:OFFLOADING IMAGE [0]:
# CHECK-NEXT:kind llvm ir
# CHECK-NEXT:arch gfx908
-# CHECK-NEXT:triple amdgcn-amd-amdhsa
+# CHECK-NEXT:triple amdgpu9.08-amd-amdhsa
# CHECK-NEXT:producer openmp
# CHECK-NEXT:image size 0 bytes
# CHECK-EMPTY:
# CHECK-NEXT:OFFLOADING IMAGE [1]:
# CHECK-NEXT:kind llvm ir
# CHECK-NEXT:arch gfx90a
-# CHECK-NEXT:triple amdgcn-amd-amdhsa
+# CHECK-NEXT:triple amdgpu9.0a-amd-amdhsa
# CHECK-NEXT:producer openmp
# CHECK-NEXT:image size 0 bytes
# CHECK-EMPTY:
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