[llvm] [UniformityAnalysis] Make divergent-exit cycle print order deterministic (PR #210107)

Fangrui Song via llvm-commits llvm-commits at lists.llvm.org
Thu Jul 16 09:43:30 PDT 2026


https://github.com/MaskRay created https://github.com/llvm/llvm-project/pull/210107

Once the set spills to the heap its iteration order follows allocation
addresses, so the printed order is nondeterministic.

Fix https://reviews.llvm.org/D130746 ("RFC: Uniformity Analysis for Irreducible Control Flow")

>From b116eeadddaa4ed0ce43e70691b92d7794ab2e1f Mon Sep 17 00:00:00 2001
From: Fangrui Song <i at maskray.me>
Date: Thu, 16 Jul 2026 01:13:08 -0700
Subject: [PATCH] [UniformityAnalysis] Make divergent-exit cycle print order
 deterministic

Once the set spills to the heap its iteration order follows allocation
addresses, so the printed order is nondeterministic.

Fix https://reviews.llvm.org/D130746 ("RFC: Uniformity Analysis for Irreducible Control Flow")
---
 llvm/include/llvm/ADT/GenericUniformityImpl.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/llvm/include/llvm/ADT/GenericUniformityImpl.h b/llvm/include/llvm/ADT/GenericUniformityImpl.h
index 630476daf2cd6..baf2d8951a615 100644
--- a/llvm/include/llvm/ADT/GenericUniformityImpl.h
+++ b/llvm/include/llvm/ADT/GenericUniformityImpl.h
@@ -48,6 +48,7 @@
 
 #include "llvm/ADT/DenseSet.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/SparseBitVector.h"
 #include "llvm/ADT/StringExtras.h"
@@ -462,7 +463,7 @@ template <typename ContextT> class GenericUniformityAnalysisImpl {
   const DominatorTreeT &DT;
 
   // Recognized cycles with divergent exits.
-  SmallPtrSet<const CycleT *, 16> DivergentExitCycles;
+  SmallSetVector<const CycleT *, 8> DivergentExitCycles;
 
   // Cycles assumed to be divergent.
   //
@@ -918,7 +919,7 @@ void GenericUniformityAnalysisImpl<ContextT>::propagateCycleExitDivergence(
   LLVM_DEBUG(dbgs() << "\tOuter-most exiting cycle: "
                     << Context.print(OuterDivCycle->getHeader()) << "\n");
 
-  if (!DivergentExitCycles.insert(OuterDivCycle).second)
+  if (!DivergentExitCycles.insert(OuterDivCycle))
     return;
 
   // Exit divergence does not matter if the cycle itself is assumed to



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