[llvm] [RISCV][P-ext] Make undef vectors Legal. (PR #210106)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 16 09:42:12 PDT 2026
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/210106
Add a few additional isel patterns to avoid false dependencies. We may want to enable the BreakFalseDep pass in the future.
>From de40bf39d651f06f691f1cf7be158b7b9468b825 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 16 Jul 2026 09:27:01 -0700
Subject: [PATCH 1/2] Pre-commit tests
---
llvm/test/CodeGen/RISCV/rvp-simd-32.ll | 29 ++++++++++++++++++
llvm/test/CodeGen/RISCV/rvp-simd-64.ll | 42 ++++++++++++++++++++++++++
2 files changed, 71 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
index 6d1bd5a336d38..806e346d55226 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
@@ -2732,3 +2732,32 @@ define <2 x i16> @test_psabs_v2i16(<2 x i16> %a) {
%res = call <2 x i16> @llvm.riscv.psabs.v2i16(<2 x i16> %a)
ret <2 x i16> %res
}
+
+define <4 x i8> @test_undef_v4i8() {
+; RV32-LABEL: test_undef_v4i8:
+; RV32: # %bb.0:
+; RV32-NEXT: li a0, 0
+; RV32-NEXT: li a1, 0
+; RV32-NEXT: ppaire.db a0, a0, a0
+; RV32-NEXT: pack a0, a0, a1
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_undef_v4i8:
+; RV64: # %bb.0:
+; RV64-NEXT: li a0, 0
+; RV64-NEXT: ret
+ ret <4 x i8> undef
+}
+
+define <2 x i16> @test_undef_v2i16() {
+; RV32-LABEL: test_undef_v2i16:
+; RV32: # %bb.0:
+; RV32-NEXT: pack a0, zero, zero
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_undef_v2i16:
+; RV64: # %bb.0:
+; RV64-NEXT: li a0, 0
+; RV64-NEXT: ret
+ ret <2 x i16> undef
+}
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
index 1355da7d5fe8a..5c0fa7f21eb55 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
@@ -5997,3 +5997,45 @@ define <2 x i32> @test_return_zero() {
; RV64-NEXT: ret
ret <2 x i32> splat (i32 0)
}
+
+define <8 x i8> @test_undef_v8i8() {
+; RV32-LABEL: test_undef_v8i8:
+; RV32: # %bb.0:
+; RV32-NEXT: li a1, 0
+; RV32-NEXT: li a0, 0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_undef_v8i8:
+; RV64: # %bb.0:
+; RV64-NEXT: li a0, 0
+; RV64-NEXT: ret
+ ret <8 x i8> undef
+}
+
+define <4 x i16> @test_undef_v4i16() {
+; RV32-LABEL: test_undef_v4i16:
+; RV32: # %bb.0:
+; RV32-NEXT: li a1, 0
+; RV32-NEXT: li a0, 0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_undef_v4i16:
+; RV64: # %bb.0:
+; RV64-NEXT: li a0, 0
+; RV64-NEXT: ret
+ ret <4 x i16> undef
+}
+
+define <2 x i32> @test_undef_v2i32() {
+; RV32-LABEL: test_undef_v2i32:
+; RV32: # %bb.0:
+; RV32-NEXT: li a1, 0
+; RV32-NEXT: li a0, 0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_undef_v2i32:
+; RV64: # %bb.0:
+; RV64-NEXT: li a0, 0
+; RV64-NEXT: ret
+ ret <2 x i32> undef
+}
>From 5718b49d582a37f01ee7e6b1ea48b38439654ddc Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 16 Jul 2026 09:27:38 -0700
Subject: [PATCH 2/2] [RISCV][P-ext] Make undef vectors Legal.
Add a few additional isel patterns to avoid false dependencies.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 ++
llvm/lib/Target/RISCV/RISCVInstrInfoP.td | 12 +++++++
llvm/test/CodeGen/RISCV/rvp-simd-32.ll | 27 ++++----------
llvm/test/CodeGen/RISCV/rvp-simd-64.ll | 39 +++++----------------
4 files changed, 29 insertions(+), 51 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 0063b429f516e..e174d9fdbf309 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -632,6 +632,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::BSWAP, VT, Legal);
}
}
+ setOperationAction(ISD::UNDEF, VTs, Legal);
setOperationAction(ISD::SPLAT_VECTOR, VTs, Legal);
setOperationAction(ISD::BUILD_VECTOR, VTs, Legal);
setOperationAction(ISD::SCALAR_TO_VECTOR, VTs, Legal);
@@ -668,6 +669,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
}
}
+ setOperationAction(ISD::UNDEF, P64VecVTs, Legal);
setOperationAction({ISD::LOAD, ISD::STORE}, P64VecVTs, Custom);
setOperationAction(ISD::BITCAST, P64VecVTs, Custom);
setOperationAction({ISD::ADD, ISD::SUB}, P64VecVTs, Legal);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index e49c861ae800b..780cb490052f5 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -2820,6 +2820,18 @@ let append Predicates = [IsRV64] in {
def : Pat<(v4i16 (riscv_punzipo (v4i16 GPR:$rs1), (v4i16 GPR:$rs2))),
(UNZIP16HP GPR:$rs1, GPR:$rs2)>;
+ // Match undef to X0 to avoid false dependency.
+ // FIXME: Match operand 0 too?
+ // FIXME: Enable BreakFalseDep pass?
+ def : Pat<(v8i8 (riscv_punzipe (v8i8 GPR:$rs1), (v8i8 undef))),
+ (UNZIP8P GPR:$rs1, (v8i8 X0))>;
+ def : Pat<(v8i8 (riscv_punzipo (v8i8 GPR:$rs1), (v8i8 undef))),
+ (UNZIP8HP GPR:$rs1, (v8i8 X0))>;
+ def : Pat<(v4i16 (riscv_punzipe (v4i16 GPR:$rs1), (v4i16 undef))),
+ (UNZIP16P GPR:$rs1, (v4i16 X0))>;
+ def : Pat<(v4i16 (riscv_punzipo (v4i16 GPR:$rs1), (v4i16 undef))),
+ (UNZIP16HP GPR:$rs1, (v4i16 X0))>;
+
// Packed zip.
def : Pat<(v8i8 (riscv_pzip (v8i8 GPR:$rs1), (v8i8 GPR:$rs2))),
(ZIP8P GPR:$rs1, GPR:$rs2)>;
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
index 806e346d55226..a490494f7a464 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
@@ -2734,30 +2734,15 @@ define <2 x i16> @test_psabs_v2i16(<2 x i16> %a) {
}
define <4 x i8> @test_undef_v4i8() {
-; RV32-LABEL: test_undef_v4i8:
-; RV32: # %bb.0:
-; RV32-NEXT: li a0, 0
-; RV32-NEXT: li a1, 0
-; RV32-NEXT: ppaire.db a0, a0, a0
-; RV32-NEXT: pack a0, a0, a1
-; RV32-NEXT: ret
-;
-; RV64-LABEL: test_undef_v4i8:
-; RV64: # %bb.0:
-; RV64-NEXT: li a0, 0
-; RV64-NEXT: ret
+; CHECK-LABEL: test_undef_v4i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: ret
ret <4 x i8> undef
}
define <2 x i16> @test_undef_v2i16() {
-; RV32-LABEL: test_undef_v2i16:
-; RV32: # %bb.0:
-; RV32-NEXT: pack a0, zero, zero
-; RV32-NEXT: ret
-;
-; RV64-LABEL: test_undef_v2i16:
-; RV64: # %bb.0:
-; RV64-NEXT: li a0, 0
-; RV64-NEXT: ret
+; CHECK-LABEL: test_undef_v2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: ret
ret <2 x i16> undef
}
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
index 5c0fa7f21eb55..f49d66019458d 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
@@ -5999,43 +5999,22 @@ define <2 x i32> @test_return_zero() {
}
define <8 x i8> @test_undef_v8i8() {
-; RV32-LABEL: test_undef_v8i8:
-; RV32: # %bb.0:
-; RV32-NEXT: li a1, 0
-; RV32-NEXT: li a0, 0
-; RV32-NEXT: ret
-;
-; RV64-LABEL: test_undef_v8i8:
-; RV64: # %bb.0:
-; RV64-NEXT: li a0, 0
-; RV64-NEXT: ret
+; CHECK-LABEL: test_undef_v8i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: ret
ret <8 x i8> undef
}
define <4 x i16> @test_undef_v4i16() {
-; RV32-LABEL: test_undef_v4i16:
-; RV32: # %bb.0:
-; RV32-NEXT: li a1, 0
-; RV32-NEXT: li a0, 0
-; RV32-NEXT: ret
-;
-; RV64-LABEL: test_undef_v4i16:
-; RV64: # %bb.0:
-; RV64-NEXT: li a0, 0
-; RV64-NEXT: ret
+; CHECK-LABEL: test_undef_v4i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: ret
ret <4 x i16> undef
}
define <2 x i32> @test_undef_v2i32() {
-; RV32-LABEL: test_undef_v2i32:
-; RV32: # %bb.0:
-; RV32-NEXT: li a1, 0
-; RV32-NEXT: li a0, 0
-; RV32-NEXT: ret
-;
-; RV64-LABEL: test_undef_v2i32:
-; RV64: # %bb.0:
-; RV64-NEXT: li a0, 0
-; RV64-NEXT: ret
+; CHECK-LABEL: test_undef_v2i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: ret
ret <2 x i32> undef
}
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