[llvm] X86: Add pattern for optimized BLSIC IR form (PR #209814)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 16 09:42:07 PDT 2026
https://github.com/Logans-olo updated https://github.com/llvm/llvm-project/pull/209814
>From cdc8cf077b56c58abde486ad8a4a6a72c3a14881 Mon Sep 17 00:00:00 2001
From: Logan Solonche <logan.s at covergenius.com>
Date: Wed, 15 Jul 2026 12:00:19 -0400
Subject: [PATCH 1/6] X86: Add pattern for optimized BLSIC IR form
Add DAG pattern to recognize the optimized IR form of BLSIC:
(xor (and x, -x), -1)
This matches the IR form produced after InstCombine optimizations,
fixing code generation regression from issue #209718.
---
llvm/lib/Target/X86/X86InstrTBM.td | 5 +++
llvm/test/CodeGen/X86/tbm-blsic-patterns.ll | 40 +++++++++++++++++++++
2 files changed, 45 insertions(+)
create mode 100644 llvm/test/CodeGen/X86/tbm-blsic-patterns.ll
diff --git a/llvm/lib/Target/X86/X86InstrTBM.td b/llvm/lib/Target/X86/X86InstrTBM.td
index 09200f0c1a9f6..a324925dc46cb 100644
--- a/llvm/lib/Target/X86/X86InstrTBM.td
+++ b/llvm/lib/Target/X86/X86InstrTBM.td
@@ -125,6 +125,11 @@ let Predicates = [HasTBM] in {
def : Pat<(or GR64:$src, (add GR64:$src, -1)),
(BLSFILL64rr GR64:$src)>;
+ def : Pat<(xor (and GR32:$src, (sub 0, GR32:$src)), -1),
+ (BLSIC32rr GR32:$src)>;
+ def : Pat<(xor (and GR64:$src, (sub 0, GR64:$src)), -1),
+ (BLSIC64rr GR64:$src)>;
+
def : Pat<(or (not GR32:$src), (add GR32:$src, -1)),
(BLSIC32rr GR32:$src)>;
def : Pat<(or (not GR64:$src), (add GR64:$src, -1)),
diff --git a/llvm/test/CodeGen/X86/tbm-blsic-patterns.ll b/llvm/test/CodeGen/X86/tbm-blsic-patterns.ll
new file mode 100644
index 0000000000000..98370869c5073
--- /dev/null
+++ b/llvm/test/CodeGen/X86/tbm-blsic-patterns.ll
@@ -0,0 +1,40 @@
+; RUN: llc -mattr=+tbm < %s | FileCheck %s
+
+target triple = "x86_64-unknown-linux-gnu"
+
+; CHECK-LABEL: test_blsic_original
+; CHECK: blsicl
+define i32 @test_blsic_original(i32 %x) {
+ %_2 = xor i32 %x, -1
+ %_0.i = add i32 %x, -1
+ %_0 = or i32 %_0.i, %_2
+ ret i32 %_0
+}
+
+; CHECK-LABEL: test_blsic_optimized
+; CHECK: blsicl
+define i32 @test_blsic_optimized(i32 %x) {
+ %1 = sub i32 0, %x
+ %2 = and i32 %x, %1
+ %3 = xor i32 %2, -1
+ ret i32 %3
+}
+
+; 64-bit versions
+; CHECK-LABEL: test_blsic_64_original
+; CHECK: blsicq
+define i64 @test_blsic_64_original(i64 %x) {
+ %_2 = xor i64 %x, -1
+ %_0.i = add i64 %x, -1
+ %_0 = or i64 %_0.i, %_2
+ ret i64 %_0
+}
+
+; CHECK-LABEL: test_blsic_64_optimized
+; CHECK: blsicq
+define i64 @test_blsic_64_optimized(i64 %x) {
+ %1 = sub i64 0, %x
+ %2 = and i64 %x, %1
+ %3 = xor i64 %2, -1
+ ret i64 %3
+}
>From 7174584d5908ec13a3023601a30511014483396e Mon Sep 17 00:00:00 2001
From: Logan Solonche <lsolonch at purdue.edu>
Date: Wed, 15 Jul 2026 13:37:40 -0400
Subject: [PATCH 2/6] Remove new testing file, and add tests as part of
existing file
---
llvm/test/CodeGen/X86/tbm-blsic-patterns.ll | 40 --------------------
llvm/test/CodeGen/X86/tbm_patterns.ll | 41 +++++++++++++++++++++
2 files changed, 41 insertions(+), 40 deletions(-)
delete mode 100644 llvm/test/CodeGen/X86/tbm-blsic-patterns.ll
diff --git a/llvm/test/CodeGen/X86/tbm-blsic-patterns.ll b/llvm/test/CodeGen/X86/tbm-blsic-patterns.ll
deleted file mode 100644
index 98370869c5073..0000000000000
--- a/llvm/test/CodeGen/X86/tbm-blsic-patterns.ll
+++ /dev/null
@@ -1,40 +0,0 @@
-; RUN: llc -mattr=+tbm < %s | FileCheck %s
-
-target triple = "x86_64-unknown-linux-gnu"
-
-; CHECK-LABEL: test_blsic_original
-; CHECK: blsicl
-define i32 @test_blsic_original(i32 %x) {
- %_2 = xor i32 %x, -1
- %_0.i = add i32 %x, -1
- %_0 = or i32 %_0.i, %_2
- ret i32 %_0
-}
-
-; CHECK-LABEL: test_blsic_optimized
-; CHECK: blsicl
-define i32 @test_blsic_optimized(i32 %x) {
- %1 = sub i32 0, %x
- %2 = and i32 %x, %1
- %3 = xor i32 %2, -1
- ret i32 %3
-}
-
-; 64-bit versions
-; CHECK-LABEL: test_blsic_64_original
-; CHECK: blsicq
-define i64 @test_blsic_64_original(i64 %x) {
- %_2 = xor i64 %x, -1
- %_0.i = add i64 %x, -1
- %_0 = or i64 %_0.i, %_2
- ret i64 %_0
-}
-
-; CHECK-LABEL: test_blsic_64_optimized
-; CHECK: blsicq
-define i64 @test_blsic_64_optimized(i64 %x) {
- %1 = sub i64 0, %x
- %2 = and i64 %x, %1
- %3 = xor i64 %2, -1
- ret i64 %3
-}
diff --git a/llvm/test/CodeGen/X86/tbm_patterns.ll b/llvm/test/CodeGen/X86/tbm_patterns.ll
index e595803efdfca..d496b5075b8ab 100644
--- a/llvm/test/CodeGen/X86/tbm_patterns.ll
+++ b/llvm/test/CodeGen/X86/tbm_patterns.ll
@@ -909,6 +909,47 @@ define i64 @test_x86_tbm_blsic_u64_sle(i64 %a, i64 %b, i64 %c) nounwind {
ret i64 %t4
}
+; RUN: llc -mattr=+tbm < %s | FileCheck %s
+
+target triple = "x86_64-unknown-linux-gnu"
+
+; CHECK-LABEL: test_blsic_original
+; CHECK: blsicl
+define i32 @test_blsic_original(i32 %x) {
+ %_2 = xor i32 %x, -1
+ %_0.i = add i32 %x, -1
+ %_0 = or i32 %_0.i, %_2
+ ret i32 %_0
+}
+
+; CHECK-LABEL: test_blsic_optimized
+; CHECK: blsicl
+define i32 @test_blsic_optimized(i32 %x) {
+ %1 = sub i32 0, %x
+ %2 = and i32 %x, %1
+ %3 = xor i32 %2, -1
+ ret i32 %3
+}
+
+; 64-bit versions
+; CHECK-LABEL: test_blsic_64_original
+; CHECK: blsicq
+define i64 @test_blsic_64_original(i64 %x) {
+ %_2 = xor i64 %x, -1
+ %_0.i = add i64 %x, -1
+ %_0 = or i64 %_0.i, %_2
+ ret i64 %_0
+}
+
+; CHECK-LABEL: test_blsic_64_optimized
+; CHECK: blsicq
+define i64 @test_blsic_64_optimized(i64 %x) {
+ %1 = sub i64 0, %x
+ %2 = and i64 %x, %1
+ %3 = xor i64 %2, -1
+ ret i64 %3
+}
+
define i32 @test_x86_tbm_t1mskc_u32(i32 %a) nounwind {
; CHECK-LABEL: test_x86_tbm_t1mskc_u32:
; CHECK: # %bb.0:
>From ed466b701ca3fc475271781beb0f83856ec704b6 Mon Sep 17 00:00:00 2001
From: Logan Solonche <lsolonch at purdue.edu>
Date: Wed, 15 Jul 2026 15:06:00 -0400
Subject: [PATCH 3/6] Resolve issues: remove target triple and RUN from
mid-file. Also update test block labels to pass.
---
llvm/test/CodeGen/X86/tbm_patterns.ll | 29 +++++++++++++--------------
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/llvm/test/CodeGen/X86/tbm_patterns.ll b/llvm/test/CodeGen/X86/tbm_patterns.ll
index d496b5075b8ab..5c7807973a798 100644
--- a/llvm/test/CodeGen/X86/tbm_patterns.ll
+++ b/llvm/test/CodeGen/X86/tbm_patterns.ll
@@ -909,9 +909,6 @@ define i64 @test_x86_tbm_blsic_u64_sle(i64 %a, i64 %b, i64 %c) nounwind {
ret i64 %t4
}
-; RUN: llc -mattr=+tbm < %s | FileCheck %s
-
-target triple = "x86_64-unknown-linux-gnu"
; CHECK-LABEL: test_blsic_original
; CHECK: blsicl
@@ -950,6 +947,8 @@ define i64 @test_blsic_64_optimized(i64 %x) {
ret i64 %3
}
+
+
define i32 @test_x86_tbm_t1mskc_u32(i32 %a) nounwind {
; CHECK-LABEL: test_x86_tbm_t1mskc_u32:
; CHECK: # %bb.0:
@@ -1210,10 +1209,10 @@ define i32 @blcic32_branch(i32 %x) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: blcicl %edi, %ebx
-; CHECK-NEXT: jne .LBB89_2
+; CHECK-NEXT: jne .LBB93_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: callq bar at PLT
-; CHECK-NEXT: .LBB89_2:
+; CHECK-NEXT: .LBB93_2:
; CHECK-NEXT: movl %ebx, %eax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
@@ -1233,10 +1232,10 @@ define i64 @blcic64_branch(i64 %x) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: blcicq %rdi, %rbx
-; CHECK-NEXT: jne .LBB90_2
+; CHECK-NEXT: jne .LBB94_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: callq bar at PLT
-; CHECK-NEXT: .LBB90_2:
+; CHECK-NEXT: .LBB94_2:
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
@@ -1256,10 +1255,10 @@ define i32 @tzmsk32_branch(i32 %x) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: tzmskl %edi, %ebx
-; CHECK-NEXT: jne .LBB91_2
+; CHECK-NEXT: jne .LBB95_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: callq bar at PLT
-; CHECK-NEXT: .LBB91_2:
+; CHECK-NEXT: .LBB95_2:
; CHECK-NEXT: movl %ebx, %eax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
@@ -1279,10 +1278,10 @@ define i64 @tzmsk64_branch(i64 %x) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: tzmskq %rdi, %rbx
-; CHECK-NEXT: jne .LBB92_2
+; CHECK-NEXT: jne .LBB96_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: callq bar at PLT
-; CHECK-NEXT: .LBB92_2:
+; CHECK-NEXT: .LBB96_2:
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
@@ -1302,10 +1301,10 @@ define i32 @blcfill32_branch(i32 %x) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: blcfilll %edi, %ebx
-; CHECK-NEXT: jne .LBB93_2
+; CHECK-NEXT: jne .LBB97_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: callq bar at PLT
-; CHECK-NEXT: .LBB93_2:
+; CHECK-NEXT: .LBB97_2:
; CHECK-NEXT: movl %ebx, %eax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
@@ -1324,10 +1323,10 @@ define i64 @blcfill64_branch(i64 %x) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: blcfillq %rdi, %rbx
-; CHECK-NEXT: jne .LBB94_2
+; CHECK-NEXT: jne .LBB98_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: callq bar at PLT
-; CHECK-NEXT: .LBB94_2:
+; CHECK-NEXT: .LBB98_2:
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
>From 287cc70cf7e14d0c57f6cf2ae34bfe9f6c3225c9 Mon Sep 17 00:00:00 2001
From: Logan Solonche <lsolonch at purdue.edu>
Date: Wed, 15 Jul 2026 15:34:34 -0400
Subject: [PATCH 4/6] Add CHECK patterns to BLSIC test functions
---
llvm/test/CodeGen/X86/tbm_patterns.ll | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/llvm/test/CodeGen/X86/tbm_patterns.ll b/llvm/test/CodeGen/X86/tbm_patterns.ll
index 5c7807973a798..0f250eb3277e3 100644
--- a/llvm/test/CodeGen/X86/tbm_patterns.ll
+++ b/llvm/test/CodeGen/X86/tbm_patterns.ll
@@ -913,6 +913,10 @@ define i64 @test_x86_tbm_blsic_u64_sle(i64 %a, i64 %b, i64 %c) nounwind {
; CHECK-LABEL: test_blsic_original
; CHECK: blsicl
define i32 @test_blsic_original(i32 %x) {
+; CHECK-LABEL: test_blsic_original:
+; CHECK: # %bb.0:
+; CHECK-NEXT: blsicl %edi, %eax
+; CHECK-NEXT: retq
%_2 = xor i32 %x, -1
%_0.i = add i32 %x, -1
%_0 = or i32 %_0.i, %_2
@@ -922,6 +926,10 @@ define i32 @test_blsic_original(i32 %x) {
; CHECK-LABEL: test_blsic_optimized
; CHECK: blsicl
define i32 @test_blsic_optimized(i32 %x) {
+; CHECK-LABEL: test_blsic_optimized:
+; CHECK: # %bb.0:
+; CHECK-NEXT: blsicl %edi, %eax
+; CHECK-NEXT: retq
%1 = sub i32 0, %x
%2 = and i32 %x, %1
%3 = xor i32 %2, -1
@@ -932,6 +940,10 @@ define i32 @test_blsic_optimized(i32 %x) {
; CHECK-LABEL: test_blsic_64_original
; CHECK: blsicq
define i64 @test_blsic_64_original(i64 %x) {
+; CHECK-LABEL: test_blsic_64_original:
+; CHECK: # %bb.0:
+; CHECK-NEXT: blsicq %rdi, %rax
+; CHECK-NEXT: retq
%_2 = xor i64 %x, -1
%_0.i = add i64 %x, -1
%_0 = or i64 %_0.i, %_2
@@ -941,6 +953,10 @@ define i64 @test_blsic_64_original(i64 %x) {
; CHECK-LABEL: test_blsic_64_optimized
; CHECK: blsicq
define i64 @test_blsic_64_optimized(i64 %x) {
+; CHECK-LABEL: test_blsic_64_optimized:
+; CHECK: # %bb.0:
+; CHECK-NEXT: blsicq %rdi, %rax
+; CHECK-NEXT: retq
%1 = sub i64 0, %x
%2 = and i64 %x, %1
%3 = xor i64 %2, -1
>From 3a7900c5ab474141fda8999638b5d287229ec90a Mon Sep 17 00:00:00 2001
From: Logan Solonche <lsolonch at purdue.edu>
Date: Wed, 15 Jul 2026 16:31:07 -0400
Subject: [PATCH 5/6] Remove hand-made CHECKS from testing
---
llvm/test/CodeGen/X86/tbm_patterns.ll | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/llvm/test/CodeGen/X86/tbm_patterns.ll b/llvm/test/CodeGen/X86/tbm_patterns.ll
index 0f250eb3277e3..3bf52f87e23c0 100644
--- a/llvm/test/CodeGen/X86/tbm_patterns.ll
+++ b/llvm/test/CodeGen/X86/tbm_patterns.ll
@@ -910,8 +910,6 @@ define i64 @test_x86_tbm_blsic_u64_sle(i64 %a, i64 %b, i64 %c) nounwind {
}
-; CHECK-LABEL: test_blsic_original
-; CHECK: blsicl
define i32 @test_blsic_original(i32 %x) {
; CHECK-LABEL: test_blsic_original:
; CHECK: # %bb.0:
@@ -923,8 +921,6 @@ define i32 @test_blsic_original(i32 %x) {
ret i32 %_0
}
-; CHECK-LABEL: test_blsic_optimized
-; CHECK: blsicl
define i32 @test_blsic_optimized(i32 %x) {
; CHECK-LABEL: test_blsic_optimized:
; CHECK: # %bb.0:
@@ -936,9 +932,6 @@ define i32 @test_blsic_optimized(i32 %x) {
ret i32 %3
}
-; 64-bit versions
-; CHECK-LABEL: test_blsic_64_original
-; CHECK: blsicq
define i64 @test_blsic_64_original(i64 %x) {
; CHECK-LABEL: test_blsic_64_original:
; CHECK: # %bb.0:
@@ -950,8 +943,6 @@ define i64 @test_blsic_64_original(i64 %x) {
ret i64 %_0
}
-; CHECK-LABEL: test_blsic_64_optimized
-; CHECK: blsicq
define i64 @test_blsic_64_optimized(i64 %x) {
; CHECK-LABEL: test_blsic_64_optimized:
; CHECK: # %bb.0:
>From 6e8fe6e2bf07d1ee7cbfc48d6b22f60d6b5162e1 Mon Sep 17 00:00:00 2001
From: Logan Solonche <lsolonch at purdue.edu>
Date: Thu, 16 Jul 2026 12:30:19 -0400
Subject: [PATCH 6/6] Address feedback 2: remove duplicate test and rename.
Also remove trailing whitespace and remove sub in favor of ineg
---
llvm/lib/Target/X86/X86InstrTBM.td | 4 +-
llvm/test/CodeGen/X86/tbm_patterns.ll | 93 ++++++++++-----------------
2 files changed, 36 insertions(+), 61 deletions(-)
diff --git a/llvm/lib/Target/X86/X86InstrTBM.td b/llvm/lib/Target/X86/X86InstrTBM.td
index a324925dc46cb..af07c3d90563a 100644
--- a/llvm/lib/Target/X86/X86InstrTBM.td
+++ b/llvm/lib/Target/X86/X86InstrTBM.td
@@ -125,9 +125,9 @@ let Predicates = [HasTBM] in {
def : Pat<(or GR64:$src, (add GR64:$src, -1)),
(BLSFILL64rr GR64:$src)>;
- def : Pat<(xor (and GR32:$src, (sub 0, GR32:$src)), -1),
+ def : Pat<(xor (and GR32:$src, (ineg GR32:$src)), -1),
(BLSIC32rr GR32:$src)>;
- def : Pat<(xor (and GR64:$src, (sub 0, GR64:$src)), -1),
+ def : Pat<(xor (and GR64:$src, (ineg GR64:$src)), -1),
(BLSIC64rr GR64:$src)>;
def : Pat<(or (not GR32:$src), (add GR32:$src, -1)),
diff --git a/llvm/test/CodeGen/X86/tbm_patterns.ll b/llvm/test/CodeGen/X86/tbm_patterns.ll
index 3bf52f87e23c0..b5643d10de39d 100644
--- a/llvm/test/CodeGen/X86/tbm_patterns.ll
+++ b/llvm/test/CodeGen/X86/tbm_patterns.ll
@@ -810,6 +810,17 @@ define i32 @test_x86_tbm_blsic_u32(i32 %a) nounwind {
ret i32 %t2
}
+define i32 @test_x86_tbm_blsic_u32_neg(i32 %x) nounwind{
+; CHECK-LABEL: test_x86_tbm_blsic_u32_neg:
+; CHECK: # %bb.0:
+; CHECK-NEXT: blsicl %edi, %eax
+; CHECK-NEXT: retq
+ %1 = sub i32 0, %x
+ %2 = and i32 %x, %1
+ %3 = xor i32 %2, -1
+ ret i32 %3
+}
+
define i32 @test_x86_tbm_blsic_u32_z(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: test_x86_tbm_blsic_u32_z:
; CHECK: # %bb.0:
@@ -865,6 +876,17 @@ define i64 @test_x86_tbm_blsic_u64(i64 %a) nounwind {
ret i64 %t2
}
+define i64 @test_x86_blsic_u64_neg(i64 %x) nounwind{
+; CHECK-LABEL: test_blsic_u64_neg:
+; CHECK: # %bb.0:
+; CHECK-NEXT: blsicq %rdi, %rax
+; CHECK-NEXT: retq
+ %1 = sub i64 0, %x
+ %2 = and i64 %x, %1
+ %3 = xor i64 %2, -1
+ ret i64 %3
+}
+
define i64 @test_x86_tbm_blsic_u64_z(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: test_x86_tbm_blsic_u64_z:
; CHECK: # %bb.0:
@@ -909,53 +931,6 @@ define i64 @test_x86_tbm_blsic_u64_sle(i64 %a, i64 %b, i64 %c) nounwind {
ret i64 %t4
}
-
-define i32 @test_blsic_original(i32 %x) {
-; CHECK-LABEL: test_blsic_original:
-; CHECK: # %bb.0:
-; CHECK-NEXT: blsicl %edi, %eax
-; CHECK-NEXT: retq
- %_2 = xor i32 %x, -1
- %_0.i = add i32 %x, -1
- %_0 = or i32 %_0.i, %_2
- ret i32 %_0
-}
-
-define i32 @test_blsic_optimized(i32 %x) {
-; CHECK-LABEL: test_blsic_optimized:
-; CHECK: # %bb.0:
-; CHECK-NEXT: blsicl %edi, %eax
-; CHECK-NEXT: retq
- %1 = sub i32 0, %x
- %2 = and i32 %x, %1
- %3 = xor i32 %2, -1
- ret i32 %3
-}
-
-define i64 @test_blsic_64_original(i64 %x) {
-; CHECK-LABEL: test_blsic_64_original:
-; CHECK: # %bb.0:
-; CHECK-NEXT: blsicq %rdi, %rax
-; CHECK-NEXT: retq
- %_2 = xor i64 %x, -1
- %_0.i = add i64 %x, -1
- %_0 = or i64 %_0.i, %_2
- ret i64 %_0
-}
-
-define i64 @test_blsic_64_optimized(i64 %x) {
-; CHECK-LABEL: test_blsic_64_optimized:
-; CHECK: # %bb.0:
-; CHECK-NEXT: blsicq %rdi, %rax
-; CHECK-NEXT: retq
- %1 = sub i64 0, %x
- %2 = and i64 %x, %1
- %3 = xor i64 %2, -1
- ret i64 %3
-}
-
-
-
define i32 @test_x86_tbm_t1mskc_u32(i32 %a) nounwind {
; CHECK-LABEL: test_x86_tbm_t1mskc_u32:
; CHECK: # %bb.0:
@@ -1216,10 +1191,10 @@ define i32 @blcic32_branch(i32 %x) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: blcicl %edi, %ebx
-; CHECK-NEXT: jne .LBB93_2
+; CHECK-NEXT: jne .LBB91_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: callq bar at PLT
-; CHECK-NEXT: .LBB93_2:
+; CHECK-NEXT: .LBB91_2:
; CHECK-NEXT: movl %ebx, %eax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
@@ -1239,10 +1214,10 @@ define i64 @blcic64_branch(i64 %x) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: blcicq %rdi, %rbx
-; CHECK-NEXT: jne .LBB94_2
+; CHECK-NEXT: jne .LBB92_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: callq bar at PLT
-; CHECK-NEXT: .LBB94_2:
+; CHECK-NEXT: .LBB92_2:
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
@@ -1262,10 +1237,10 @@ define i32 @tzmsk32_branch(i32 %x) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: tzmskl %edi, %ebx
-; CHECK-NEXT: jne .LBB95_2
+; CHECK-NEXT: jne .LBB93_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: callq bar at PLT
-; CHECK-NEXT: .LBB95_2:
+; CHECK-NEXT: .LBB93_2:
; CHECK-NEXT: movl %ebx, %eax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
@@ -1285,10 +1260,10 @@ define i64 @tzmsk64_branch(i64 %x) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: tzmskq %rdi, %rbx
-; CHECK-NEXT: jne .LBB96_2
+; CHECK-NEXT: jne .LBB94_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: callq bar at PLT
-; CHECK-NEXT: .LBB96_2:
+; CHECK-NEXT: .LBB94_2:
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
@@ -1308,10 +1283,10 @@ define i32 @blcfill32_branch(i32 %x) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: blcfilll %edi, %ebx
-; CHECK-NEXT: jne .LBB97_2
+; CHECK-NEXT: jne .LBB95_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: callq bar at PLT
-; CHECK-NEXT: .LBB97_2:
+; CHECK-NEXT: .LBB95_2:
; CHECK-NEXT: movl %ebx, %eax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
@@ -1330,10 +1305,10 @@ define i64 @blcfill64_branch(i64 %x) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: blcfillq %rdi, %rbx
-; CHECK-NEXT: jne .LBB98_2
+; CHECK-NEXT: jne .LBB96_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: callq bar at PLT
-; CHECK-NEXT: .LBB98_2:
+; CHECK-NEXT: .LBB96_2:
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
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