[llvm] [PowerPC]optimize the epilogue for restore non volatile cr fields (PR #202339)

[via llvm-commits]

================
@@ -1768,6 +1769,22 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
     }
   }
   assert(RBReg != ScratchReg && "Should have avoided ScratchReg");
+
+  auto BuildMoveToCR = [&]() {
+    assert(!Subtarget.is32BitELFABI() && "Non 32 Bit ELF ABI only.");
+    if (MustSaveCRs.size() == 1) {
+      // In Non 32 Bit ELF ABI, we are not required to restore all CR fields.
+      // If only one CR field was clobbered, use mtocrf to selectively
+      // restore just that field.
+      BuildMI(MBB, MBBI, dl, MoveToSingleCRInst, MustSaveCRs[0])
+          .addReg(TempReg, getKillRegState(true));
+    } else {
+      BuildMI(MBB, MBBI, dl, MoveToCRInst)
+          .addImm(255)
----------------
RolandF77 wrote:

You are mis-reading the UM. That same line is actually in the P8 UM. It says the following:

The architecture warns that updating a subset of the CR fields on an mtcrf instruction might have worse
performance than updating all of the fields. In the POWER8 processor, both the mtcrf instruction and the
mfcr instruction are emulated through the use of microcode templates. For best performance, software must
use the single-field variants (mtocrf and mfocrf) of these instructions as described in the Power ISA.

Note that this is the format of the UM. Since it says something in the architecture, follow it with actual processor aware info. Note also that as it pre-dates P10 the architecture info can not be based on actual P10 info.

The P9 UM also says to use single field form right after. However what we know about P9 instruction timing and properties does not seem to agree with this.

We have no reliable info that says the full mask is better on P10. Just using the multi-field form instruction is P10/P9 favourable, based on what we do know, which is that it is cracked no microcoded. There is no need to make it worse for P8 than needed.

https://github.com/llvm/llvm-project/pull/202339