[llvm] c9ec54a - [RISCV] Add DUMMY_REG_PAIR_WITH_X0->GPR copy to copyPhysReg. (#209964)

[via llvm-commits]

Author: Craig Topper
Date: 2026-07-16T09:04:58-07:00
New Revision: c9ec54a8a781166546c1001a8bfb2448fbacda44

URL: https://github.com/llvm/llvm-project/commit/c9ec54a8a781166546c1001a8bfb2448fbacda44
DIFF: https://github.com/llvm/llvm-project/commit/c9ec54a8a781166546c1001a8bfb2448fbacda44.diff

LOG: [RISCV] Add DUMMY_REG_PAIR_WITH_X0->GPR copy to copyPhysReg. (#209964)

The register coalescer can convert (extract_subreg x0_pair, sub_gpr_odd)
to a read of DUMMY_REG_PAIR_WITH_X0. This patch treats it the same as a
copy from X0.

I don't know if this is a good long term fix, but I think it's ok for
now. I will continue to look for other options.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    llvm/test/CodeGen/RISCV/rvp-simd-64.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 6512dde8fde23..50f548857a97b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -522,6 +522,15 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
     return;
   }
 
+  // Extracting from X0_Pair may create copies from DUMMY_REG_PAIR_WITH_X0.
+  if (SrcReg == RISCV::DUMMY_REG_PAIR_WITH_X0 &&
+      RISCV::GPRRegClass.contains(DstReg)) {
+    BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
+        .addReg(RISCV::X0)
+        .addImm(0);
+    return;
+  }
+
   if (RISCV::GPRF16RegClass.contains(DstReg, SrcReg)) {
     BuildMI(MBB, MBBI, DL, get(RISCV::PseudoMV_FPR16INX), DstReg)
         .addReg(SrcReg, KillFlag | getRenamableRegState(RenamableSrc));

diff  --git a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
index 164996a746c23..1355da7d5fe8a 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
@@ -5983,3 +5983,17 @@ define <4 x i16> @test_psabs_v4i16(<4 x i16> %a) {
   %res = call <4 x i16> @llvm.riscv.psabs.v4i16(<4 x i16> %a)
   ret <4 x i16> %res
 }
+
+define <2 x i32> @test_return_zero() {
+; RV32-LABEL: test_return_zero:
+; RV32:       # %bb.0:
+; RV32-NEXT:    li a1, 0
+; RV32-NEXT:    li a0, 0
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: test_return_zero:
+; RV64:       # %bb.0:
+; RV64-NEXT:    li a0, 0
+; RV64-NEXT:    ret
+  ret <2 x i32> splat (i32 0)
+}